Dependable Memory - Laboratoire Interface Capteurs ...
Dependable Memory - Laboratoire Interface Capteurs ...
Dependable Memory - Laboratoire Interface Capteurs ...
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
70 CHAPTER 3. DESIGN METHODOLOGY AND MODEL SPECIFICATIONS<br />
CPI*/CPI<br />
5<br />
4.5<br />
4<br />
3.5<br />
3<br />
2.5<br />
2<br />
1.5<br />
1<br />
0.5<br />
0<br />
0<br />
Permutation Benchmark<br />
(Random Errors Injection)<br />
CPI*/CPI (seq_duration=10) CPI*/CPI (seq_duration=50)<br />
CPI*/CPI (seq_duration=100)<br />
0 2.00E-04 4.00E-04 8.00E-04 1.60E-03 3.20E-03 6.40E-03 1.28E-02 2.56E-02<br />
Error Injection Rate (EIR)<br />
Figure 3.18: Model-I: additional CPI for benchmark group II<br />
From the simulation results of graphs 3.24, 3.25, 3.26 the CPI*/CPI ratio is smaller than model-I.<br />
In graph 3.24 with SD of 10 when EIR varies from 2e-4 to 2e-2, the additional CPI increases only by<br />
50% (on y-axis CPI*/CPI is 1.5) which means the execution time increases by only 50% even when<br />
the EIR becomes 100 times higher. This shows a good performance for the proposed architecture.<br />
For example, if we accept increasing by 50% the CPI, with SD of 10 there can be 20 errors per 1000<br />
instructions whereas with SD of 50 there will be only 6 errors per 1000 instructions. Furthermore, the<br />
SD has a direct impact on the size of journal memory in architecture and subsequently on its area.<br />
3.7.3 Comparison<br />
A comparison between model-I and model-II is summarized up in table 3.1. In both models, the<br />
effect of rollback is more dominant in higher SDs like 100 and 50. For example, as VP occurs after<br />
every hundred instructions in the SD= 100 there is more chances of provoking errors which rises the<br />
CPI*/CPI ratio more rapidly as compared to SD = 10 and 50. Since there is a large interval between<br />
the two consecutive VPs there is more chances for error occurrence which on the other hand increases<br />
the rate of re-execution of instructions.<br />
From the performance point of view in model-II, due to parallel access to the memory and journal<br />
in read operation the overall efficiency of the system is increased resulting in lower CPI ratios at<br />
higher EIRs as compared to model-I. Therefore, no clock-cycles are wasted if data is not found in the<br />
Journal. It has a better performance than our previous model as shown in the graphs 3.24, 3.25, 3.26.