Chapter 5 Robust Performance Tailoring with Tuning - SSL - MIT
Chapter 5 Robust Performance Tailoring with Tuning - SSL - MIT
Chapter 5 Robust Performance Tailoring with Tuning - SSL - MIT
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are tailored such that the mass is concentrated towards the center of the array by<br />
setting the batten height and width at the ends smaller than at the center. However,<br />
the severity of the tailoring is different for each design. The PT design is closet to<br />
the nominal design in that the widths are nearly equal along the truss and the bay<br />
heights only differ by 0.7 m from the end to the center. The RPT and RPTT designs<br />
are tailored more drastically in both bay width and height. The RPTT design has the<br />
largest difference between the end and center bay heights (2 m). The mount radius<br />
and isolator frequency are both decreased from nominal in the PT and RPT designs.<br />
These values are kept at nominal in the RPTT design since tuning is only considered<br />
on hardware in this optimization. The finite element models of the three designs are<br />
shown in Figures 6-11 through 6-13.<br />
Table 6.13: Design parameters for nominal and optimal TPF SCI designs.<br />
<strong>Tailoring</strong>, �x Total Mass<br />
h1 [m] h2 [m] w1 [m] w2 [m] rPM [m] fiso [Hz] [kg]<br />
Nominal 1.0 1.0 2.0 2.0 0.05 8.0 2679.0<br />
PT 1.824 2.522 1.760 1.780 0.03 6.56 2506.6<br />
RPT 0.754 2.52 1.34 2.25 0.02 6.77 2264.2<br />
RPTT 0.50 2.56 1.48 2.34 0.05 8.0 2801.2<br />
The RMS OPDs between collectors 1 and 4 of each of the three designs are eval-<br />
uated for the cases of nominal and worst-case uncertainty. The results are listed in<br />
Table 6.14 and shown graphically in Figure 6-14. The nominal performance is in-<br />
dicated by circles and the worst-case performance <strong>with</strong> solid error bars. As in the<br />
development model, the PT design exhibits the best nominal performance (2.90 nm),<br />
but is sensitive to uncertainty as evidenced by the large performance range between<br />
the error bars. The nominal performance of the RPT design is worse than that of the<br />
PT design (3.79 nm), but it suffers the least performance degradation at the worst-<br />
case uncertainty vertex. The nominal and worst-case performances of the RPTT are<br />
worse than those of either the PT or RPT designs. This result is due, in part, to the<br />
fact that the tuning parameters are not part of the nominal RPTT design since they<br />
are considered explicitly during hardware tuning.<br />
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