Chapter 5 Robust Performance Tailoring with Tuning - SSL - MIT

indicating that this requirement is aggressive for this system at this uncertainty level.
Therefore, to guarantee success through tailoring and tuning the system should be
designed for maximum tunability with a robustness weight at or near α = 0. However,
if this requirement is relaxed to 250µm then less tuning authority is necessary to
meet requirements, and a higher weight, up to α =0.4, can be placed on robustness.
Placing the maximum weight possible on robustness produces a design with a worst-
case performance prediction that is closer to the requirement increasing the chance
that the hardware will not need tuning at all.
5.3.2 Hardware Simulations
The results presented thus far indicate that the RPTT is more tunable than both
the PT and RPT designs at the worst-case uncertainty vertex. This result is not
surprising given the formulations of the design optimizations. PT does not consider
uncertainty at all, and RPT is only concerned with being robust to uncertainty at
the worst-case vertex and does not take advantage of hardware tuning. The RPTT
formulation anticipates the decrease in uncertainty effected by building hardware and
incorporates that benefit into the design by allowing different tuning configurations
at each uncertainty vertex and minimizing the worst-case tuned performance. As a
result, it is guaranteed that RPTT is tunable at the uncertainty vertices, but it is
unclear if that assumption holds throughout the rest of the uncertainty space. In this
final section, a series of hardware simulations are run to evaluate the performance of
the designs across all of the uncertainty space.
The algorithm used to generate the hardware simulations is given in Figure 5-6.
The outer loop in the algorithm is over the number of simulations desired, nsims.
For each simulation an uncertainty realization, �pMC, is chosen randomly from the
uncertainty model. Recall from Equation 3.1 that the uncertainty values in the SCI
development model are assumed to be uniformly distributed about the nominal val-
ues within bounds of ±∆%. A hardware simulation is generated for each of the three
designs, PT, RPT and RPTT, by applying �pMC to the models and evaluating the
performance, σHW. The hardware performance is then compared to the requirement.
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