eldo_user

IBIS Models Support in Eldo
IBIS Component
• c_comp_pu=value, c_comp_pd=value, c_comp_pc=value, c_comp_gc=value
These four keywords are optional. If one of these keywords is specified with a non-zero
value; c_comp capacitor will be split up to four parts. Values are dimensionless numbers
between 0 and 1, and sum of them should be equal to 1. The default is 0 for the unspecified
values.
• use_fall_wvf= 0|1|2, use_rise_wvf= 0|1|2
0
Use the ramp for the falling/rising transitions.
1
Use one waveform for the falling/rising transitions.
2
Use two waveforms for the falling/rising transitions.
The default behavior is to use the first two waveforms if more than one waveform is
specified in the IBIS model, use one waveform if only one is specified, and to use ramp if no
waveforms are specified.
• all_sm=YES|NO
For Series/Series_Switch buffers. Setting all_sm to NO makes Eldo use only the first
non-zero Vds table to generate the current of Series MOSFET elements in the Series buffer.
The default is YES.
• keep_vds_monotonic=NO|YES
For Series/Series_Switch buffers. Setting keep_vds_monotonic to YES will keep the Ids
current monotonic versus Vds values for a given Vgs. Default is NO.
• keep_vgs_monotonic=NO|YES
For Series/Series_Switch buffers. Setting keep_vgs_monotonic to YES will keep the Ids
current monotonic versus Vgs values for a given Vds. Default is NO.
• rx_logic=0|1
For Input or IO buffers; if the input voltage on a_signal port is between Vinl and Vinh
thresholds then rx_logic will control the output voltage on the d_receive port. When
rx_logic=0 (default), the voltage on the d_receive port will be 0.5V (representing logic
"X"). When rx_logic=1, the voltage on the d_receive port will have the same value (state) as
the previous time step.
Note
If there are hysterises thresholds (Vinl+, Vinl-, Vinh+, and Vinh-) under the
[Model Spec] keyword, then rx_logic has no effect.
768
Eldo® User's Manual, 15.3