eldo_user

IBIS Models Support in Eldo
Component
Component
Eldo can simulate IBIS devices either individually or in the overall component. The component
simulation means creating all the buffers inside the component, connecting these buffers to the
appropriate nodes and power buses, creating the package parasitics and connecting buffer die
pads to the package parasitics.
Several keywords and sub-parameters in the IBIS file are used in a component simulation in
addition to that used in the individual buffer simulation:
• [Pin Mapping] is used to define the buffers sharing the same power/ground bus.
See “Pin Mapping” on page 745.
• [Series Pin Mapping] is used to join two die pads by a series buffer and [Series Switch
Groups] is used to define switching combinations of series switches.
See “Series Pin Mapping and Series Switch Groups” on page 746.
• [Circuit Call] and [Node Declarations] create subcircuits from external circuit models
written in SPICE or Verilog-A language, and make their interconnections.
See “Node Declarations and Circuit Call” on page 747.
• [Package Model] defines an advanced package model, taking coupling effects into
account.
Pin Mapping
When the input of a buffer(s) changes from High to Low, the output driver current (Ldi/dt)
creates a fluctuation between the core ground and power buses. This creates a pulse that can
affect static buffer(s) output, causing the receiver(s) to switch inappropriately. A similar effect
occurs when the input of a buffer(s) changes from Low to High. The difference between the
core ground and power is referred to as “ground bounce.” The amount of ground bounce is
dependent on the number of outputs changing state at the same time and thus the ground bounce
may also be called “simultaneous switching output noise” (SSON).
The [Pin Mapping] keyword, in the IBIS file, contains information on how power supplies are
connected to individual buffers or groups of buffers that can be used for predicting SSON. The
bus connections (from buffer nodes to supply or ground nodes) described by [Pin Mapping] are
assumed as ideal shorts, and do not override parasitic information given for power and/or
ground pins. Figure 17-13 indicates how the model is constructed, the [Pin Mapping] contains
information about the bus connection from buffer nodes to supply/ ground nodes. For example,
pins 8 and 12 are connected to the Power bus; pins 10 and 38 are connect to the Ground bus; and
the models with signal terminals connected to pins 35 and 40 use these buses for their voltage
supplies.
Eldo® User's Manual, 15.3 745