eldo_user

IBIS Models Support in Eldo
Buffers
Figure 17-7. Pseudo-Differential Output Buffer Consisting of Two Single-Ended
Output Buffers
The two inputs are tied together and the overall differential buffer has one input and two
outputs. Positive differential delay means the non-inverting output is delayed with respect to the
inverting output. Inverting differential delay means inverting output is delayed with respect to
the non-inverting output.
True Differential Buffers
The native IBIS does not support true differential buffers, they are only supported using the
external model format created using SPICE or Verilog-A.
SPICE or Verilog-A formatted models are pure analog. Eldo is responsible for handling the A/D
and D/A conversions as shown in Figure 17-8. Specification of these A/D and D/A blocks are
defined in the IBIS file.
Eldo® User's Manual, 15.3 741