eldo_user

IBIS Models Support in Eldo
Buffers
I/O and I/O_ECL Buffers
Figure 17-4 shows the model of an I/O buffer. The d_enable signal determines if the buffer will
operate as an Input or Output buffer. If the buffer is active low, then it will behave as an Output
buffer if d_enable < 0.5 V and as an Input buffer otherwise. If the buffer is active high, then it
will behave as an Output buffer if d_enable > 0.5 V and as an Input buffer otherwise.
Figure 17-4. I/O Buffer Model Building Blocks
When behaving as an Output buffer, I/O_ECL buffer differs mainly from I/O buffer in that the
a_pdref is internally connected to the a_puref; that is, pull-up and pull-down share the same
power reference. I/O and I/O_ECL buffers also differ in the conventions related to [Pulldown],
[Temperature Range], [Pin Mapping] keywords and the measuring conditions of the switching
characteristics. Otherwise, if behaving as an Input buffer, I/O and I/O_ECL buffers differ in the
default values of Vinl and Vinh (see “Input and Input_ECL buffers” on page 735 for details).
3_state and 3_state_ECL Buffers
The model of a 3_state buffer is show in Figure 17-5. The 3_state buffer is very similar to the I/
O buffer but does not have a digital output. It either works as an output buffer when enabled or
high impedance when not enabled. The high impedance state is described by the Power Clamp,
GND Clamp and die capacitance, C_comp.
738
Eldo® User's Manual, 15.3