eldo_user

Electrothermal Simulation
Verilog-A Support
• Implicit .TEMPNODE specification—a SPICE resistor is replaced by the Verilog-A
instance xra:
*Verilog-A Electrothermal simulation example
* I(V1) = -2.5607996733E-02
* TEMP(X1) = 4.6050301765E+01 Celsius
.hdl resistor.va
.SUBCKT test a b
xra a b resistor RS=1k tc1 = 0.1
.ENDS
.tempnode subckt=test thnode=thn
.option numdgt = 10
v1 a 0 100
* instantiate the thermal subcircuit:
* 2 pins to connect
x1 a b test
r2 b 0 1k
* connect the implicit thermal node
* to the thermal network
rthn x1.thn 0 10
.op
.extract dc i(v1)
.extract dc TEMP(x1)
.end
• An example of the $temperature function usage is shown in the small resistor code
below. In this model, the temperature is evaluated at each iteration and the value of the
resistor updated accordingly. This may have a certain cost.
`include "disciplines.h"
module resistor1 (a,b);
electrical a , b;
inout a,b;
parameter real RS = 0;
parameter real TC1 = 0;
real rtval;
analog begin
rtval = RS*(1.0 + TC1*($temperature - 300.15));
I(a,b)