eldo_user

The .TEMPNODE statement can also be specified outside the subcircuit.
Electrothermal Simulation
Verilog-A Support
In the second example below, a SPICE resistor is replaced by a Verilog-A instance.
• Case of $temperature specified in @initial_step
Examples
To avoid multiple evaluations of some variables, the @initial_step of a Verilog-A model
is commonly used. In a standard (non electrothermal) simulation, the temperature of the
circuit is supposed to be constant during the entire simulation.
For electrothermal simulation, Eldo allows the update of the local temperature without
modifying the model. All variables that are dependent of the temperature and are present
only in the initial step statement, are updated at each temperature variation inside the
surrounding subcircuit.
This reduces the evaluation cost of the resistor model with $temperature in the @initial
step compared to the first model.
In the third example below, resistor1 and resistor2 give the same electrothermal
simulation results.
Examples of .TEMPNODE specifications with Verilog-A models:
• Explicit .TEMPNODE specification—a SPICE resistor is replaced by the Verilog-A
instance xra:
* Verilog-A Electrothermal simulation example
* I(V1) = -2.5607996733E-02
* TEMP(X1) = 4.6050301765E+01 Celsius
.hdl resistor.va
.SUBCKT test a b thn
.tempnode thn
xra a b resistor RS=1k tc1 = 0.1
.ENDS
.option numdgt = 10
v1 a 0 100
* instantiate the thermal subcircuit:
* 3 pins to connect
x1 a b thn test
r2 b 0 1k
* connect the explicit thermal node
* to the thermal network
rthn thn 0 10
.op
.extract dc i(v1)
.extract dc TEMP(x1)
.end
Eldo® User's Manual, 15.3 721