eldo_user

Optimization
Robust Optimization Using Corners
* SS_33 : Slow NMOS Slow PMOS model for 3.3V devices
.ALTER SS_33 : SLOW NMOS SLOW PMOS MODEL
.LIB ./cln90g_lk.eldo SS_33
* FF_33 : Fast NMOS Fast PMOS model for 3.3V devices
.ALTER FF_33 : FAST NMOS FAST PMOS MODEL
.lib ./cln90g_lk.eldo FF_33
* SF_33 : Slow NMOS Fast PMOS model for 3.3V devices
.ALTER FS_33 : FAST NMOS SLOW PMOS MODEL
.LIB ./cln90g_lk.eldo FS_33
* FS_33 : Fast NMOS Slow PMOS model for 3.3V devices
.ALTER FS_33 : SLOW NMOS FAST PMOS MODEL
.LIB ./cln90g_lk.eldo SF_33
Analyses and Design Objectives
Two analyses were specified to define the following design objectives:
• A transient analysis to extract the output voltage.
.EXTRACT TRAN LABEL=RSLOPE SLOPE(V(OUT),0,0,140N)
+ GOAL=80.0E6 WEIGHT=1000.0
• A DC analysis for extracting the IDS current.
.PARAM SCAL_I=1E4 ! INVERSE OF TYPICAL VALUE
.EXTRACT DC LABEL=SCAL_IBIAS SCAL_I*ID(M16)
+ GOAL=MINIMIZE WEIGHT=1.0
The constant parameter SCAL_I was used to rescale the extracted measure IBIAS. The values
taken by RSLOPE and SCAL_IBIAS have the same order of magnitude. The specified weight
for the measure RSLOPE was introduced to find a solution that minimize the rise time at the
expense of larger IBIAS values. Users can experiment with different choices of weights.
Design Variables and the Optimization
A shrink parameter WS is used for the width of each MOS instantiated in the netlist. The
capacitor is also optimized:
.PARAMOPT
+ WS=(2,0.5,4)
+ C_COMP=(1p,0.01p,100p)
This example must be run with the following commands:
.OPTIMIZE TOL_OPT=1E-2
.OPTION OPSELDO_ALTER
where the option OPSELDO_ALTER informs Eldo that optimization must be performed on all
.ALTER sections. The results of the optimization are placed in the optimization file with the
extension .otm.
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Eldo® User's Manual, 15.3