eldo_user

Optimization
Examples of Circuit Optimization
Examples of Circuit Optimization
A number of example files are provided to illustrate the Eldo Optimizer.
See Table 13-4 for filenames and descriptions of the example files provided in your installed
directory: $MGC_AMS_HOME/examples/optimizer/
Table 13-4. Basic Examples of Circuit Optimization
Example File name Description
Designing a Low Noise Amplifier
(LNA)
lnaopt.cir
Optimization using AC, Noise and
SST analyses
Fourband Filter Optimization fourband.cir Optimization of a filter response
MOS Characterization nmos.cir Double DC sweep optimization and
ALTER blocks
Robust Optimization Using Corners aop_optim.cir Optimization of a 2-stage operational
amplifier using ALTER blocks
Setup Time Computation
Optimization of the setup time
computation of a flip-flop
Designing a Low Noise Amplifier (LNA)
Netlist file: lnaopt.cir
The Low Noise Amplifier (LNA) architecture is a fully balanced dual-gain amplifier for
achieving gain, linearity, and the noise specifications for a Zero-IF receiver architecture. Output
power matching is not required since the output load is given by the integrated mixer.
This example will show how the Eldo optimizer can be used for a LNA. The architecture of the
LNA is based on the 2.45GHz Switched-Gain CMOS LNA [6]. The high-gain stage is a fully
balanced cascade configuration with an integrated LC tank as the load. This design reduces the
Miller effect and improves isolation (-S12). The low-gain stage consists of two NMOS devices
used as switches to achieve the required linearity and insertion loss.
The main characteristics are: Voltage Gain (AV), Input Power Matching (S11), Noise Figure
(NF), and Input Third Order Intercept Point (IIP3). The circuit parameters are:
• Input Network Model (CPIN1, CPIN2, LSIN, CSIN).
• Source Inductor (associated with serial resistance).
• NMOS Width (composed of 10mm length fingers).
The input network consists of a serial capacitor (CSIN) used to isolate the LNA DC from the
input. A p-network (consists of CPIN1, CPIN2, LSIN) enables simultaneous input power and
noise matching. Changing the source inductor (LS) and the width of the NMOS through the
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Eldo® User's Manual, 15.3