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SPEF File Structure
Post-Layout Simulation
SPEF File Structure
Input for: .SPEF_INCLUDE command.
The SPEF file is an alternative format for parasitic information extracted from layout.
Format
The file begins with a header. It includes various information on the tools used for extraction.
The important fields are the following:
*SPEF "IEEE 1481-1999"
*DESIGN "name"
*DIVIDER /
*DELIMITER :
If used, the DESIGN field is the name of the subcircuit on which the parasitics will be applied.
The DIVIDER field is the hierarchical divider, and the DELIMITER is used in subnode names.
The following section contains the units used in the body of the file:
*T_UNIT
*C_UNIT
*R_UNIT
*L_UNIT
1 NS
1 PF
1 OHM
1 HENRY
Time unit must be one of NS or PS; capacitance: PF or FF; resistor: OHM or KOHM; and
inductance: HENRY, MH or UH. They are all mandatory.
The next section contains the name mapping. You can map any net to a number. This is useful
when net names are very long.
*NAME_MAP
*1 N1
*2 N2
*3 NETWITHALONGNAME
*4 OTHER_NET
The next section contains the ground nets:
*GND_NETS VSS
The following section contains the nodes which are considered as ports, with their direction, and
an eventual load behind:
*PORTS
N0 O *L 10
N1 O
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Eldo® User's Manual, 15.3 399