eldo_user

Chapter 10
Post-Layout Simulation
This chapter describes the DSPF (Detailed Standard Parasitic Format) backannotation and
network reduction capabilities for post-layout simulation in Eldo.
Post-Layout Simulation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
DSPF Backannotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
DSPF File Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Parasitic Network Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Eldo Post-Layout Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Eldo Post-Layout Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
DSPF Backannotation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
SPEF Backannotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
SPEF File Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
SPEF File Example for Corners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Eldo Reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Basic Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Parameters Controlling the Reduction Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Reduction Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Reduction Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Reduction Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Reduction Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Post-Layout Simulation Overview
Eldo enables you to verify design functionality and timing including the effects of physical
layout. To include these effects of layout, you must generate a netlist that includes parasitics
extracted from layout using an extraction tool such as xCalibre. The extracted parasitic
information is included in the netlist in the form of large networks of passive resistors,
capacitors, and inductors connected to the transistors or other active objects of the circuit. Due
to the large number of elements that they contain, such parasitic networks strongly constrain
post-layout simulation both in terms of memory and CPU time.
A typical analog post-layout flow is shown in Figure 10-1:
Eldo® User's Manual, 15.3 389