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Introduction to Eldo<br />

Getting Started With the Eldo Simulation Flow<br />

During a mixed-signal, or pure analog, simulation, Questa ADMS uses Eldo to simulate the<br />

following:<br />

• A mixed-signal design that includes SPICE subcircuits as components.<br />

• A SPICE netlist that includes VHDL-AMS and VHDL design entities or Verilog-AMS<br />

and Verilog modules as components.<br />

• A pure SPICE netlist.<br />

See the Questa ADMS User’s Manual.<br />

Verilog-A<br />

Verilog-A is an analog subset of the Verilog-AMS language, for use to help design analog<br />

systems with high-level behavioral descriptions, as well as structural descriptions of systems<br />

and components. The default Verilog-A implementation in Eldo is the same as that used by<br />

Verilog-AMS in Questa ADMS. Eldo and Questa ADMS can share the same compiled Verilog-<br />

A modules.<br />

See the Eldo Verilog-A User’s Manual.<br />

Waveform Analysis<br />

The EZwave graphical post-processor enables waveform analysis and post-processing of<br />

simulation results. The native waveform format of EZwave, called “wdb,” is extremely efficient<br />

for manipulating huge databases. EZwave can load gigabytes of data in seconds. EZwave can<br />

also load most popular waveform formats, and operates on both analog and digital signals.<br />

See the EZwave Users Manual.<br />

Viewing ASCII Simulation Output Files<br />

You can use the AMS Results Browser to view simulation results and associated files.<br />

Depending on the file format, results may be sorted, filtered, grouped, searched, printed, copied,<br />

and exported.<br />

The AMS Results Browser is mainly intended to be used to view Eldo outputs, but you can also<br />

use it to view SPICE input files and any text file.<br />

See the AMS Results Browser.<br />

Getting Started With the Eldo Simulation Flow<br />

The basic Eldo simulation flow is to setup a .cir netlist file, run the Eldo simulation on the<br />

netlist file, then analyze the generated results.<br />

This example consists of a simple cascade of three inverters. Figure 1-1 and Figure 1-2 show<br />

the circuit diagram for the cascade together with the inverter subcircuit. To create the Eldo<br />

netlist, node names must be assigned to the circuit. The complete netlist is provided.<br />

Eldo® User's Manual, 15.3 31

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