eldo_user

Introduction to Eldo
Overview of Eldo
• Extensive device model libraries including leading MOS, bipolar and MESFET
transistor models such as: BSIM3v3.x, BSIM 4, MM11, Mextram, HICUM, and PSP.
• TSMC Model Interface (TMI) support for TMI1 and TMI2.
• IBIS (I/O Buffer Information Specification) model support.
• Waveform analysis and post-processing of simulation results with the EZwave ®
graphical post-processor.
• Integration into Mentor Graphics Custom IC flow, consisting of Pyxis® Schematic for
schematic capture, Pyxis Layout for the layout side, and Calibre/Calibre xRC for DRC/
LVS and extraction. This flow provides a complete, front-to-back design and
verification environment for analog, mixed-signal and RF.
• Integration into Cadence’s Analog Design Environment with Artist Link ® .
Analog Simulation Capabilities
Eldo uses a unique partitioning scheme that enables the use of different algorithms on different
portions of a design. It provides a flexible control of simulation accuracy using a wide range of
device model libraries, and gives a high accuracy yield in combination with high speed and high
performance.
See “Getting Started With the Eldo Simulation Flow” on page 31.
RF Capabilities
Eldo RF extends the capabilities of the Eldo simulator with added extensions for RF simulation
to enable the fast large-signal Steady-State analysis (SST analysis) of high frequency electronic
circuits. A set of dedicated algorithms are provided to accurately and efficiently handle the
multi-GHz signals in modern wireless communication applications. Of importance to the RF
designer, you can extract large-signal S parameters, and W elements and multiple lossy
transmission lines are supported.
See the Eldo RF User’s Manual.
Mixed-Signal Simulation
Questa ADMS incorporates Eldo Classic and Eldo Premier to efficiently simulate mixed-signal
designs within a unified simulation environment. Questa ADMS extends the familiar Questa
verification platform with analog and mixed-signal standard languages. You can mix all
languages in a single hierarchy; and you can combine VHDL-AMS, Verilog-AMS, VHDL,
Verilog, SystemVerilog, SPICE and SystemC anywhere and at any level in the design. The
testbench may be SPICE, an analog or mixed-signal language, or a digital language.
In Questa ADMS, you can use digital units that have been previously compiled and simulated
by Questa without any modification. You can use SPICE subcircuits anywhere in the design
hierarchy for greater flexibility in modeling.
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Eldo® User's Manual, 15.3