eldo_user

Examples
Tutorial—High Impedance Fault Detection of a PLL Circuit
4. From the table, it is easy to find out which nodes have the highest average impedance
values. The first instance in the list points to the PLL input control node TPROG1_1,
which is a subnode inserted through DSPF backannotation. In second and third positions
in the list are the gates of MOS transistors M1 and M2 instantiated within
XPLL.XTEST.XDUM1.
The figure below illustrates the backannotated node TPROG1, highlighted in red:
5. To find out why such a HiZ value is reported by Eldo, look at the contents of the DSPF
file dspf_pll_v01.dspf. There is a mistake in the parasitic values in the corresponding
DSPF section for net TPROG1:
Eldo® User's Manual, 15.3 1361