LINEPULS & LINECOD catalogue 2016 in English

LINECOD
Absolute output circuits and fieldbus interfaces
“MSB left aligned” protocol allows to left align the bits, beginning from MSB to LSB; MSB
is then sent at the first clock cycle. If the number of clock signals is higher than the data bits,
then unused bits are forced to low logic level (0) and follow the data word.
The number of clocks to be sent to the encoder must equal the number of data bits at least,
anyway it can be higher, as stated previously. The great advantage of this protocol over the
LSB RIGHT ALIGNED format is that data can be transmitted with a minimum time loss and
the TM monoflop time can immediately follow the data bits without any additional clock
signal. In specific encoders the SSI word can further provide an error bit and the parity bit.
The error bit follows the position information and is intended to communicate the normal
(“1” high logic level) or fault (“0” low logic level) state of the Slave. Parity bit is an optional
function used for checking in a very basic way whether errors occur during transmission (for
further information refer to page 41).
“MSB LEFT ALIGNED” protocol
MSB LEFT ALIGNED protocol scheme (BG-, GG- and G1- output circuit codes)
Advantages: simple, efficient and cost-effective, less conductors, less electronic components,
transmission rate up to 2 Mbit/s, circuit can be galvanically insulated by means of
optocouplers, increased noise immunity, long cable runs, SSI encoders can be easily integrated
into conventional fieldbus or industrial Ethernet networks using IF55 converters (see
on page 47).
Disadvantages: point-to-point architecture, transmission speed lower than in competing
parallel interface.
Recommended input circuit
SSI cable length
For max. cable lengths refer to the section “Cable lengths” on page 44.
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