AMSV Newsletter 2015

A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC
In ISSCC 2015 & JSSC 2016
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan (Ben) U, and Rui Paulo Martins
From Data Conversion and Signal Processing research line
Motivation
Architecture
For 60GHz-band receivers and serial links applications.
The SAR ADC is a well-known energy-efficient architecture
while the speed of SAR ADCs can be further improved
with the comparator interleaving, loop-unrolled
asynchronous loop or the multi-bit per cycle.
The Flash ADC is known as the fastest ADC architecture
but power hungry. By adopting interpolation or calibration,
outstanding energy efficiency can also be accomplished
under advanced technology nodes.
In a standalone flash or SAR architecture, speed and
energy efficiency are still limited due to their inherent
characteristics; therefore, they are often combined with
time interleaving to achieve a breakthrough.
Time interleaving can be a very effective way to increase
the sampling rate of the ADC but it induces extra design
complexity and conversion non-idealities especially with
large numbers of interleaving channels.
V in,P
V in,N
Input
4
En, chX
4×
Channels
Clock
Gen.
Common
Clk
Bootstrap
2
V ref,N/V ref,P
Decoder & BDCO
3b/cycle SAR
Segmentation Logic
8
DAC Array
DAC Array
DAC Array
DAC Array
Dummy Latch
Dynamic
Pre-amp.
interpolation
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
On-Chip Offset Calibration Cal Ctrl.
6
14
6
MUX
Final Output
Codes
The power required for the digital gain and timing corrections
is prohibitive at 6b resolution.
Implementation
Verification
40
30
20
10
0
SNDR/SFDR (dB)50
43.5
30.78
SFDR
SNDR @Nyquist
43.12
30.76
42.95
30.66
1 2 3
#Sample
Sample #2, fs = 5 Gs/s
45
SNDR/SFDR (dB)
40
35
30
25
SFDR
SNDR
20
0 0.5 1.0 1.5 2.0 2.5 3.0
Input Frequency (GHz)
ISSCC’10[1] VLSI’13[5] VLSI’12[6] ISSCC’14[25] A-SSCC’14[26] This work
Architecture Ti-pipelined B-S Flash Flash Ti-SAR Ti-SAR Ti-Multi-bit SAR
Process 40nm 32nm SOI 40nm 28nm UTBB FDSOI 32nm SOI
65nm
Supply voltage (V) 1.1 0.85 1.1 1.0
1.1 1.0 1.2
10
36
5 6
Sampling rate (GS/s) 2.2 5
3
Resolution (bit) 6 6
Power (mW) 2.6 11
SNDRminin Nyq. band (dB) 29.6 33.1
Input cap.(fF) 200 72
FoM@ Nyq.(fJ/conv.-step) 40.0 100.48
Active area (mm 2 ) * 0.03 * 0.02 * 0.021
Calibration
Off-chip Off-chip Off-chip
*without Calibration **with Calibration
6 6
6
6
8.5 32
110 5.5 10.6
30.9 33.8
31.6 30.25 30.13
135 100
N/A
31
59.33 81
98
39 67.37
* 0.009 ** 0.048 * 0.008 (**
0.09)
Off-chip On-chip
On-chip