AMSV Newsletter 2015
AMSV Newsletter 2015
AMSV Newsletter 2015
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In ESSCIRC 2014 & JSSC 2016<br />
An 11b 450 MS/s 3-way Time-Interleaved Sub-ranging Pipelined-<br />
SAR ADC in 65nm CMOS<br />
Yan Zhu, Chi-Hang Chan, Seng-Pan (Ben) U, and Rui Paulo Martins<br />
From Data Conversion and Signal Processing research line<br />
Motivation<br />
Architecture<br />
The SAR architecture demands a stringent noise requirement<br />
for the comparator design while aiming for<br />
high resolution.<br />
The mismatch spurs due to the timing, offset and<br />
gain in TI SAR limit both signal-to-noise distortion<br />
ratio (SNDR) and spurious-free dynamic range<br />
(SFDR).<br />
The pipelined-SAR ADCs still maintain their superiority<br />
in power efficiency with high resolution in deep<br />
sub-micron technology. The implementation of low<br />
stage-gain (G) relaxes the desired noise requirement<br />
in the comparator and balances the trade-off between<br />
the power dissipation and gain-bandwidth<br />
product (GBW) requirement of the Op-Amp.<br />
Time skews on the other hand are tolerated by design<br />
constraint or avoided through architecture optimizations.<br />
Proposed hybrid ADC architecture and multiple<br />
shared elements among the TI channels.<br />
Implementation<br />
Verification