AMSV Newsletter 2015

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Adhesion Promoter for a Multi-Dielectric-Layer on a Digital Microfluidic Chip Jie Gao, Tianlan Chen, Cheng Dong, Yanwei Jia, Pui-In Mak, Mang-I Vai, and Rui P. Martins From Multidisciplinary Research Area (Microfluidic) In UK Royal Society of Chemistry – Advances <strong>2015</strong> Motivation Technique A silane-based adhesion promoter suitable for a multi-dielectric-layer coating on a digital microfluidic chip is reported. It measures >100 improvement in chip lifetime via transforming the bonding of the dielectric layers (Ta 2 O 5 and Parylene C) from nonspecific to chemical. The refined chip-fabrication protocol also allows low EWOD actuation voltages down to 5 V. Verification I Verification II
In IEEE Transactions on Electron Devices <strong>2015</strong> A Precision CMOS Voltage Reference Exploiting Silicon Bandgap Narrowing Effect Bo Wang, Man-Kay Law and Amine Bermak From Wireless research line Motivation Architecture Conventional precision voltage references (BGRs) can be achieved by multiple temperature trimmings and/or power hungry curvature correction circuits that inevitably increases cost and energy efficiencies. We exploit the intrinsic temperature characteristics of the BJT itself to reduce the BJT curvature and perform curvature correction using the silicon bandgap narrowing effect so as to avoid the power overhead of curvature correction circuits by batch trimming. Measurement results show that the BJT curvature can be effectively reduced from its inherent 3.6 mV to 1.4 mV. The proposed BGR measures a minimum temperature coefficient of 8.7 ppm/° C and 4.1 ppm/°C from −55 °C to 125 °C after batch trimming and curvature trimming, respectively. Proposed BGR Topology with curvature reduction using bandgap narrowing effect Relationship between voltage and temperature showing the curvature reduction and correction with convex (left) and concave (right) BJT intrinsic curvatures. Implementation Verification (a) Complete schematic of the proposed BGR using bandgap narrowing effect. (b) Chip micrograph of the proposed BGR (a) Inaccuracy of V REF from 12 samples without trimming and after batch trimming resistor R c1 at 25 °C (dotted lines indicates ± 3σ values); (b) Measured BJT intrinsic curvature and V REF before and after the curvature compensation.
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AMSV Newsletter 2015

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