AMSV Newsletter 2015

State Key Lab of Analog and Mixed-Signal VLSI (SKL AMS-VLSI)
Newsletter
Motto: “Locally, from (World) Quality towards (National) Quantity”
座 右 銘 : 立 足 本 土 、 人 才 培 養 , 以 世 界 級 質 量 創 建 國 家 級 規 模
Year 5
No . 5
2015 Milestones
March 2016
Co-Funded by
Macao Science and Technology
Development Fund (FDCT)
Events
A delegation led by Wan Gang, Vice Chairman of the Chinese People’s Political Consultative Conference and Minister
of Science and Technology, visited the University of Macau’s (UM) State Key Laboratory of Analog and Mixed-Signal
VLSI (SKL AMS-VLSI) on 4 December 2015
FDCT/MOST Annual Meeting in Chengdu, China, Chaired by Cao Jianlin, Vice-Minister of Science & Technology on
November 2015
The University of Macau’s (UM) State Key Laboratory of Analog and Mixed-Signal VLSI (SKL AMS-VLSI) held in
April 2015 the 2nd meeting of the Academic Committee, which summarized and analyzed the lab current status,
and gave great recognition to AMSV’s development direction

State-of-the-Art Chips - Designed and Tested in 2015 (20 chips)
A successfully
developed power
quality compensator
ISSCC 2016
Four PhD students and one assistant professor from the University of Macau (UM) State Key Laboratory of Analog and Mixed-Signal
VLSI (AMS-VLSI Lab) and Faculty of Science and Technology attended the Institute of Electrical and Electronics Engineer’s (IEEE)
62 nd International Solid-State Circuits Conference (ISSCC) in February 2016, which is considered the ‘Chip Olympics’, the
most competitive conference in the field of chip design.
The 3 papers and 3 Student Research Previews from UM
were "A 0.038mm 2 Saw-less Multiband Transceiver using an N-Path SC
Gain Loop", "A 0.003mm 2 1.7-to-3.5GHz Dual-Mode Time-Interleaved
Ring-VCO achieving 90-to150kHz 1/f3 Phase-Noise Corner", "A
Handheld 50-pM Sensitivity Micro-NMR CMOS Platform with B-Field
Stabilization for Multi-Type Biological/Chemical Assays", "A 12.5-ENOB
5MHz BW 4.2mW DT Multirate 2-1 Mash ΔΣ Modulator with Horizontal/
Vertical Opamp Sharing in 65nm CMOS", "A 0.45V 147-to-375nW
Hardware-Efficient Real-Time ECG Processor with Lossless-to-Lossy
Data Compression for Wireless Healthcare Wearables", and "A 2.4-GHz
Digitally-Modulated Class-D Polar PA Using Power-Gating, Interactive
AM-AM Modulation and a Dynamic Matching Network for Battery Lifetime
Extension". There included 1 Silk Road Award and 2 Student
Travel Grant Awards.
Prof. Seng-Pan U becomes the 1st
Macao-educated scholar to be
elevated to IEEE fellow
A research team from SKL AMS-VLSI
received the Best Paper Award at
ESSCIRC 2015
UM PhD student receives
Distinguished Design Award at
IEEE A-SSCC 2015
Prof Seng-Pan U who is the deputy director of
the State Key Laboratory of Analog and
Mixed-Signal VLSI, has been elevated to the
fellowship of the IEEE for the year 2016,
becoming the first scholar who was educated
in Macao, who has developed his professional
career both at UM and in the local and global
electronics industry, to be elevated to this
prestigious fellowship. Prof U was nominated
by IEEE Solid-State Circuit Society Presidentelect
Prof Jan Van Spiegel, for leadership in
the analog circuit design.
A research team from the University of
Macau (UM) received the Best Paper Award
at the European Solid-State Circuits Conference
(ESSCIRC) 2015, which is considered
‘Europe’s “Chip Olympics”’. This year’s conference
attracted 200 high-quality papers
from all over the world. The UM team was
composed by assistant professor Zhu Yan
and PhD student Chan Chi Hang from SKL
AMS-VLSI; Prof. U Seng Pan from the Department
of Electrical and Computer Engineering,
Faculty of Science and Technology;
and Vice Rector (Research) Prof. Rui Martins,
both also from SKL AMS-VLSI.
Lei Ka-Meng, a PhD student from the University
of Macau (UM) SKL AMS-VLSI and
Faculty of Science and Technology (FST),
recently received a Distinguished Design
Award for his research paper titled “A µNMR
CMOS Transceiver Using a Butterfly-Coil
Input for Integration with a Digital Microfluidic
Device Inside a Portable Magnet” at
the IEEE Asian Solid-State Circuits Conference
2015 (IEEE A-SSCC 2015).
4 New PhD Graduates
4. Jie Gao, Electronic-Automated Intelligent Digital Microfluidic System and Its Applications to DNA Amplification, Oct. 2015.
3. Chi-Hang Chan, Design Techniques and Considerations in Low-to-moderate Resolution Power-efficient GHz Range ADCs, Jul. 2015.
2. Yaohua Zhao, Low-Power High-Linearity and Area-Efficient Switched-Capacitor Filters Design Techniques in Nanoscale CMOS, Mar. 2015.
1. Tawfiq Amin, Analysis and Design of Power-Efficient Voltage-Controlled Oscillators for Wireless Applications in Nanoscale CMOS, Mar. 2015.
US Patents granted in 2015
1. Ka-Fai Un, Pui-In Mak, R.P.Martins, “Wideband Driver Amplifier”, US Patent, No. 9,172,337, Oct. 2015.
2. Chi-Seng Lam, Man-Chung Wong, Wai-Hei Choi, Ying-Duo Han, “Adaptive DC-link voltage controlled LC coupling hybrid active
power filters for reactive power compensation”, US Utility Patent, Granted, No. 9,122,296, Sep. 2015.
3. Ka-Fai Un, Pui-In Mak, Man-Kay Law, R.P.Martins, “Poly-phase Local Oscillator”, No. 9,093,951, US Patent, Jul. 2015.
4. Ka-Fai Un, Pui-In Mak, Man-Kay Law, R.P.Martins, “Wireless Transmitter”, No. 9,037,100, US Patent, May 2015.
5. Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, R.P.Martins, “Sampling front-end for analog to digital converter”, No.
8,947,283, US Patent, Feb. 2015.
6. Zushu Yan, Pui-In Mak, Man-Kay Law and R. P. Martins, “Frequency Compensation Techniques for Low-Power and Small-Area
Multistage Amplifiers”, No. 8,963,639, US Patent, Feb. 2015.

Selected works from each research line
In JSCC 2015
A 0.02-mm 2 59.2-dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz
Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad
Yaohua Zhao, Pui-In Mak, Rui P. Martins and Franco Maloberti
From Wireless research line
Motivation
Architecture
This work is a switched-capacitor (SC)-buffer Biquad
that can be recycled efficiently as an ultra-compact
low-pass filter (LPF) in nanoscale CMOS. It incorporates
only passive-SC networks and open-loop unitygain
buffers; both are friendlier to technology
downscaling than most conventional Biquads that
use high-gain amplifiers and closed-loop negative
feedback. Complex-pole pairs with independent Q
factors are recursively realized in one clock period,
while ensuring low crosstalk effect between the formations
of each pole. Nonlinearity and parasitic effects
are inherently low due to no internal gain. The
fabricated 65 nm CMOS prototype is a 1x-recycling
SC-buffer Biquad that is equivalent to a 4th-order
Butterworth LPF with 75% buffer utilization. It occupies
a die size of only 0.02 mm and exhibits 20x
bandwidth tunability (0.5 to 10 MHz), linear with the
clock rate. At 10 MHz bandwidth, the in-band IIP3 is
+17.6 dBm and input-referred noise is 19.5 nV/ Hz;
they correspond to 59.2 dB SFDR and 0.013 fJ figure
-of-merit which are favorably comparable with the
recent art. The 1 dB compression point conforms to
the out-of-band blocker profile of the LTE standard at
a 20 dB front-end gain.
Implementation
Verification

Adhesion Promoter for a Multi-Dielectric-Layer on a Digital
Microfluidic Chip
Jie Gao, Tianlan Chen, Cheng Dong, Yanwei Jia, Pui-In Mak, Mang-I Vai,
and Rui P. Martins
From Multidisciplinary Research Area (Microfluidic)
In UK Royal Society of Chemistry – Advances 2015
Motivation
Technique
A silane-based adhesion promoter suitable
for a multi-dielectric-layer coating on a digital
microfluidic chip is reported.
It measures >100 improvement in chip lifetime
via transforming the bonding of the dielectric
layers (Ta 2 O 5 and Parylene C) from
nonspecific to chemical.
The refined chip-fabrication protocol also
allows low EWOD actuation voltages down
to 5 V.
Verification I
Verification II

In IEEE Transactions on Electron Devices 2015
A Precision CMOS Voltage Reference Exploiting Silicon Bandgap
Narrowing Effect
Bo Wang, Man-Kay Law and Amine Bermak
From Wireless research line
Motivation
Architecture
Conventional precision voltage references
(BGRs) can be achieved by multiple temperature
trimmings and/or power hungry curvature
correction circuits that inevitably increases cost
and energy efficiencies. We exploit the intrinsic
temperature characteristics of the BJT itself to
reduce the BJT curvature and perform curvature
correction using the silicon bandgap narrowing
effect so as to avoid the power overhead of curvature
correction circuits by batch trimming.
Measurement results show that the BJT curvature
can be effectively reduced from its inherent
3.6 mV to 1.4 mV. The proposed BGR measures
a minimum temperature coefficient of 8.7 ppm/°
C and 4.1 ppm/°C from −55 °C to 125 °C after
batch trimming and curvature trimming, respectively.
Proposed BGR Topology with curvature reduction using bandgap
narrowing effect
Relationship between voltage and temperature showing the curvature reduction
and correction with convex (left) and concave (right) BJT intrinsic curvatures.
Implementation
Verification
(a)
Complete schematic of the proposed BGR using bandgap narrowing effect.
(b)
Chip micrograph of the proposed BGR
(a) Inaccuracy of V REF from 12 samples without trimming and after batch
trimming resistor R c1 at 25 °C (dotted lines indicates ± 3σ values); (b)
Measured BJT intrinsic curvature and V REF before and after the curvature
compensation.

In IET Electronics Letters 2015
Output pressure enhancement of CMUTs by using multiple
Helmholtz resonance apertures
Yuan Yu Yu, Xue Wen Cao, Sio Hang Pun, Peng Un Mak and Mang I Vai
From Biomedical IC research line
Motivation
Architecture
Multiple Helmholtz resonance apertures are proposed
to enhance the output pressure of aircoupled
capacitive micromachined ultrasonic
transducers (CMUTs) for non-contact ultrasound
imaging applications.
The methodologies of defining the design parameters
of CMUTs and the resonant apertures
on the membrane of CMUTs are discussed.
In comparing certain configurations of resonant
apertures with conventional CMUTs, simulation
results show that a prospective improvement of
output pressure (up to 32.1%) can be achieved.
Cross-section view of CMUT cell with Helmholtz resonance
apertures (red dash line indicates central axis of CMUT cell
(not in scale))
Implementation
Verification
3D FEA model of CMUT cell and air domain: CMUT cell and
air domain (Fig. a) and details of CMUT cell (Fig. b)
Cross-section view of CMUT cell with Helmholtz resonance
apertures (red dash line indicates central axis of CMUT cell
(not in scale))

In ESSCIRC 2014 & JSSC 2016
An 11b 450 MS/s 3-way Time-Interleaved Sub-ranging Pipelined-
SAR ADC in 65nm CMOS
Yan Zhu, Chi-Hang Chan, Seng-Pan (Ben) U, and Rui Paulo Martins
From Data Conversion and Signal Processing research line
Motivation
Architecture
The SAR architecture demands a stringent noise requirement
for the comparator design while aiming for
high resolution.
The mismatch spurs due to the timing, offset and
gain in TI SAR limit both signal-to-noise distortion
ratio (SNDR) and spurious-free dynamic range
(SFDR).
The pipelined-SAR ADCs still maintain their superiority
in power efficiency with high resolution in deep
sub-micron technology. The implementation of low
stage-gain (G) relaxes the desired noise requirement
in the comparator and balances the trade-off between
the power dissipation and gain-bandwidth
product (GBW) requirement of the Op-Amp.
Time skews on the other hand are tolerated by design
constraint or avoided through architecture optimizations.
Proposed hybrid ADC architecture and multiple
shared elements among the TI channels.
Implementation
Verification

A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC
In ISSCC 2015 & JSSC 2016
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan (Ben) U, and Rui Paulo Martins
From Data Conversion and Signal Processing research line
Motivation
Architecture
For 60GHz-band receivers and serial links applications.
The SAR ADC is a well-known energy-efficient architecture
while the speed of SAR ADCs can be further improved
with the comparator interleaving, loop-unrolled
asynchronous loop or the multi-bit per cycle.
The Flash ADC is known as the fastest ADC architecture
but power hungry. By adopting interpolation or calibration,
outstanding energy efficiency can also be accomplished
under advanced technology nodes.
In a standalone flash or SAR architecture, speed and
energy efficiency are still limited due to their inherent
characteristics; therefore, they are often combined with
time interleaving to achieve a breakthrough.
Time interleaving can be a very effective way to increase
the sampling rate of the ADC but it induces extra design
complexity and conversion non-idealities especially with
large numbers of interleaving channels.
V in,P
V in,N
Input
4
En, chX
4×
Channels
Clock
Gen.
Common
Clk
Bootstrap
2
V ref,N/V ref,P
Decoder & BDCO
3b/cycle SAR
Segmentation Logic
8
DAC Array
DAC Array
DAC Array
DAC Array
Dummy Latch
Dynamic
Pre-amp.
interpolation
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
On-Chip Offset Calibration Cal Ctrl.
6
14
6
MUX
Final Output
Codes
The power required for the digital gain and timing corrections
is prohibitive at 6b resolution.
Implementation
Verification
40
30
20
10
0
SNDR/SFDR (dB)50
43.5
30.78
SFDR
SNDR @Nyquist
43.12
30.76
42.95
30.66
1 2 3
#Sample
Sample #2, fs = 5 Gs/s
45
SNDR/SFDR (dB)
40
35
30
25
SFDR
SNDR
20
0 0.5 1.0 1.5 2.0 2.5 3.0
Input Frequency (GHz)
ISSCC’10[1] VLSI’13[5] VLSI’12[6] ISSCC’14[25] A-SSCC’14[26] This work
Architecture Ti-pipelined B-S Flash Flash Ti-SAR Ti-SAR Ti-Multi-bit SAR
Process 40nm 32nm SOI 40nm 28nm UTBB FDSOI 32nm SOI
65nm
Supply voltage (V) 1.1 0.85 1.1 1.0
1.1 1.0 1.2
10
36
5 6
Sampling rate (GS/s) 2.2 5
3
Resolution (bit) 6 6
Power (mW) 2.6 11
SNDRminin Nyq. band (dB) 29.6 33.1
Input cap.(fF) 200 72
FoM@ Nyq.(fJ/conv.-step) 40.0 100.48
Active area (mm 2 ) * 0.03 * 0.02 * 0.021
Calibration
Off-chip Off-chip Off-chip
*without Calibration **with Calibration
6 6
6
6
8.5 32
110 5.5 10.6
30.9 33.8
31.6 30.25 30.13
135 100
N/A
31
59.33 81
98
39 67.37
* 0.009 ** 0.048 * 0.008 (**
0.09)
Off-chip On-chip
On-chip

A Digital Low-Dropout Regulator with Coarse-Fine-Tuning and
Burst-Mode Operation
Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, and Rui P. Martins
In TCAS-II 2016
[Accepted in 2015]
From Integrated Power research line
Motivation
Digital low-dropout (D-LDO) regulator, that replaces the
power transistor in analog LDO regulator with a power
switch array, has recently drawn significant attention for
its low operation voltage and process scalability feature.
However, for a conventional shift register based D-LDO,
only one PMOS is turned on/off per clock cycle for the
shift register operation; and the transient speed can only
be improved by increasing sampling frequency which
degrades the power consumption. To address this issue,
a wide load range D-LDO regulator with coarse-fine tuning
and burst-mode techniques is proposed for fast transient
response and low quiescent current.
Architecture
For the proposed topology, the PMOS arrays consist of one
coarse section and one fine section, driven by separate shift
registers. To extend the load current range, the coarse
PMOS array is designed to be with 64 power switches. The
unit size of the coarse PMOS is designed to be 16 times of
that of the fine PMOS for the loop gain boosting. To cover
the current gap between two adjacent coarse bits can provide,
the fine PMOS array is designed with 32 units for sufficient
margin. Once the voltage undershoot/overshoot is
detected, the coarse-tuning quickly finds out the coarse control
word in which the load current should be located, with
large power MOS strength and high sampling frequency for
a fixed duration. Then, the fine-tuning with reduced power
MOS strength and sampling frequency takes over the
steady-state operation for high accuracy and current efficiency.
Implementation
Verification
The proposed D-LDO regulator was fabricated in a 65-nm
CMOS process.

Sensor
Conventional
Proposed
Conventional
Proposed
In TPEL 2015
Self-reconfiguration property of a mixed signal controller for
improving power quality compensator during light loading
Man-Chung Wong, Yan-Zheng Yang, Chi-Seng Lam, Wai-Hei Choi, Ning-Yi Dai, Ya-jie Wu,
Chi-Kong Wong, Sai-Weng Sin, U-Fat Chio, Seng-Pan U, R.P. Martins
From Integrated Power research line
Motivation
Currently, when compensator performance
does not satisfy international standards, other
PWMs can be selected, or the dc link voltage
can be increased. However, it may be the case
that neither of these methods will improve compensator
performance during light loading due
to the low resolution of the input signals compared
with the error signal and the PWM error
margin. The design of digital controllers is usually
based on a full loading situation. The full
analog-to-digital (A/D) conversion input signal
range of a digital controller is therefore utilized,
to avoid analog signal saturation. In a light load
situation, the digital controller may suffer from
the problem of low resolution, which significantly
affects its compensation performance. There
is presently no achievable control strategy to
deal with power quality compensation issues
during light loading.
Architecture
A mixed signal controller for power quality compensator is proposed for enhancing
the advanced performance that cannot be achieved by analog or
digital controller alone and independently. Several special features can be
achieved by mixed signal controller are given as follows:
▓ Adaptive Signal Conditioning and Programmability on-the-Fly
▓ Parallelism Properties and Higher Redundancy
▓ Higher Accuracy, Higher Bandwidth, Faster Response Time and Low
Power
▓ Algorithm Complexity and Simplicity of Implementation
The FPAA can be operated as an adaptive signal conditioning unit that preconditions
and filters, according to the optimization of system performance.
The modified signals then pass to the digital unit for further processing, assisted
by the ADC. The digital system, FPGA/DSP, can work with a “backer”
sub-program to optimize the system operation by reconfiguring the control
system automatically, or to carry out self-testing and self-repairing tasks.
When it is necessary to reconfigure the analog part, the re-programming data
can be transferred directly through the digital path to the FPAA. Conversely,
the FPAA can also send out control signals to the FPGA to modify the algorithm
for protection, critical operations, etc.
Input Signals
vLa, vLb, vLc
iLa, iLb, iLc
iCa, iCb, iCc
FPAA
Mixed Signal Controller
vLa, vLb, vLc
iLa, iLb, iLc
iCa, iCb, iCc
Gain Saturation
Signal
ADC
Reconfigurable
Gain G
FPGA/
DSP
PWM Signals
Ta,Ta
Tb,Tb
Tc,Tc
Analog Signal Paths
Digital Signal Paths
Implementation
Verification
The proposed mixed signal controller is tested in a threephase
four-wire hybrid active power filter (HAPF) system in
comparison with a conventional digital controller.
v sa
v sb
L s
i sn
i sb
i sc
v La
v Lb
v Lc
ica
icb
icc
i La
i Lb
i Lc
A
B Loads N
C
i Ln
A
N
B
N
C
N
LLa
LLb
LLc
RLa
RLb
RLc
Inductive
Linear Load
IEEE Standard (

Events and Visits
Visit by Mr. Ma Chi Ngai Frederico, President of FDCT
with members of S&T Assessment Committee (FDCT)
Visit by Dr. Peter Lam, University Council Chair
Distinguished Lectures on Microelectronics
Distinguished Lecture on Microelectronics - "Power Minimization in
Amplifiers and Filters" by Prof. Willy Sansen , IEEE Life Fellow,
Professor at the Catholic University of Leuven, in Belgium
Distinguished Workshop on Analog IC Design by
Professor Behzad Razavi, Professor of electrical engineering at
University of California, Los Angeles, USA
4 New Academics, 1 Post-Doc and 1 Administrative Joined SKL AMS-VLSI
Assistant Professor
Yanwei Jia, received the B.S. and M. S degrees from Hunan University, Changsha, China in 1996 and 2002, respectively, and the Ph.D.
degree from the National University of Singapore in 2006. She currently serves as assistant professor at SKL AMS-VLSI.
Research interests: Microfluidics, Biotechnology and Multidisciplinary research.
Assistant Professor
Yong Chen, received the B.Eng. degree in electronic and information engineering, Communication University of China (CUC), Beijing,
China, in 2005, and the Ph.D. in Engineering in microelectronics and solid-state electronics, Institute of Microelectronics of Chinese
Academy of Sciences (IMECAS), Beijing, China, in 2010. He currently serves as assistant professor at SKL AMS-VLSI.
Research Interests: Analog/Biomedical detection and RF integrated circuit, mm-wave system and circuit, high-speed on-chip and chip-to
-chip Electrical/Optical
Research Assistant Professor
Chi-Hang Chan received the B.S. degree in electrical engineering from University of Washington (U.W. Seattle), USA, in 2008, and the
M.S. degree in electrical and electronics engineering and Ph.D. degree from the University of Macau, Macao, China, in 2012 and 2015,
respectively. He currently serves as research assistant professor at SKL AMS-VLSI.
Research interests: Nyquist ADC, Mixed-signal circuits.
Lecturer (Macao Fellow)
Ka-Fai Un received the B.Sc. degree in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan, in 2007, and the
M.Sc. degree in electrical and electronics engineering and Ph.D. degree from the University of Macau (UM), Macao, China, in 2009 and
2014, respectively. He is currently a lecturer (Macao Fellow) at SKL AMS-VLSI.
Research Interests: Wireless integrated circuits design, Mathematics.
Post-Doctoral Fellow & Cleanroom Specialist
Jie Gao, she received her M.Sc. degree in Materials Science and Engineering from the Technical University of Hamburg-Harburg,
Germany and University of Aveiro, Portugal in 2007. She received her Ph.D. degree in Electrical and Computer Engineering from University
of Macau, in 2015. She currently serves as Post-Doctoral Fellow and Cleanroom Specialist at SKL AMS-VLSI.
Research interests: Design and fabrication of automated microfluidic chips for point-of-care applications.
Senior Administrative Officer
Weng-Keong CHE received the B.S. degree, M.S. degree and Ph.D. degree from the National Taiwan University, in 1997, 1999 and
2005, respectively. He currently serves as Senior Administrative Officer for commercialization coordination, industrial collaboration and
spin-off incubation at SKL AMS-VLSI.
Research interests: RF Transceiver IC / RF SoC / Fiber optical Front-End IC / MCU SoC / Automobile SoC design.

SCI Journals – 28 Papers
▓ “Polyphase Decomposition for Tunable Band-Pass Sigma-Delta A/D Converters”, IEEE Journal on Emerging and Selected Topics in Circuits and
Systems, Dec. 2015.
▓ “Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques”, IEEE Transactions
on VLSI Systems, Dec. 2015.
▓ “Improving the Linearity and Power Efficiency of Active Switched-Capacitor Filters in a Compact Die Area”, IEEE Transactions on VLSI Systems, Dec.
2015.
▓ “DCM operation analysis of KY converter”, IET Electronics Letters, Nov. 2015
▓ “Non-Linear adaptive hysteresis band pwm control for hybrid active power filters in reducing switching loss”, IET Power Electronics, Nov. 2015
▓ "Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate", IEEE Journal of Solid-State
Circuits, Oct. 2015
▓ "A Sub-GHz Wireless Transmitter Utilizing a Multi-Class-Linearized PA and Time-Domain Wideband-Auto I/Q-LOFT Calibration for IEEE 802.11af WLAN",
IEEE Transactions on Microwave Theory and Techniques, Oct. 2015
▓ “Self-reconfiguration property of a mixed signal controller for improving power quality compensator during light loading,” IEEE Transactions on Power
Electronics, Oct. 2015
▓ “Hybrid railway power conditioner with partial compensation for converter power rating reduction”, IEEE Transactions on Industry Applications,
Sep./Oct. 2015
▓ "A 0.02 mm 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad", IEEE Journal of Solid-
State Circuits, Sep. 2015
▓ "Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs," IEEE Transactions on Circuits and
Systems-I: Regular Papers, Sep. 2015
▓ "Resolution-enhanced sturdy MASH delta–sigma modulator for wideband low-voltage applications", IET Electronics Letters, Jul. 2015
▓ "A CMOS Delta-Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration," IEEE Transactions on Circuits and Systems-I: Regular
Papers, Jul. 2015
▓ “A Precision CMOS Voltage Reference Exploiting Silicon Bandgap Narrowing Effect”, IEEE Transactions on Electron Devices, Jul. 2015
▓ “A 0.07mm 2 2.2 mW 10 GHz Current-Reuse Class-B/C Hybrid VCO achieving 196-dBc/Hz FoM A ”, IEEE Microwave Wireless and Components Letters,
Jul. 2015.
▓ "A Palm-Size µNMR Relaxometer Using a Digital Microfluidic Device and a Semiconductor Transceiver for Chemical/Biological Diagnosis", Royal Society of
Chemistry - Analyst, Jun. 2015
▓ “Analysis, control and experimental verification of a single-phase capacitive-coupling grid connected inverter”, IET Power Electronics, May 2015
▓ "Adhesion Promoter for Multi-dielectric-layer on Digital Microfluidic Chip", RSC Advances, May 2015
▓ "A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links", IEEE Transactions on VLSI Systems,
May 2015
▓ "On the Droplet Velocity and Electrode Lifetime of Digital Microfluidics: Voltage Actuation Techniques and Comparison", Springer Microfluidics and
Nanofluidics, Apr. 2015
▓ "A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth",
IEEE Transactions on Circuits and Systems–I: Regular Papers, Apr. 2015
▓ “Output pressure enhancement of CMUTs by using multiple Helmholtz resonance apertures,” IET Electronics Letters, Mar. 2015
▓ "A 0.0045-mm 2 32.4-µW Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation", IEEE Transactions on Circuits and Systems–II:
Express Briefs, Mar. 2015
▓ " 0.0045mm 2 15.8μW Three-Stage Amplifier Driving 10x-Wide (0.15 to 1.5nF) Capacitive Loads with >50° Phase Margin", IET Electronics Letters, Mar.
2015
▓ "Wideband Receivers: Design Challenges, Tradeoffs and State-of-the-Art", IEEE Circuits and Systems Magazine, Mar. 2015
▓ "A Fully-Integrated Low-Dropout Regulator with Full-Spectrum Power Supply Rejection," IEEE Transactions on Circuits and Systems-I: Regular
Papers, Mar. 2015
▓ “A systematic approach to hybrid railway power conditioner design with harmonic compensation for high-speed railway”, IEEE Transactions on Industrial
Electronics, Feb. 2015
▓ "A 3.6mW 6GHz Current-Reuse VCO-Buffer with Improved Load Drivability in 65nm CMOS", Wiley International Journal of Circuit Theory and
Applications, Jan. 2015
Conferences – 23 Papers
Major IEEE solid-state circuits conferences
IEEE International Solid-State Circuits Conference (ISSCC) 2015, San Francisco, CA, USA, Feb. 2015
▓ “A 5.5mW 6b 5GS/s 4-times Interleaved 3b/cycle SAR ADC in 65nm CMOS” [Pre-Doctoral Achievement Award]
▓ “A 0.028mm 2 11mW Single-Mixing Blocker-Tolerant Receiver with Double-RF N-Path Filtering, S 11 Centering, +13dBm OB-IIP 3 and 1.5-to-2.9dB NF” [Pre-
Doctoral Achievement Award]
▓ “A 123-Phase DC-DC Converter-Ring with Fast-DVS for Microprocessors”
▓ “A 2-/3-Phase Fully-Integrated Switched-Capacitor DC-DC Converter in Bulk-CMOS for Energy-Efficient Digital Circuits With 14% Efficiency Improvement”
▓ “A 12b 180MS/s 0.068mm 2 Full-Calibration Integrated Pipelined-SAR ADC” [Student Research Preview]
▓ “A Multi-Step Multi-Sample µNMR Relaxometer Using Inside-Magnet Digital Microfluidics and a Butterfly-Coil-Input CMOS Transceiver” [Student Research
Preview]
IEEE Asian Solid-State Circuits Conference (A-SSCC), Xiamen, Fujian, China, Nov. 2015
▓ “A μNMR CMOS Transceiver Using a Butterfly-Coil Input for Co-integration with a Digital Microfluidic Device Inside a Portable Magnet” [Distinguished
Design Award]
▓ “A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation”
Other IEEE conferences:
IEEE Region 10 Conference (TENCON), Macao, China, Nov. 2015
▓ “An All-Factor Modulation Bandwidth Extension Technique for Delta-Sigma PLL Transmitter” [Professional Award]
▓ “Capacitive floating level shifter: Modeling and design”
▓ “Generalized type III controller design interface for dc-dc converters”
▓ “Hardware and software design of a thyristor controlled LC-coupling hybrid active power filter”
▓ “Comparison among PPF, APF, HAPF and a combined system of a shunt HAPF and a shunt thyristor controlled LC”
▓ “A woman in engineering - increasing Macao students’ interest in science and technology” [Invited Workshop Paper]
▓ “Historical review of hybrid active power filter for power quality improvement”
International Conference on Miniaturized Systems for Chemistry and Life Sciences (MicroTAS), Gyeongju, Korea, Oct. 2015
▓ “A Thermal-Insensitive All-Electronic Modular µNMR Relaxometer with a 2D Digital Microfluidic Chip for Sample Management”
IEEE Energy Conversion Congress and Exposition (ECCE), Montreal, Canada, Sep. 2015
▓ “Analysis, design and implementation of a quasi-proportional-resonant controller for multi-functional capacitive-coupling grid-connected inverter”
IEEE Ph.D. Research In Micro-electronics and Electronics (PRIME), Glasgow, Scotland, Jul. 2015
▓ “Exploring the Noise Limits of Fully-Differential Micro-Watt Transimpedance Amplifiers for Sub-pA/√Hz Sensitivity”
International Symposium on Signals, Circuits and Systems (ISSCS), Iasi, Romania, Jul. 2015
▓ “Multi-Range, Ultra-Low-Power, -20 to 60°C CMOS Smart Temperature Sensor with ±0.1°C Inaccuracy”
▓ “Comparator with Built-in Reference Voltage Generation and Split-ROM Encoder for a High-Speed Flash ADC”
IEEE Congress on Evolutionary Computation (CEC), Sendai, Miyagi, Japan, May 2015
▓ “Predicting Protein Docking Poses on a Solid Surface by Particle Swarm Optimization”
IEEE EMBS Neural Engineering Conference (NER), Montpellier, France, Apr. 2015
▓ “Input Capacitance Compensated Neural Recording Amplifier”
IEEE International Wireless Symposium (IWS), Shenzhen, China, Mar. 2015
▓ “A Review and Design of the On-Chip Rectifiers for RF Energy Harvesting”
State Key Laboratory of Analog and Mixed-Signal VLSI / UM
http://www.amsv.umac.mo