IHP Annual Report 2006 - IHP Microelectronics

J a h r e s b e r i c h t 2 0 0 6 – a n n u a l r e p o r t 2 0 0 6
Annual Report 2006
A n n u A l R e p o R t 2 0 0 6

prof. Dr. Wolfgang Mehr
2006 war für das IHP und seine Partner ein sehr erfolgreiches
Jahr. Die erreichten Ergebnisse zeugen von der
Fähigkeit des Institutes, durch anspruchsvolle, langfristige
Forschungsarbeiten komplexe Zielstellungen
zu erreichen. Ein Beispiel dafür ist die experimentelle
Demonstration eines Systems für die drahtlose Kommunikation
mit Datenraten bis 1 Gbps. Weitere wichtige
Ergebnisse sind die erreichte Modernisierung der
technologischen Ausrüstungen, der Höchstfrequenz-
Messtechnik und der Design-Software für das technologische
Strukturniveau 0,13 µm sowie die Weiterentwicklung
der SiGe-BiCMOS-Technologie. Damit wurden
die Voraussetzungen für eine weitere Erhöhung der Geschwindigkeit
und Komplexität von Schaltkreisen und
Systemen geschaffen.
Eines der nächsten Ziele des IHP ist es, mit SiGe-Heterobipolartransistoren
Lösungen für den Terahertz-Bereich
zu demonstrieren. Das betrifft insbesondere Systeme
mit deutlich erhöhten Datenraten und bildgebende
Verfahren. Längerfristig orientiert sich das Institut
darüber hinaus auf die System-Integration von Nanobauelementen
mit noch höheren Arbeitsfrequenzen
für Kommunikationssysteme sowie auf in Silizium integrierte
Lösungen für die optische Datenübertragung.
Grundlegende Arbeiten dazu werden seit mehreren Jahren
im Gemeinsamen Labor mit der BTU Cottbus durchgeführt.
2 A n n u A l R e p o R t 2 0 0 6
V o r w o r t – F o r e w o r d
2006 was a very successful year for the IHp and its
partners. the obtained results demonstrate the
ability of the institute to achieve complex goals by
performing challenging, long-term research work.
Indicative of this is the experimental demonstration
of a system for wireless communication with data rates
up to 1 Gbps. Further important results are the
realized upgrade of the technological equipment,
the measuring technique for very high frequencies
and the design software for the technological level
of 0.13 µm as well as the progress of the SiGe BiCMoS
technology development. In this way the foundations
for a further increase of the speed and complexity of
circuits and systems were laid.
one of the next goals of the IHp is to demonstrate
solutions for the tHz range using SiGe heterobipolar
transistors. this development will apply in particular
to systems with considerably increased data rates and
to imaging systems. In the longer term the institute
additionally orientates itself towards the system integration
of nanoscale devices operating at still higher
frequencies for communication systems as well as
towards integrated silicon solutions for optical data
communication. Fundamental work on this topic has
been accomplished for several years in the Joint lab
with the Btu Cottbus.

Die Forschungskooperationen des IHP haben sich kontinuierlich
weiterentwickelt, wovon unter anderem die
deutliche Erhöhung der eingeworbenen Drittmittel
im Jahr 2006 zeugt. Der vom IHP angebotene Multi-
Projekt-Wafer-Service wird weltweit durch eine steigende
Zahl von Universitäten und Forschungseinrichtungen
genutzt.
Durch Mitarbeiter des IHP wurde die Firma „Silicon Radar“
ausgegründet, die 2007 ihre operative Tätigkeit
auf dem Gebiet siliziumbasierter Schaltkreise im GHz-
Bereich aufnehmen wird.
In Frankfurt (Oder) etablierten sich im Jahr 2006 drei
Solarfabriken. Das IHP ist mit diesen Firmen und weiteren
wissenschaftlichen Einrichtungen in einem Netzwerk
zur Vorbereitung gemeinsamer Forschungs- und
Ausbildungsprojekte aktiv.
Der Belegschaft des IHP möchten wir an dieser Stelle
für ihre sehr engagierte Arbeit danken. Der Brandenburgischen
Landesregierung und der Bundesregierung
gilt unser Dank für die außerordentliche Unterstützung
unserer Forschungsarbeiten.
Wolfgang Mehr Manfred Stöcker
Wiss.-Techn. Geschäftsführer Adm. Geschäftsführer
V o r w o r t – F o r e w o r d
the research cooperation of the IHp has developed
continuously, as is demonstrated by the significant
increase of acquired third party funding in the year
2006. the multi-project wafer service offered by the
IHp is used throughout the world by an increasing
number of universities and research institutions.
the spin-off company “Silicon Radar” was founded
by scientists of the IHp and will start its operational
work in the area of silicon-based GHz circuits in
2007.
three solar factories were established in Frankfurt
(oder) in 2006. the IHp is working actively with these
companies and other scientific institutions in a network
for the preparation of joint projects for research
and education in this context.
At this point we would like to thank the IHp staff for
their dedicated work. We are also grateful to the regional
government of Brandenburg and the federal
government for the extraordinary support of our research
activities.
A n n u A l R e p o R t 2 0 0 6

A n n u A l R e p o R t 2 0 0 6
i n h a l t s V e r Z e i c h n i s – c o n t e n t s
Contents

i n h a l t – c o n t e n t s
Vorwort
Aufsichtsrat
Wissenschaftlicher Beirat
Das IHP auf einen Blick
Forschung des IHP
Das Jahr 2006
Ausgewählte Projekte
Gemeinsame Labore
Konferenzen und Workshops
Zusammenarbeit und Partner
Gastwissenschaftler und Seminare
Publikationen
Angebote und Leistungen
Wegbeschreibung zum IHP
2
6
7
8
0
26
66
72
76
80
8
72
80
Foreword
Supervisory Board
Scientific Advisory Board
IHp in a nutshell
IHp‘s Research
update 2006
Selected projects
Joint labs
Conferences and Workshops
Collaboration and partners
Guest Scientists and Seminars
publications
Deliverables and Services
Directions to IHp
A n n u A l R e p o R t 2 0 0 6

Aufsichtsrat
Konstanze Pistor
Vorsitzende
Ministerium für Wissenschaft, Forschung und Kultur
Land Brandenburg
MinR Thomas Sondermann
Stellvertretender Vorsitzender (bis 01. Nov. 2006)
Bundesministerium für Bildung und Forschung
Dr. Volkmar Dietz
Stellvertretender Vorsitzender (seit 01. Nov. 2006)
Bundesministerium für Bildung und Forschung
Dr.-Ing. Peter Draheim
Silicon Manufacturing Itzehoe SMI GmbH
Prof. Dr. Helmut Gabriel
Freie Universität Berlin
Dr. Eckhard Grass
IHP GmbH
Norbert Quinkert
Motorola GmbH, Taunusstein
Dr. Harald Richter
IHP GmbH
Prof. Dr. Ernst Sigmund
Brandenburgische Technische Universität Cottbus
MinR Gerhard Wittmer
Ministerium der Finanzen
Land Brandenburg
6 A n n u A l R e p o R t 2 0 0 6
a u F s i c h t s r a t – s u p e r V i s o r y b o a r d
supervisory board
Konstanze pistor
Chair
Ministry of Science, Research and Culture
State of Brandenburg
Minr thomas sondermann
Deputy Chair (until november 1, 2006)
Federal Ministry of education and Research
dr. Volkmar dietz
Deputy Chair (since november 1, 2006)
Federal Ministry of education and Research
dr.-ing. peter draheim
Silicon Manufacturing Itzehoe SMI GmbH
prof. helmut Gabriel
Freie universität Berlin
dr. eckhard Grass
IHp GmbH
norbert Quinkert
Motorola GmbH, taunusstein
dr. harald richter
IHp GmbH
prof. ernst sigmund
Brandenburg technical university, Cottbus
Minr Gerhard wittmer
Ministry of Finance
State of Brandenburg

Wissenschaftlicher Beirat
w i s s e n s c h a F t l i c h e r b e i r a t – s c i e n t i F i c a d V i s o r y b o a r d
Prof. Dr. Hermann G. Grimmeiss
Vorsitzender
Department of Solid State Physics
University of Lund, Schweden
Dr. Jürgen Arndt
Stellvertretender Vorsitzender
ATMEL Germany GmbH, Heilbronn
Prof. Dr. Ignaz Eisele
Fakultät für Elektrotechnik und
Informationstechnik
Universität der Bundeswehr München
Prof. Dr. Christian Enz
CSEM SA, Neuchatel, Schweiz
Prof. Dr. Michael Hoffmann
Institut für Mikrowellentechnik
Universität Ulm
Prof. Dr. Ulrich Rohde
Synergy Microwave Corporation, USA
Dr. Josef Winnerl
Infineon Technologies AG, München
Leitung
Prof. Dr. Wolfgang Mehr
Wissenschaftlich-Technischer Geschäftsführer
Manfred Stöcker
Administrativer Geschäftsführer
scientific advisory board
prof. hermann G. Grimmeiss
Chair
Department of Solid State physics
university of lund, Sweden
dr. Jürgen arndt
Deputy
AtMel Germany GmbH, Heilbronn
prof. ignaz eisele
Department of electrical engineering and
Information technology
university of the Bundeswehr Munich
prof. christian enz
CSeM SA, neuchatel, Switzerland
prof. Michael hoffmann
Institute of Microwave techniques
university of ulm
prof. ulrich rohde
Synergy Microwave Corporation, uSA
dr. Josef winnerl
Infineon technologies AG, Munich
Management
prof. wolfgang Mehr
Director
Manfred stöcker
Administrative Director
A n n u A l R e p o R t 2 0 0 6
7

8 A n n u A l R e p o R t 2 0 0 6
d a s i h p a u F e i n e n b l i c K – i h p i n a n u t s h e l l
IHP in a Nutshell

Das Institut
d a s i h p a u F e i n e n b l i c K – i h p i n a n u t s h e l l
- Gegründet 1983; 1991 Neugründung aus einem
früheren Akademieinstitut mit langjähriger
Erfahrung in der Mikroelektronik auf Silizium-
Basis
- 210 Mitarbeiter aus 16 Ländern
- Mitglied der Leibniz-Gemeinschaft
aufgabe
- Wirkung als Europäisches Forschungs- und
Innovationszentrum für drahtlose Kommunikationstechnologien
- Stärkung der Wettbewerbsfähigkeit der deutschen
und europäischen Mikroelektronik- und Kommunikationsforschung
- Erhöhung der Attraktivität der Region als
Hochtechnologiestandort
strategie
- Konzentration auf drahtlose und Breitbandkommunikation
- Erarbeitung zukunftsorientierter Technologien,
Schaltkreise und Systeme bis zu Prototypen
- Wertschöpfung durch Innovation
Infrastruktur
- Vollständige Innovations-Kette vom Material
bis zu Systemen, einschließlich Pilotlinie mit
0,25 (0,13) µm-BiCMOS-Technologien
Kompetenzen
- Systeme für die drahtlose Kommunikation
- HF-Schaltkreisentwurf
- Erweiterung von Silizium-CMOS-Technologien
für neue Funktionen
- Materialien für die Mikro- und Nanoelektronik
the institute
- Founded in 1983; re-established in 1991 as a
successor institution to the former institute of
the east German Academy with extensive
experience in silicon microelectronics
- 210 employees from 16 countries
- Member of the leibniz Association
Mission
- to act as a european Research and Innovation
Center for wireless communication
technologies
- to strengthen the competitive position of the
German and european microelectronic and
communication research
- to enhance the attractiveness of the region
as a location for high technology
strategy
- to focus on solutions for wireless and broadband
communications
- Development of future-oriented technologies,
circuits and systems up to prototypes
- to create value through innovation
Facilities
- Complete innovation chain from materials to
systems, including a pilot line with
0.25 (0.13) µm BiCMoS technologies
competencies
- Systems for wireless communication
- RF circuit design
- extension of silicon CMoS technologies for new
functionalities
- Materials for micro- and nanoelectronics
A n n u A l R e p o R t 2 0 0 6

0 A n n u A l R e p o R t 2 0 0 6
F o r s c h u n G d e s i h p – i h p ‘ s r e s e a r c h
IHP‘s Research

Das IHP arbeitet an den folgenden drei eng miteinander
verbundenen Forschungsprogrammen:
1. Drahtloses Internet: Systeme und Anwendungen,
2. Technologieplattform für drahtlose und
Breitbandkommunikation,
3. Materialien für die Mikro- und Nanoelektronik.
Gemeinsames Ziel ist die Schaffung innovativer Lösungen
für Anwendungen in den Bereichen drahtlose
und Breitbandkommunikation.
Die Forschungsprogramme nutzen die besonderen
Möglichkeiten des IHP. So verfügt das IHP über eine
Pilotlinie für technologische Forschungen und Entwicklungen.
Eine weitere Besonderheit ist das vertikale
Forschungskonzept des IHP unter Nutzung der
zusammenhängenden und aufeinander abgestimmten
Kompetenzen des Instituts auf den Gebieten Systementwicklung,
Schaltungsentwurf, Technologie und Materialforschung.
Die Forschung des IHP setzt auf die typischen Stärken
eines Leibniz-Instituts: Sie ist charakterisiert durch eine
langfristige, komplexe Arbeit, die Grundlagenforschung
mit anwendungsorientierter Forschung verbindet.
Die Realisierung der Forschungsprogramme erfolgt
mit Hilfe eines regelmäßig aktualisierten Portfolios
von Projekten. Die Aktualisierung geschieht aufgrund
inhaltlicher Erfordernisse sowie der Möglichkeiten für
Kooperationen und Finanzierung. Drittmittelprojekte
werden im Einklang mit den strategischen Zielen des
IHP eingeworben.
Im Folgenden werden wesentliche Zielstellungen der
Forschungsprogramme des IHP beschrieben.
Drahtloses Internet: Systeme und Anwendungen
In diesem Programm werden komplexe Systeme für
die drahtlose Kommunikation in Form von Prototypen
und Anwendungen untersucht und entwickelt. Ziel sind
Hardware / Software-Systemlösungen auf hochintegrierten
Single-Chips. Der vertikale Forschungsansatz
zeigt sich auch in der Architektur der erarbeiteten Systeme.
Im Wesentlichen wird die Wechselwirkung zwischen
verschiedenen Schichten optimiert und eine vertikale
Migration semantischer Elemente realisiert.
Die drei Hauptforschungsrichtungen sind Systeme mit
hoher Performance, Systeme mit geringem Energiever-
F o r s c h u n G d e s i h p – i h p ‘ s r e s e a r c h
IHp is working on the following three closely connected
research programs:
1. Wireless Internet: Systems and Applications,
2. technology platform for Wireless and
Broadband Communication,
3. Materials for Micro- and nanoelectronics.
the joint objective is the creation of innovative solutions
for wireless and broadband applications.
the research programs make use of the special opportunities
provided by the IHp. In this way the institute
has a pilot line for research and technological developments.
An additional feature is the IHp vertical
research concept employing the associated and harmonized
competencies of the institute in the fields of
system development, circuit design, technology and
materials research.
the research of the IHp is based on the typical
strengths of a leibniz Institute; it is dominated by
long-term, complex efforts which connect basic research
with application-oriented research.
the realization of the research programs is accomplished
through a project portfolio which is regularly
updated according to the content requirements as
well as through opportunities for cooperations and
outside funding. Grant projects are acquired in accordance
with the strategic goals of IHp.
Significant goals of IHp’s research programs are specified
below.
wireless internet: systems and applications
this program investigates and develops complex systems
for wireless communication as prototypes and
applications with the objective to find solutions for
Hardware / Software systems on highly integrated
single chips. the vertical research approach is also
reflected in the architecture of the addressed systems.
Basically inter-layer interaction is optimized
and a vertical migration of semantic elements is performed.
the three major directions of research are systems
with high performance, systems with low power con-
A n n u A l R e p o R t 2 0 0 6

auch und Middleware für kontextabhängige drahtlose
Internetanwendungen.
Für drahtlose Systeme mit hoher Performance ist es das
Ziel, alle Funktionen eines drahtlosen PDA auf einem Chip
zu integrieren. Dabei sollen Datenraten bis über 2 Gbps
bei Trägerfrequenzen bis zu 60 GHz erreicht werden.
Weiterführende Arbeiten hin zu Datenraten bis 100 Gbps
werden im Grundlagenbereich dieses Forschungsprogramms
vorbereitet.
Die Forschung zu Systemen mit geringem Energieverbrauch
hat zum Ziel, Sensornetze auf Basis hochintegrierter
Chips zu realisieren. Typische Anwendungen dafür
sind Body-Area-Netze für medizinische Anwendungen
oder im Wellness-Bereich. In diesem Zusammenhang
werden neue Netzarchitekturen, verteilte, ressorcenarme
Middlewareansätze, neue energieeffiziente Medienzugriffsprotokolle
sowie energieeffiziente Transceiver erforscht
und realisiert. UWB-Transceiver sind für Anwendungen
im Nahbereich und Anwendungen mit hohen
Ortsauflösungseigenschaften besonders geeignet.
Die Forschung zu kontextabhängigen Middleware-Systemen
betrifft insbesondere auch die Erhaltung der
Privatsphäre und die Sicherheit bei der Nutzung mobiler
Endgeräte. Darüber hinaus wird die symmetrische bzw.
asymmetrische Verteilung von Ressourcen zwischen Endgeräten
und Servern im Gesamtsystem untersucht.
Technologieplattform für drahtlose und
Breitbandkommunikation
In diesem Programm werden Technologien (insbesondere
BiCMOS-Technologien) mit zusätzlichen Funktionen
durch die modulare Erweiterung industrieller CMOS-
Technologien entwickelt. Die Schwerpunkte in diesem
Programm sind Technologien mit hoher Performance,
kostengünstige Technologien für System-on-Chip, sowie
die Sicherung des Zugriffs interner und externer Designer
auf die Technologien des IHP.
Die Forschung in Richtung Technologien hoher Performance
zielt auf extrem schnelle SiGe HBTs, einschließlich komplementärer
Bauelemente und neuer Bauelementekonzepte
für Anwendungen bei Frequenzen bis > 100 GHz.
Zielstellung der Forschung für kostengünstige Technologien
ist es, BiCMOS-Technologien mit ausreichender
Performance und geringen Fertigungskosten zu entwickeln
sowie darin zusätzliche Module wie HF-LDMOS,
2 A n n u A l R e p o R t 2 0 0 6
F o r s c h u n G d e s i h p – i h p ‘ s r e s e a r c h
sumption and middleware for context sensitive wireless
internet applications.
the goal for high-performance wireless systems is to
integrate all functionalities of a wireless pDA on a
single chip. the targets are to achieve a data rate exceeding
2 Gbps at carrier frequencies of up to 60 GHz.
Continuing activities towards data rates up to 100 Gbps
will be made in the basic area of this research program.
the research on systems with low energy consumption
is directed towards sensor networks based on highly
integrated chips. typical applications are body-area
networks for health care or wellness. In this context
new network architectures, distributed low resource
middleware concepts, new energy efficient protocols
for medium access as well as energy efficient transceivers
are investigated and realised. uWB transceivers
are particularly well suited for short range
applications and applications requiring high spatial
resolution.
Research in context-sensitive middleware systems
addresses especially privacy and security questions
in using mobile devices. Moreover the symmetrical
and asymmetrical resource distribution between client
and server parts of the overall system is investigated.
technology platform for wireless and
broadband communication
the goal of this program is to develop value-added
technologies, preferably BiCMoS technologies, by
the modular extension of industrial CMoS. the focal
points in this program are technologies with a high
performance, low-cost technologies for system-onchip,
and the provision of technology access for internal
and external designers.
the research towards high-performance technologies
targets ultrafast SiGe HBts, including complementary
devices and new device concepts for applications at
frequencies of up to > 100 GHz.
the aim of the research for low-cost technologies is
to develop BiCMoS technologies with ample performance
and low manufacturing costs and to integrate
additional modules such as RF lDMoS, Flash and passive
devices.

Flash und passive Bauelemente zu integrieren.
Die 0,25-µm-BiCMOS-Technologien des IHP sind europa-
und weltweit für Designer nutzbar. Ein Zeitplan für die
entsprechenden technologischen Durchläufe in der Pilotlinie
in Frankfurt (Oder) ist über die Internetadresse
des IHP verfügbar. Eine neue 0,13-µm-BiCMOS-Technologie
wird entwickelt.
Materialien für die Mikro- und Nanoelektronik
Die Materialforschung am IHP hat die Integration neuer Materialien
in gegenwärtige und zukünftige Technologien zum
Ziel, um so verbesserte, zusätzliche oder neuartige Funktionalitäten
zu erreichen. Darüber hinaus werden Grundlagen
für neue Forschungsgebiete am IHP geschaffen.
Gegenstand der Arbeiten sind neue Hoch-k-Dielektrika
sowie die Erforschung neuer Prinzipien für Hochleistungs-
Schaltkreise unter Nutzung von Nanostrukturen bzw. optischer
Datenübertragung. An den letztgenannten Zielen
wird in einem gemeinsamen Labor mit der BTU Cottbus
gearbeitet.
Aktuelle Schwerpunkte der Arbeiten zu neuen Hoch-k-Dielektrika
sind praseodymhaltige ternäre Legierungen für
zukünftige Anwendungen in MIM-Kondensatoren, Speichern
und Transistoren sowie als Epitaxievermittler für
hochwertige heteroepitaktische Halbleiterschichten (SIS-
Schichtstapel). Weiterhin werden neue Materialien für
SAW-Filter und NVM-Speicher bewertet.
Gegenstand der Arbeiten im Gemeinsamen Labor mit der
BTU Cottbus ist die Si-Materialforschung. Dabei sollen die
Eigenschaften des Si-Materials maßgeschneidert werden,
um neue Anwendungen zu ermöglichen und um bestehende
Anwendungen zu verbessern.
Schwerpunkte sind die grundlagenorientierte Vorlaufforschung
zu Si-basierten Lichtemittern für die optische Datenübertragung,
zum Defect Engineering für zukünftige
Si-Wafer sowie für eine selbstorganisierte Anlagerung von
Biomolekülen an der Si-Oberfläche, zum Bandstrukturdesign
und Ladungsträgertransport in Si-basierten Quantenstrukturen
und zur Beherrschung der elektrischen Eigenschaften
von Kristalldefekten in Solar-Si.
F o r s c h u n G d e s i h p – i h p ‘ s r e s e a r c h
IHp’s 0.25 µm BiCMoS technologies are available
in europe and throughout the world for designers.
A schedule for technological runs in
the pilot line in Frankfurt (oder) is available
via IHp`s internet address. A new 0.13 µm SiGe
BiCMoS technology is under development.
Materials for Micro- and nanoelectronics
Materials research at IHp targets the integration of
new materials into the technology to achieve additional,
better or innovative functionalities. It also
gears towards the preparation of new research fields
at the institute.
Subject of the research are new high-k dielectrics
and the research of new concepts for high-performance
circuits using nanostructures or optical data
transmission. the latter work is done at the Joint lab
IHp / Btu Cottbus.
Current focal points of the activities with high-k
dielectrics are ternary alloys with praseodymium for
future applications in MIM capacitors, memories and
transistors as well as for epitaxy mediation for high
quality epitactical semiconductor layers (silicon-
insulator-silicon stacks). Additionally, new materials
for SAW filters and non-volatile memories are evaluated.
Silicon materials research is the subject matter of the
Joint lab IHp / Btu. Silicon properties are tailored
to enable new applications and to improve existing
ones.
Focuses are initial basic research for Si-based light
emitters for optical data transmission, defect engineering
for future silicon wafers, self organized adsorption
of biomolecules on the silicon surface, band
structure design and charge carrier transport in Sibased
quantum structures, and the control of electrical
properties of crystal defects in solar silicon.
A n n u A l R e p o R t 2 0 0 6

A n n u A l R e p o R t 2 0 0 6
d a s J a h r 2 0 0 6 – u p d a t e 2 0 0 6
Update 2006

Das Jahr 2006
Im Jahr 2006 gab es zahlreiche Initiativen zur weiteren
Vernetzung der Forschung des IHP und zur Vorbereitung
neuer Forschungsprojekte.
Wissenschaftler des IHP waren tätig als Initiatoren, Organisatoren
oder Vortragende wissenschaftlicher Konferenzen
und Workshops auf allen Forschungsgebieten
des IHP. Beispiele für maßgeblich durch IHP-Mitarbeiter
organisierte internationale Veranstaltungen sind
drei Symposien beim E-MRS Spring Meeting in Nizza
(Symposium A „Current Trends in Nanoscience“, Symposium
L „Characterisation of High-k Dielectric Materials“
und Symposium V „Advanced Silicon for the 21 th
Century“), die internationale Konferenz „Extended
Defects in Semiconductors“ in Halle, der Workshop
„SiGe:C HBT: Device Technology and Applications“ bei
der European Microwave Week in Manchester sowie der
Workshop „From Research to Innovation“ in Szczecin.
IHP-Mitarbeiter waren beteiligt bei der Organisation
des „Workshops on Dielectrics in Microelectronics“
(WoDiM) in Catania, eines Symposiums „Silicon Materials
Science and Technology“ in Denver und eines Symposiums
„SiGe: Materials, Processing and Devices“ in
Cancun.
In Frankfurt (Oder) wurden durch das IHP mehrere internationale
Veranstaltungen organisiert, so ein Workshop
mit dem National NanoFab Center (NNFC) Korea,
das Symposium „Halbleiter und Nanostrukturen“, der
5. Workshop zu „High-Performance SiGe BiCMOS for
Wireless and Broadband Communication“ mit anschließendem
Tutorial zu „IHP Design Kits“ sowie der internationale
Sommerstudiengang Mikroelektronik mit
Studenten aus Osteuropa.
Die Kooperationen des IHP mit regionalen Universitäten
und Fachhochschulen konnten weiter ausgebaut
werden. Die Forschungsarbeiten des Gemeinsamen Labors
mit der BTU Cottbus fanden internationale Anerkennung.
Sie sind ein wichtiger Bestandteil der langfristigen
Vorlaufforschung des IHP. Ein gemeinsames
Forschungs- und Ausbildungszentrum des IHP und der
TFH Wildau wurde eröffnet. Mit der TU Berlin wurde ein
Kooperationsvertrag unterzeichnet. Das IHP bewarb
sich zusammen mit der TU Berlin und weiteren Berliner
d a s J a h r 2 0 0 6 – u p d a t e 2 0 0 6
update 2006
the year 2006 produced numerous initiatives for the
further networking of the institute’s research and for
the preparation of new research projects.
Scientists of the IHp were active as initiators, organizers
or speakers at scientific conferences and workshops
on all major spheres of IHp’s activities. examples
of international meetings significantly organized
by IHp staff are three symposia at the e-MRS Spring
Meeting in nice (symposium A “Current trends in nanoscience”,
symposium l “Characterisation of High-k
Dielectric Materials” and symposium V “Advanced Silicon
for the 21th Century”), the international conference
“extended Defects in Semiconductors“ in
Halle, the workshop “SiGe:C HBt: Device technology
and Applications” at the european Microwave Week in
Manchester as well as the workshop “From Research
to Innovation“ in Szczecin.
IHp co-workers were actively involved in the organization
of the “Workshops on Dielectrics in Microelectronics”
(WoDiM) in Catania, a symposium “Silicon
Materials Science and technology” in Denver and a
symposium “SiGe: Materials, processing and Devices”
in Cancun.
Several international meetings in Frankfurt (oder)
were organized by the IHp, such as a workshop with
the national nanoFab Center (nnFC) Korea, the symposium
“Semiconductors and nanostructures”, the
5th workshop “High performance SiGe BiCMoS for
Wireless and Broadband Communication” followed by
a tutorial about “IHp Design Kits” as well as the “International
Summer School on Microelectronics” with
students from eastern europe.
Cooperations of the IHp with regional universities
and universities of applied sciences were further developed.
Research at the Joint lab with the Btu Cottbus
gained international recognition. they are an essential
part of the long-term research at the IHp.
the common research and education centre of the
IHp and the university of Applied Sciences Wildau
(tFHW) was inaugurated in February. this Joint lab
unites important competencies in research and education
of both partners. A cooperation contract
A n n u A l R e p o R t 2 0 0 6

Forschungseinrichtungen als Exzellenzcluster „Human-
Centric Communication“. Die Europa-Universität Viadrina
und das IHP bieten ihr Know-how den Unternehmen
der Region an. Dazu wurde im Juli 2006 das gemeinsame
Transferzentrum Ostbrandenburg gegründet.
Die internationale Kooperation des Institutes konnte
im Jahr 2006 weiter ausgebaut werden. Das dokumentiert
sich unter anderem in den neuen Kooperationsvereinbarungen
mit der Tohoku Universität Sendai in Japan,
mit der TU Szczecin, MOUs mit dem NNFC und dem
ETRI in Korea sowie in dem Beginn der Zusammenarbeit
mit der National-Taiwan-University in Taipeh.
Die Designerin Li Wang wurde 2006 auf zwei IEEE-Konferenzen
mit einem „Best Paper Award“ ausgezeichnet.
Sie erhielt die Ehrungen für einen Micromixer für 77 GHz
Radar (International Microwave Symposium, San Francisco)
und für einen Frequenzteiler (6 th Topical Meeting
on Silicon Monolithic Integrated Circuits in RF Systems,
San Diego). Der Mitarbeiter des Gemeinsamen Labors
mit der BTU Cottbus, Tzanimir Arguirov, erhielt für seine
Präsentation den „Young Scientist Award“ eines EMRS-
Symposiums in Nizza.
Durch ein hochrangiges Gutachtergremium des BMBF
wurde im Rahmen des Programms InnoProfile das
IHP-Projekt „TANDEM“ ausgewählt, in dem extrem
verbrauchsarme Funksysteme für sensorische Anwendungen
entwickelt werden.
6 A n n u A l R e p o R t 2 0 0 6
d a s J a h r 2 0 0 6 – u p d a t e 2 0 0 6
with the Humboldt university of Berlin was signed.
together with the technical university of Berlin and
other Berlin research institutions the IHp applied
for becoming a cluster of excellence “Human Centric
Communication”. the european university Viadrina
and the IHp jointly offer their know-how to regional
companies. For this purpose the “transfer Center east
Brandenburg” was founded in July 2006.
the international cooperation of the institute was further
developed in 2006. this is documented amongst
others by new cooperation agreements with the tohoku
university Sendai in Japan, with the Szczecin university
of technology, by Mous with the nnFC and the
etRI in Korea as well as by the beginning of cooperation
with the national taiwan university in taipeh.
the RF designer li Wang was presented with the “Best
paper Award” at two Ieee-conferences in 2006. She
received the awards for a 77 GHz radar micromixer
(International Microwave Symposium, San Francisco)
and for a frequency divider (6th topical Meeting on
Silicon Monolithic Integrated Circuits in RF Systems,
San Diego). the scientist of the Joint lab IHp / Btu
Cottbus,tzanimir Arguirov, received the “Young Scientist
Award“ for his presentation of an eMRS-symposium
in nice.
In the framework of the BMBF program Innoprofile
the IHp-project tAnDeM was selected by a high-ranking
referee team. tAnDeM will develop radio systems
for sensor applications with very low power consumption.

Wissenschaftliche Ergebnisse
Drahtloses Internet: Systeme und Anwendungen
Die Ergebnisse dieses Forschungsprogramms wurden
insbesondere durch die Abteilungen System Design und
Circuit Design unter Nutzung der Ergebnisse anderer
Abteilungen erarbeitet. Schwerpunkte sind Si-basierte
Schaltungen und Systeme mit extrem hohen Leistungsparametern
als Schlüssel für neue Anwendungsfelder.
Beispiele für Ergebnisse im Jahr 2006 sind:
1. Integrierte Lösungen für Systeme zur drahtlosen
Kommunikation mit sehr hohen Datenraten
Die Schaltkreise für 60-GHz-Receiver und -Transmitter
wurden optimiert. Im Juni 2006 wurde mit sehr
großem Erfolg ein vollständiges 60-GHz-Übertragungssystem
realisiert und auf dem Statusseminar
des BMBF in Erlangen demonstriert. Sowohl die 60-
GHz-Schaltungen als auch die 5-GHz-Schaltungen
für die Zwischenfrequenz-Bearbeitungen arbeiteten
wie spezifiziert. Das Basisband wurde vollständig
realisiert und auf FPGA-Boards mit dem HF-Frontend
integriert. Datenraten bis zu 780 Mbps konnten
übertragen werden. Damit positioniert sich das
IHP gleichauf mit IBM im internationalen Vergleich
von drahtloser Gigabit-Kommunikation bei 60 GHz.
Zusätzlich wurde ein Vorschlag des IHP zur Standardisierung
bei der TG 15.3c der IEEE 802 Initiative
eingereicht. Hier gibt es inzwischen eine enge Kooperation
mit France Telecom und anderen großen
Firmen.
2. Radarsensoren bei 24 GHz und bei 77 GHz
Nach erfolgreichen Arbeiten zu Radarsensoren bei 24
GHz wurde im August 2006 die Firma „Silicon Radar“
aus dem IHP ausgegründet. Die Firma wird in Kooperation
mit einem Industriepartner eine finale Version
für die Fertigung von spannungsgesteuerten Oszilatoren
(VCOs) für kommerzielle Radarmodule sowie
LNAs und Mischer erarbeiten. Am IHP wird in einem
Projekt an grundlegenden Lösungen für ein Single-
Chip Radar-Frontend bei 24 GHz gearbeitet.
d a s J a h r 2 0 0 6 – u p d a t e 2 0 0 6
scientific results
wireless internet: systems and applications
the results of this research program were obtained
in particular by the departments System Design and
Circuit Design using also the results from other departments.
emphasis here is on circuits and systems
with extremely high performance parameters as keys
for new application fields.
examples of results in 2006 are:
1. Integrated solutions for wireless communication
systems with very high data rates
the 60 GHz receiver and transmitter circuits were
optimized. In June 2006 a complete data transmission
system for 60 GHz was very successfully
realized and presented at the BMBF status seminar
in erlangen. Both the circuits at 60 GHz and
at 5 GHz for the intermediate frequency worked as
specified. the base band was completely realized
and integrated on FpGA boards together with the
RF frontend. Data rates up to 780 Mbps could be
transferred. thus the IHp positions itself on the
same level with IBM in wireless Gigabit communication
at 60 GHz. In addition, IHp submitted a
suggestion for the standardisation to tG 15.3c of
the Ieee 802 initiative. In the meantime a close
collaboration with France telecom and other big
companies was established.
2. Radar sensors at 24 GHz and at 77 GHz
After successful work on radar detectors at 24 GHz
the IHp spin-off “Silicon Radar” was founded in
August 2006. In cooperation with an industrial
partner the company will develop a final version
for the manufacturing of voltage-controlled oscillators
(VCos) for commercial radar modules as well
as lnAs and mixers. At the IHp a project is under
way on fundamental solutions for a single chip radar
frontend at 24 GHz.
A n n u A l R e p o R t 2 0 0 6
7

Die 77-GHz-Komponenten für das FMCW-Radar wurden
weiter optimiert. Ein Breitband-VCO mit hoher
Ausgangsleistung konnte realisiert werden.
3. Schnelle A / D- und D / A-Umsetzer
In einem internen Projekt wurde ein schneller A / D-
Wandler mit 12 GSps und 4 Bit Auflösung (3,2 ENOB)
realisiert. Ein Drittmittelprojekt zur Realisierung von
A / D- und D / A-Wandlern für Ultra-Breitband-Funksysteme
konnte eingeworben werden. Als wichtige
Komponenten für schnelle A / D-Wandler wurden ein
Komparator mit 20 GHz Taktrate, 4 mV Auflösung und
40 mW Verlustleistung sowie ein schneller Track-And-
Hold-Verstärker mit 10 GSps, 7,8 Bit (ENOB) Auflösung
realisiert und bei der ESSCIRC präsentiert.
4. Single-Chip PLL-Frequenzsynthesizer
Zwei Projekte zur Realisierung von kostengünstigen
vollintegrierten Frequenzsynthesizern bei 10 und
19 GHz für die breitbandige Satellitenkommunikation
wurden in Zusammenarbeit mit der ESA begonnen.
In diesem Rahmen wurden als kritischste
Bauelemente zwei VCOs mit hervorragenden Phasenrauschwerten
sowie ein kompletter Frequenzsynthesizer
in SiGe BiCMOS mit Fractional-N PLL
und Delta-Sigma-Modulator realisiert. Die Funktionalität
konnte mit zwei Einzelchips (CMOS und
BiCMOS) gezeigt werden. Die Realisierung eines
Single-Chip Synthesizers wird folgen.
Zudem wurden theoretische Untersuchungen zum
Phasenrauschen in Fractional-N PLLs durchgeführt,
sowie ein Simulationswerkzeug in Matlab
implementiert, um die anspruchsvollen Phasenrauschanforderungen
erreichen zu können.
8 A n n u A l R e p o R t 2 0 0 6
d a s J a h r 2 0 0 6 – u p d a t e 2 0 0 6
the 77 GHz components for the FMCW radar were
further optimized. A broadband VCo with high
output power was realized.
3. Fast A / D- and D / A-converters
A fast A / D-converter with 12 GSps and 4 bit resolution
(3.2 enoB) was realised in an internal project.
A third-party funded project for the development
of A / D- and D / A-converters for uWB radio
systems was acquired. As important components
for fast A / D-converters a comparator with 20 GHz
clock rate, 4 mV resolution and 40 mW power dissipation
as well as a fast track-and-hold amplifier
with 10 GSps, 7.8 bits (enoB) resolution was realized
and presented at the conference eSSCIRC.
4. Single chip pll frequency synthesizer
In collaboration with the european Space Agency
(eSA) two projects were started for the realization
of cost-effective fully integrated frequency synthesizers
at 10 GHz and 19 GHz. As most critical
devices also two VCos with excellent phase noise
as well as a complete frequency synthesizer with
fractional-n pll and Delta-Sigma-Modulator were
realized in SiGe BiCMoS. the functionality was
demonstrated with two single chips (CMoS and
BiCMoS). the next step will be a single chip synthesizer.
Additionally, theoretical investigations concerning
the phase noise in fractional-n plls were
performed. A simulation tool was implemented
in MAtlAB to fulfil the challenging phase noise
requirements.

5. Integriertes Wireless-Bus-System für medizinische
Anwendungen
Die Arbeiten fanden im Rahmen des Projektes BA-
SUMA statt. Die Knotenarchitektur des Body-Area-
Netzes wurde realisiert und erfolgreich getestet. Das
generische, ereignisgesteuerte Betriebssystem RE-
FLEX wurde portiert und zusammen mit einer innovativen
SDL-Laufzeitumgebung integriert. Dadurch
werden die Entwicklungszeiten für MAC- und Netzwerkprotokolle
deutlich verkürzt. Das IEEE802.15.3
MAC-Protokoll wurde auf dieser Plattform realisiert
und zusammen mit einem MAC-Hardwarebeschleuniger
integriert.
Ausgehend von diesen Ergebnissen wurden verschiedene
weiterführende Projekte zu Sensornetzwerken
initiiert. So wurde zu diesem Thema das Projekt
„TANDEM“ im Rahmen der InnoProfile-Ausschreibung
des BMBF mit einer Förderung von 3 Mio. Euro
eingeworben.
6. Ultra-Wide-Band Schaltkreise
Das EU-Projekt „PULSERS 2“ (Nachfolger des Projektes
PULSERS) begann am 1. Januar 2006. Innerhalb
dieses Projektes wurden Arbeiten zum Systemkonzept
durchgeführt. Zusätzlich wurden in einem
internen IHP-Projekt verschiedene Komponenten
für ein impulsbasiertes UWB-Frontend entwickelt
und Ergebnisse auf internationalen Konferenzen
publiziert.
7. Modulare Prozessor-Bibliothek
Der LEON-Prozessor ermöglicht in seiner strahlungssicheren
Variante die Anwendung der Sensorknoten
des IHP im Weltraum. Dazu wird eine eigene Bibliothek
entwickelt und es werden schaltungstechnische
Varianten untersucht. Das IHP hat einen LEON-3 FT
Prozessor realisiert, der nach den Vorgaben der ESA
als strahlungsfest eingesetzt werden kann. Ziel dieser
Arbeiten ist es, das IHP als einen zugelassenen
Komponentenlieferanten der ESA zu etablieren. Mit
den schnellen SiGe-Technologien des IHP ist sowohl
eine hervorragende Hochfrequenz-Performance als
auch eine hohe Integration erreichbar.
d a s J a h r 2 0 0 6 – u p d a t e 2 0 0 6
5. Integrated wireless bus system for medical
applications
the research was performed in the framework of
the project BASuMA. the node architecture of the
body-area-network was realized and successfully
tested. the generic, event-controlled operating
system ReFleX was ported and integrated together
with an innovative SDl cycle time environment.
In this manner, the development periods
for MAC and network protocols are significantly
shortened. the Ieee 802.15.3 MAC protocol was
realized on this platform and integrated together
with the MAC hardware accelerator.
Based on these results, new projects on sensor
networks were initiated. As an example, the project
tAnDeM in the framework of the BMBF initiative
Innoprofile was won with euro 3 million
funding.
6. ultra-wideband circuits
the european project pulSeRS 2 (successor of the
project pulSeRS) started January 1, 2006. In this
project a system concept was drafted. Additionally,
various components for an impulse-based uWB
frontend were developed in an IHp-project and
published at international conferences.
7. Modular processor library
the radiation hard version of the leon processor
enables the use of IHp’s sensor nodes in outer
space. For this purpose a new library is under development
and special circuit versions are tested.
the IHp has developed a leon-3 Ft processor for
radiation hard applications according to the eSA
requirements. the intention of this work is the establishment
of the IHp as a listed component supplier
for the eSA. IHp’s high frequency SiGe technologies
allow for an excellent RF performance as
well as for a high level of integration.
A n n u A l R e p o R t 2 0 0 6

8. Spezifische Lösungen bei 5 GHz
Die Arbeiten im EU-Projekt WINDECT wurden erfolgreich
beendet. Das Ergebnis ist ein neuartiger
MAC-Prozessor, der als weltweit erster Prozessor die
HCCA Mode der 802.11e Spezifikation erfüllt. Der
HCCA Mode dient im Wesentlichen der Unterstützung
einer garantierten Übertragungsqualität in
drahtlosen Netzen. Die Ergebnisse sind notwendige
Voraussetzung für das Projekt HOMEPLANE, ein im
BMWi Wettbewerb NGM eingeworbenes Projekt zu
drahtlosen Heimnetzen. Dieses Projekt liefert auch
die Basis für die Arbeiten des IHP im Bereich der
Car-2-Car Kommunikation, die in zukünftigen Fahrzeugen
die Verkehrssicherheit erhöhen soll.
9. Ein neues Konzept für Kryptoprozessoren
Im Bereich der kontextsensitiven drahtlosen Internetanwendungen
wurden Erfolge bei Kryptoprozessoren
erzielt. Die Prozessoren des IHP unterstützen
durch den neuartigen modularen Aufbau verschiedene
elliptische Kurven und unterschiedliche AES
Sicherheitsstufen. Zusätzlich konnte der Datendurchsatz
gesteigert werden. Zum Thema Kryptoprozessoren
wurden zahlreiche Masterarbeiten geschrieben,
von denen eine als beste Masterarbeit
der Fakultät 1 der BTU Cottbus ausgezeichnet wurde.
Zwei Patente wurden im Rahmen dieser Arbeit
angemeldet.
Technologieplattform für drahtlose und Breitbandkommunikation
Im Jahr 2006 wurde sowohl an der Sicherung der Stabilität
der existierenden 0,25-µm-BiCMOS-Technologien
und in ausgewählten Punkten an deren Weiterentwicklung
als auch an einem neuen 0,13-µm-BiCMOS-
Prozess gearbeitet. Die 0,13-µm-Technologie dient
der Erforschung neuer Bauelemente-, Schaltungs- und
Systemkonzepte und soll zusätzlich zu den 0,25-µm-
Technologien im MPW- und Prototyping Service des IHP
angeboten werden.
20 A n n u A l R e p o R t 2 0 0 6
d a s J a h r 2 0 0 6 – u p d a t e 2 0 0 6
8. Specific wireless solutions at 5 GHz
the eu-project WInDeCt was finished successfully.
the result of the project is the first MAC processor
worldwide that realizes the HCCA mode of the
802.11e specification. the HCCA mode basically
supports a data transmission with guaranteed
quality of service in wireless networks. these results
are a necessary prerequisite for HoMeplAne,
a project on wireless home networking, won in the
competition nGI of the BMWi. the WInDeCt results
are also the basis for IHp’s activities in the
area of car-2-car communication, which will increase
the traffic safety for future cars.
9. A new concept for crypto processors
Successes were achieved with crypto processors
for wireless internet applications. With their novel
modular setup the processors developed at the
IHp support different elliptic curves and different
AeS security levels. Additionally the throughput
was increased. numerous master theses were
written about crypto processors, with one of them
awarded as the best of the faculty 1 of the Btu
Cottbus. IHp applied for two crypto processor patents.
technology platform for wireless and broadband
communication
In 2006 there were activities both on the stability
of the existing 0.25 µm BiCMoS technologies and on
selected topics for their development as well as for a
new 0.13 µm BiCMoS process. the 0.13 µm technology
is necessary for studying new concepts for devices,
circuits and systems. In addition to the 0.25
µm technologies it will be offered in the MpW and
prototyping Service of the IHp.

Beispiele für Ergebnisse 2006 sind:
1. Weiterentwicklung der 0,25-µm- und Entwicklung
der 0,13-µm-BiCMOS-Technologie
Für eine komplementäre BiCMOS-Technologie wurde
ein neues Bipolar-Integrationskonzept entwickelt,
das speziell auf niedrige Prozesskosten abzielt.
Mit dem neuen Kozept können drei npn-HBTs mit
f T / BV CEO -Werten von 40 GHz / 5 V , 63 GHz / 3,5 V , und
120 GHz / 2,1 V zusammen mit einem 32 GHz / 4,4 V
pnp SiGe HBT mit nur drei zusätzlichen Maskenschritten
im Vergleich zum unterliegenden CMOS-
Prozess hergestellt werden. Diese Ergebnisse wurden
im Dezember 2006 auf der IEDM in San Francisco
vorgestellt.
Es konnten deutliche Fortschritte bei der Entwicklung
der 0,13-µm-SiGe-BiCMOS-Technologie erzielt
werden. So wurde der Prozess der Maskendatengenerierung
für 0,13-µm-Masken etabliert und erfolgreich
mit der Erstellung des ersten vollständigen
Maskensatzes demonstriert. Im Juli wurden die Silizium-Wafer
für die Erstellung der MOS-Spicemodelle
fertig gestellt und die Daten für die Entwicklung der
0,13-µm-Bibliothek geliefert. Erste funktionierende
Testchips (4 Mbit SRAM) demonstrieren die Richtigkeit
des Technologiekonzeptes. Die Entwicklung der
Technologiemodule ist zum großen Teil abgeschlossen.
An einzelnen Modulen sind noch Optimierungsarbeiten
notwendig (z.B. Trenchfill, Metallisierung).
Für die zwei Technologievarianten SG13B
(High Performance HBT mit minimalem CMOS) und
SG13S (vollständige 0,13-µm-BiCMOS) ist „Early
Access“ für Ende 2007 vorgesehen.
d a s J a h r 2 0 0 6 – u p d a t e 2 0 0 6
examples of results in 2006 are:
1. Further development of the 0.25 µm and develop-
ment of the 0.13 µm BiCMoS technology
A new low-cost, bipolar integration concept for a
complementary 0.25 µm BiCMoS technology was
developed. three npn HBts with f t / BV Ceo values of
40 GHz / 5 V, 63 GHz / 3.5 V and 120 GHz / 2.1 V
together with a 32 GHz / 4.4 V pnp HBt can be fabricated
with only three mask steps in addition to
the underlying CMoS core process. In December
2006 these results were presented at the IeDM in
San Francisco.
Considerable progress was made in the development
of the 0.13 µm SiGe BiCMoS technology. the
process of generating mask data for the 0.13 µm
level was developed and successfully demonstrated
by realizing a first complete mask set. In July
the silicon wafer for the extraction of the spice
models were completed and the data for the development
of the 0.13 µm library were delivered.
First working 4 Mbit SRAM test chips proved the
technology concept. the development of the
technology modules is close to completion. Some
modules such as trench fill and metallization
still need optimisation. early access for the two
technology versions SG13B (high performance
HBts with minimum CMoS) and SG13S (complete
0.13 µm BiCMoS) is planned for the end of 2007.
A n n u A l R e p o R t 2 0 0 6
2

2. Flash Speicher
Die Technologie für integrierte Flash Speicher konnte
stabilisiert und weiter optimiert werden. Um
weitere Verbesserungen der Parameter (z.B. Read
Access) des 65 kB Stacked-Gate Flash-Speichers zu
erreichen, wurde eine zusätzliche Design-Iteration
durchgeführt und es konnte eine Lesezugriffszeit
von 50 ns demonstriert werden. Für die Speicher
auf Basis der Single-Poly-Zellen (Speichertechnologie
für eine besonders kostengünstige Integration
kleiner Speicher) sind erste IP-Speicherbausteine
entworfen und erfolgreich getestet worden: ein 1kBit-Flash-Speicher
und ein 8 Bit nichtflüchtiges
Register. Zuverlässigkeitsuntersuchungen für beide
Technologievarianten werden 2007 durchgeführt
und abgeschlossen. Der Leiter des Projektes,
Alexander Fox, konnte die Ergebnisse in seiner Promotionsarbeit
mit Auszeichnung verteidigen.
3. Neue LDMOS
Durch ein neues Bauelementekonzept mit verändertem
Driftgebiet konnte die Zuverlässigkeit der
LDMOS-Transistoren entscheidend verbessert werden.
Dieses Konzept ist die Basis für die Integration
in die 0,13-µm-BiCMOS-Technologie.
4. Weltweite Nutzung der IHP-Technologien durch
MPW & Prototyping Service
Die regelmäßigen Technologie-Shuttles am IHP
ermöglichen auch Hochschulen, Forschungseinrichtungen
und Industriepartnern die Präparation
innovativer Entwicklungsmuster und Prototypen.
Durch Verbesserung der Infrastruktur konnte die
Betreuung der Partnerprojekte und deren Zugriff auf
wichtige Informationen weiter qualifiziert werden.
Durch Einführung einer neuen Software gelang es,
die Generierung der Maskendaten zu verbessern und
Fehlerquellen zu reduzieren. 2006 konnten die erzielten
Drittmitteleinnahmen erhöht werden. Eine
wesentliche Ursache für das sehr gute Ergebnis ist
die Attraktivität der angebotenen BiCMOS-Technologien.
22 A n n u A l R e p o R t 2 0 0 6
d a s J a h r 2 0 0 6 – u p d a t e 2 0 0 6
2. Flash memory
the technology for integrated flash memory was
stabilized and further optimized. Additional design
iteration was made to improve the parameters
(e.g. read access) of the 65 kB stacked gate
flash memory. A read access time of 50 ns was demonstrated.
First Ip memory blocks (a 1 kbit flash
memory and an 8 bit non-volatile register) were
designed and tested successfully for the memories
based on single poly cells, which is a technology
for the cost-effective integration of small memories.
Reliability tests for both technology versions
will be made and completed in 2007. the project
leader, Alexander Fox, defended the results of his
graduation work with honour.
3. new lDMoS devices
the reliability of the lDMoS transistors was improved
essentially by a new device concept with
a changed drift area. the lDMoS integration into
the 0.13 µm BiCMoS technology will be based on
this concept.
4. Worldwide use of the IHp technologies by the
MpW and prototyping Service
the regular IHp technology shuttles also allow
universities, research institutions and industrial
partners to prepare innovative development samples
and prototypes. the support of partner projects
and their access to important information
was further qualified by an improved infrastructure.
the generation of mask data was improved
and the sources of error were reduced by using
new software. the third-party income was increased
in 2006. the major reason for this excellent
result is the attractiveness of the BiCMoS technologies
offered.

5. Projekt KOKON
In diesem BMBF-Verbundprojekt testen deutsche
Automobilhersteller und die Halbleiterindustrie
gemeinsam die Integration und Zuverlässigkeit von
Silizium-Millimeterwellen-Schaltkreisen (MMIC) für
die Anwendung als Radar-Sende / Empfangseinheit
(Anti-Kollisions-Radar, Nahbereichs-Radar) im Frequenzbereich
76 - 81 GHz. Wesentlich ist dabei die
Entwicklung von VCOs (Oszillatoren) mit Leistungsverstärkern
in SiGe-Technologien. Zusätzlich zu den
ursprünglich geplanten Aufgaben wurden von der
Universität Ulm designte VCOs mit IHP-Technologie
gefertigt.
Materialien für die Mikro- und Nanoelektronik
Ein Schwerpunkt der Materialforschung waren Hoch-k-
Dielektrika auf Basis von Praseodym und deren spezifische
Anwendungen. Am gemeinsamen Labor mit der
BTU Cottbus wurde auf neuen Gebieten wie Si-basierte
Quantenbauelemente und Lichtemitter gearbeitet.
Beispiele für Ergebnisse 2006 sind:
1. Globale Heteroepitaxie edler Schichten
Struktur, Defekte und die dielektrischen Eigenschaften
des kubischen Pr 2 O 3 (111) / Si(111)-Heteroepitaxie-Systems
wurden untersucht und bewertet.
Es konnte weiter gezeigt werden, dass auf
diesem System beim Vorhandensein vorteilhafter
Defektenergien ein einkristallines heteroepitaktisches
Schichtwachstum sowohl von Si(111) als
auch von Ge(111) mit besserer Qualität möglich
ist als auf dem Si(001)-Substrat. Dieser Effekt
kann durch eine geeignete Wärmebehandlung des
Schichtstapels noch verstärkt werden. Die Epitaxiebedingungen
für Si(111) auf Pr 2 O 3 (111) lassen
sich weiter dadurch verbessern, indem durch eine zusätzliche
dünne Y 2 O 3 -Schicht zwischen Pr 2 O 3 (111)
und Si(111) die Bildung eines amorphen Silikats
verhindert wird.
d a s J a h r 2 0 0 6 – u p d a t e 2 0 0 6
5. project KoKon
In this BMBF funded cooperation project German
automobile producers and the semiconductor industry
are jointly testing the integration and reliability
of Si-millimeter-wave integrated circuits
(MMIC) for application as radar transmitter / receiver
units (anti-collision-radar, short-range-radar)
in the frequency range 76 - 81 GHz. In this
context the development of VCos (voltage controlled
oscillators) with power amplifiers in SiGe
technologies is essential. In addition to the originally
planned tasks, VCos were designed by the
university of ulm in IHp technology.
Materials for Micro- and nanoelectronics
the main focus of the materials research was High-k-
Isolators on the basis of praseodymium and specific applications
for them. At the Joint lab IHp / Btu Cottbus
the research focus was on new areas such as integrated
silicon-based quantum devices and light emitters.
examples of results in 2006 are:
1. Global hetero-epitaxy of functional layers
Structure, defects and dielectric properties of the
cubic pr 2 o 3 (111) / Si(111)-hetero-epitaxial system
were investigated and evaluated. It was demonstrated
that in presence of advantageous defect
energies a single crystalline hetero-epitaxial
layer growth of Si(111) as well as of Ge(111) is
possilble with a higher quality than on an Si(001)
substrate. this effect can be enhanced by a suitable
heat treatment of the layer stack. the conditions
for epitaxy of Si(111) on pr 2 o 3 (111) can be
improved further by preventing the growth of an
amorphous silicate using an additional Y 2 o 3 -layer
between pr 2 o 3 (111) and Si(111).
A n n u A l R e p o R t 2 0 0 6
2

2. PrAlO 3 auf TiN-beschichteten Si(001)-Wafern
Die Untersuchungen an diesen Schichtstapeln
wurden im Hinblick auf den Einfluss von Defekten
auf das Leckstromverhalten in Speicherbauelementen
der nächsten Generation durchgeführt.
Wechselwirkungen zwischen dem Substrat und der
dielektrischen Schicht sowie Oberflächenkontaminationen
sind maßgebend für die Entstehung von
Defekten. Infolge chemischer Reaktionen an der
Interface ist ein defektkontrollierter Anstieg des
Leckstromes durch die Schicht mit wachsender Temperatur
zu beobachten.
3. Hoch-k-MIM-Kondensatoren
Der Einsatz von Hoch-k-Materialien in MIM-Kondensatoren
für Analoganwendungen dient der Flächenreduzierung
und erfordert eine ausreichende
Kapazitäts-Spannungs-Unabhängigkeit. Auf der
Grundlage eines physikalischen Modells für die
Spannungsabhängigkeit der Kapazität ist es möglich,
kritische Schichtdicken für dielektrische Materialien
zu bestimmen, für die die quadratische
Spannungsabhängigkeit einen akzeptablen Grenzwert
nicht überschreitet. Bei Kenntnis der kritischen
Schichtdicken ist auch die Berechnung der maximalen
Kapazitätsdichten möglich. Planare MIM-Kondensatoren
mit HfO 2 als Dielekrikum weisen eine
dreifach höhere Kapazitätsdichte als SiO 2 -basierte
MIM-Kondensatoren bei vergleichbarer Spannungslinearität
auf.
4. Silizium-basierte Lichtemitter
Direktes Silizium-Waferbonden (realisiert in Zusammenarbeit
mit dem MPI für Mikrostrukturphysik
Halle) erlaubt die reproduzierbare Erzeugung von
regelmäßigen Versetzungsnetzwerken. Dabei kann
für eine bestimmte Fehlorientierung ein Netzwerk
erzeugt werden, bei dem die D1-Linie dominiert.
Das ist die erforderliche Wellenlänge des Emitters
von 1,5 µm (Vortrag des IHP auf der IEDM 2005).
2 A n n u A l R e p o R t 2 0 0 6
d a s J a h r 2 0 0 6 – u p d a t e 2 0 0 6
2. prAlo 3 on tin-coated Si(001) wafers
the research on these layer stacks was performed
in view of the influence of defects on the leakage
current in next generation memories. Interactions
between the substrate and the dielectric layer as
well as surface contaminations determine the defect
generation. As a result of chemical reactions
at the interface a defect-controlled increase of
the leakage current with higher temperature is
observed.
3. High-k MIM capacitances
the use of high-k materials in MIM capacitances
for analog applications serves the reduction of silicon
area and requires a sufficient independence
of the capacitance from the applied voltage. Based
on a physical model for the voltage dependence
of the capacitance, critical thicknesses for
dielectric layers can be determined for which the
quadratic voltage dependence of the capacitance
remains below a critical value. If the critical layer
thicknesses are known, the maximum area capacitance
can be calculated. planar MIM capacitances
with Hfo 2 -dielectric have a three times higher
area capacitance compared to Sio 2 -based ones,
with comparable voltage linearity.
4. Silicon-based light emitters
Direct bonding of silicon wafers (realised together
with the MpI for Microstructure physics in Halle)
enables the reproducible formation of dislocation
networks. In this process a network can be formed
with light emission dominated by the D1-line for a
defined misorientation. this is the required emitter
wavelength of 1.5 µm (IHp’s IeDM-presentation
in 2005).

Im Jahr 2006 wurde dieses Konzept erstmals für
eine MOS-LED genutzt, bei der sich das Versetzungsnetzwerk
ca. 45 nm unterhalb des etwa 1,8 nm dicken
Tunneloxides befindet. Dieses Ergebnis wurde
in einem gemeinsamen Vortrag (IHP und MPI Halle)
auf der IEDM 2006 mit Erfolg präsentiert.
5. Silizium-basierte Nanostrukturen
Begonnen wurde mit Arbeiten zu Silizium-Nanodrähten
für die Mikroelektronik (in Kooperation
mit der Zhejiang Universität, China) sowie zu
Schichtstapeln aus dünnen Silizium-Schichten, die
in dünne Silizium-Oxid-Schichten eingebettet sind,
für die Photovoltaik der 3. Generation (in Zusammenarbeit
mit der RWTH Aachen).
Die Schichtstapel mit den dünnen Silizium-Schichten
lassen ein Bandgap-Engineering zu. Ab ca. 5 nm
Schichtdicke nimmt mit sinkender Dicke des Siliziums
die Breite der Energie-Bandlücke deutlich zu.
Dieser Effekt soll in Tandemstrukturen mit variierter
Bandlücke für zukünftige Si-basierte Höchsteffizienz-Solarzellen
ausgenutzt werden.
6. Silizium für die Mikroelektronik
Auf diesem Arbeitsgebiet wurde in Kooperation
mit der deutschen Industrie gearbeitet, um deren
Wettbewerbsposition zu stärken. In der Zusammenarbeit
mit der Siltronic AG für zukünftige Si-Wafer
wurden u.a. experimentelle und theoretische Arbeiten
zur Sauerstoffpräzipitation durchgeführt. Für
die Centrotherm GmbH + Co. KG wurde der Einfluss
der Hochtemperatur-Prozessierung auf die Vergleitung
in horizontal und vertikal gelagerten Si-
Wafern großen Durchmessers untersucht und eine
sehr gute Übereinstimmung mit Modellrechnungen
gefunden.
d a s J a h r 2 0 0 6 – u p d a t e 2 0 0 6
In 2006 this concept was applied for a MoS-leD for
the first time. In this device the dislocation network
is about 45 nm below the tunnel oxide with a
thickness of about 1.8 nm. this achievement was
successfully presented in a joint presentation of
IHp and the MpI Halle at the 2006 IeDM.
5. Silicon-based nano-structures
In cooperation with the Zhejiang university in
China we have started research on silicon nanowires
for microelectronics. We have also started
working together with the RWtH Aachen on stacks
of thin silicon layers embedded in thin layers of
silicon oxide, for application in third generation
photovoltaics.
using stacks of thin silicon layers allows Bandgap
engineering. Beginning at about 5 nm, the energy
of the band gap significantly rises with decreasing
layer thickness. this effect can be utilized in
tandem structures with varying band gap for future
solar cells of high efficiency.
6. Silicon for microelectronics
In this area we collaborated with the German industry
in order to strengthen their competitive
position. In cooperation with the Siltronic AG for
future silicon wafers we performed e.g. experimental
and theoretical work on the precipitation
of oxygen. For Centrotherm GmbH & Co. KG the
influence of high-temperature processing for gliding
processes in horizontal and vertical wafers of
high diameters was investigated. A very good correlation
with model calculations was found.
A n n u A l R e p o R t 2 0 0 6
2

26 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Selected Projects

Drahtloses Internet
WIGWAM - Wireless Gigabit with Advanced
Multimedia Support
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Ziel des IHP-Beitrages dieses vom BMBF geförderten
Projektes war es, ein Höchstgeschwindigkeits-Kommunikationssystem
mit Datenraten von 1 Gbps zu entwerfen
und prototypisch zu implementieren. Um den ständig
wachsenden Bedarf an Datenrate zu befriedigen,
gewinnt das 60-GHz-Band zunehmend an Bedeutung.
Viele Firmen und Forschungseinrichtungen beschäftigen
sich daher mit entsprechenden Systemen und
Schaltungen.
Die wesentlichen Beiträge des IHP am WIGWAM Projekt
sind prototypische Realisierung eines kompletten 60-
GHz-Kommunikationssystems, mit den Basiskomponenten
analog Frontend (AFE), Basisbandprozessor (BB)
und Medium Access Control Prozessor (MAC).
Die 60-GHz-Sender- und Empfänger-Chips konvertieren
das übertragene Signal auf eine Zwischenfrequenz von
5 GHz. Ein lokaler Oszillator mit geringem Phasenrauschen
ist für die OFDM Übertragung notwendig. Sowohl
für den Sender als auch für den Empfänger werden eine
56-GHz-PLL verwendet. Nach dem Hochmischen des Sig-
nals wird eine Pufferstufe mit großer Verstärkung eingesetzt.
Um die Gefahr des Schwingens zu verringern,
wurde dafür ein differentielles Design verwendet. Der
60-GHz-Sender wurde in einen Chip integriert, wie in
Abb. 1 ersichtlich. Dieser enthält drei wesentliche Blöcke:
die 56-GHz-PLL, einen Mischer sowie einen 60-GHz-
Ausgangspuffer. Der Mischer beruht auf einer Gilbert
Topologie. Für den zweistufigen Ausgangpuffer kam
eine Kaskode-Topologie zum Einsatz, die eine Verstärkung
von 20 dB erreicht und eine bessere Linearität
als eine Common-Emitter-Schaltung aufweist. Zwei
Leiterplatten für Sender und Empfänger wurden entworfen.
Diese bestehen aus dem, im Vergleich zu Keramiksubstraten,
kostengünstigen Rogers 3003 Material.
Die nackten Chips wurden auf das Substrat in einer
Silicon-on-Board Technologie (SOB) montiert. Zur Verbindung
kommen kurze Bonddrähte zum Einsatz. Abb.
2 zeigt die Empfänger-Platine. Der Sender wurde auf
die gleiche Weise hergestellt. Teure und komplizierte
Packaging Technologien werden damit nicht benötigt.
wireless internet
wiGwaM - wireless Gigabit with advanced
Multimedia support
the IHp contribution to this BMBF funded cooperative
project was focused on the development and prototype
implementation of an ultra-high-speed communication
system with data rates of 1 Gbps. to satisfy
the rapidly growing demand for communication
bandwidth, the 60 GHz band has become more and
more attractive to many companies and research institutions.
We have recently completed and presented
the first version of a system demonstrator, operating
in this frequency band. this demonstrator comprises
three main blocks: the 60 GHz analog frontend (AFe),
the baseband processor (BB) and a high-throughput
medium access control processor (MAC). three departments
of IHp are involved in the project.
the 60 GHz receiver and transmitter chips convert the
60 GHz signal to an intermediate frequency (IF) of
about 5 GHz or vice versa, respectively. A low phase
noise local oscillator is required for oFDM application.
We used a pll working at 56 GHz for both the
receiver and the transmitter. After up conversion,
the signal is weak. A high gain buffer is needed to
amplify it. to reduce the risk of oscillations, we used
a differential design approach. A 60 GHz transmitter
frontend was integrated into a single chip as shown
in Fig. 1. three building blocks were integrated: A
56 GHz pll, an up converter mixer and a 60 GHz output
buffer. the up converter mixer utilizes a Gilbert mixer
topology as the core. A two stage cascode topology
was used as the 60 GHz output buffer which provides
a gain as high as 20 dB and better linearity compared
to a common emitter configuration. two boards
were designed for transmitter and receiver, respectively.
Rogers 3003 is used as the substrate instead
of ceramic because of the low cost. the bare chips
are mounted directly onto the boards in a silicon on
board (SoB) technology. they are connected to the
board by bond wires. Fig. 2 shows the receiver board.
the transmitter board was realized in the same way.
Complicated and expensive packaging techniques are
not required in this solution. A Vivaldi antenna with a
A n n u A l R e p o R t 2 0 0 6
27

Abb. 1: Chip Photo des 60-GHz-Senders.
Fig. 1: transmitter chip photo.
28 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Direkt auf der Leiterplatte ist auch eine Vivaldi Antenne
mit einem Öffnungswinkel von 30 Grad untergebracht.
Diese Antenne wurde von unserem Partner, dem IHE
der Universität Karlsruhe entwickelt.
Die ZF Modulator- und Demodulator-Chips wurden ebenfalls
am IHP entwickelt (Abb. 3). Der ZF-Empfänger
demoduliert das 5-GHz-Signal vom 60-GHz-Frontend
und generiert das komplexe Basisband I / Q Signal. Eine
programmierbare 10-GHz-PLL mit einem Frequenzteiler
erzeugt das I / Q Signal für den Sender und auch für
den Empfänger. Auf der Sendeseite wird das komplexe
I / Q Basisbandsignal mit einem I / Q Modulator auf die
Zwischenfrequenz von 5 GHz gemischt und dann an das
60-GHz-Frontend weitergeleitet.
Bislang wurde kein 60-GHz-Transceiver in Silizium Technologie
mit einem integrierten 60 GHz HF-Filter veröffentlicht.
Dieses Filter ist notwendig, um Interferenzen
mit benachbarten Kanälen zu vermeiden. Dazu wurde
ein LNA mit einem Bandpassfilter dritter Ordnung entworfen.
Der gemessene und simulierte Frequenzgang
dieses Filters ist in Abb. 4 dargestellt. Ein kompletter
Empfänger kann durch direkte Verbindung des LNA mit
dem Mischer ohne weitere HF-Filter implementiert werden.
Der Basisbandprozessor (BB) des WIGWAM Demonstrators
arbeitet mit der OFDM Übertragungstechnik.
Es werden acht verschiedene Datenraten unterstützt.
Diese reichen von 120 Mbps bis zu 1,08 Gbps. Eine neuere
Breitbandversion unterstützt auch Datenraten bis
radiation angle of about 30 degree is also integrated
into the boards. this antenna was developed by our
partner, the IHe at the university of Karlsruhe.
the IF modulator and demodulator chips were also
designed at IHp. the IF receiver demodulates the
5 GHz signal from the 60 GHz frontend output and
generates a complex baseband I / Q signal. A 10 GHz
programmable pll with a divide-by-two stage was
used to generate the quadrature lo signal for both
the receiver and the transmitter. the IF transmitter
modulates the baseband I / Q signal to 5 GHz IF signal
which feeds to the 60 GHz transmitter IF input.
Abb. 2: Leiterplatte mit Empfängerchip.
Fig. 2: Receiver board.
up to now, all published 60 GHz transceiver systems in
silicon technologies do not have an on chip RF filter,
which is necessary to avoid interference with other
systems working in a close frequency band. For this
purpose, a new lnA with a 3rd order bandpass filter
response was successfully designed and tested. the
measured and simulated lnA frequency response is
shown in Fig. 4. A complete receiver frontend can be
realized by directly connecting the lnA and the mixer
without any passive RF filter.
the Baseband processor (BB) of the WIGWAM demonstrator
is based on oFDM transmission and supports
eight different data rates ranging from 120 Mbps up
to 1,08 Gbps. A newer wideband version supports
higher rates up to 2 Gbps. the simulated frame-error

Abb. 3: LNA und Mischer Chip Photos.
Fig. 3: lnA and mixer chip photo.
Abb. 5: Paketfehlerraten bei einer Datenrate von 1920 Mbps
für verschiedene Kanäle.
Fig. 5: System performance of the high data rate mode
(1920 Mbps) for different channels.
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
zu 2 Gbps. Die Paketfehlerkurven in Abbildung 5 entstammen
Systemsimulationen für die Datenrate 1920
Mbps für vier verschiedene Kanalszenarien unter der
Annahme der perfekten Kanalschätzung. Die Paketgröße
betrug 2048 Datenbytes. Die vier Szenarien entsprechen
typischen Ausbreitungsbedingungen im Büro
für Sichtkontakt (CM 3.2) und ohne Sichtkontakt (CM
4) sowie entsprechenden Modellen in einer Bibliothek
(CM 5 und CM 6). Ungerichtete Antennen liegen den
Kanalmodellen zugrunde. Fehlerhafte Pakete müssen
in der Regel neu gesendet werden. Um den Einfluss von
solchen Paketen auf die effektive Datenrate vernachlässigen
zu können, ist eine Paketfehlerrate von unter
1% erstrebenswert. Von Interesse sind daher diejenigen
Punkte, wo die Fehlerkurven unter die 1%-Marke fallen.
Anhand der Charakteristiken des analogen Front-Ends
(Sendeleistung, Antennengewinn, Rauschzahl) lässt
Abb. 4: Gemessene und simulierte Verstärkung des LNA in
Abhängigkeit von der Frequenz.
Fig. 4: Measured and simulated lnA gain versus frequency.
curves shown in Fig. 5 represent the physical layer
system performance for the high data rate mode of
1920 Mbps for four different channel scenarios under
the assumption of perfect channel estimation. 2048
data bytes were used per frame. the four channel
scenarios are the office line-of-sight (loS) link (CM
3.2) and non-line-of-sight (nloS) link (CM 4) and
the library loS and nloS link scenarios (CM 5 and CM
6). omnidirectional antennas were assumed in the
simulations. A desirable packet error rate is below
1%, in which case the real throughput is hardly diminished
by erroneous frames, which usually have to
be retransmitted. the critical points are determined
by the 1%-crossings of the FeR curves. together with
the characteristics of the analogue frontend (trans-
Abb. 6: Analog Frontend Komponenten des IHP 60-GHz-
Demonstrators.
Fig. 6: Analog frontend components of the IHP 60 GHz
demonstrator.
A n n u A l R e p o R t 2 0 0 6
2

0 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
sich die erzielbare Reichweite für eine zuverlässige
Übertragung abschätzen.
Als Medium Access Control (MAC) Protokoll wurde eine
modifizierte Version des IEEE 802.15.3 MAC Standards
verwendet. Es läuft auf einer Hardware-Plattform, die aus
einem in IHP-Technologie gefertigten LEON Prozessor Chip
und einem FPGA besteht. In letzterem sind die externen
Interface und ein Hardware-Accelerator realisiert, der zeitkritische
Operationen wie die Berechnung der CRC Prüfsummen
mit der erforderlichen Performance ausführt.
Ein kompletter 60-GHz-Demonstrator für Datenraten bis
1 Gbps wurde entwickelt und ist in Abb. 6 zu sehen. Das
Analog Frontend basiert auf Schaltungen in der IHPeigenen
0,25-µm-SiGe-BiCMOS-Technologie. Die Basisbandverarbeitung
ist auf einer FPGA Plattform implementiert.
Dies erlaubt einen „Hardware-in-the-Loop”
Ansatz zur schnellen Verifikation des Analog Frontend.
Abb. 7: OFDM 16-QAM Konstellationsdiagramm mit kommerziell
verfügbarem Basisband Signal Generator.
Fig. 7: oFDM 16 QAM constellation diagram using commercial
baseband equipment.
Die maximale Datenrate, die wir mit diesem Demonstrator
bislang gezeigt haben, beträgt 720 Mbps. Dies wurde
auf dem BMBF Statusseminar in Erlangen im Juni 2006
vorgeführt. Ein 16-QAM Konstellationsdiagramm sowie
das Leistungsspektrum des OFDM-Signals sind in den
Abb. 7 bzw. 8 dargestellt. Die letztendliche Version des
Demonstrators wird eine Datenrate von > 1 Gbps übertragen
können. Gemeinsam mit internationalen Partnern
setzen wir unsere Arbeiten fort, die Ergebnisse dieses
Projektes in den IEEE802.15.3c Standard einzubringen.
mit power, antenna gain, noise figure), the maximum
range of reliable transmission can be estimated.
An adapted version of the Ieee 802.15.3 MAC standard
was utilized as Medium Access Control (MAC)
protocol. It runs on a hardware platform consisting
of a 32 bit leon processor fabricated in IHp 0.25 µm
CMoS technology and an FpGA implementing external
interfaces as well as a hardware accelerator. this component
allows implementing time critical functions
such as the CRC check with the performance needed.
A complete 60 GHz oFDM demonstrator for data rates
up to 1 Gbps was developed and implemented as shown
in Fig. 6. the analog frontend is based on circuits implemented
in IHp‘s 0.25 µm SiGe BiCMoS technology.
the baseband processor is implemented on an FpGA
platform. this allows a hardware-in-the-loop approach
for fast verification of the analog frontend.
Abb. 8: Leistungsspektrum der OFDM Unterträger mit SNR.
Fig. 8: Subcarrier power spectrum and SnR.
the maximum data rate achieved by our demonstrator
so far is 720 Mbps. It was shown at the BMBF Status
Seminar in erlangen in June 2006. We will continue
our work to further optimize the performance of the
demonstrator. the QAM constellation diagram and
subcarrier power spectra measured at the receiver are
shown in Figs. 7 and 8.
the final version will show the full data rate of >1
Gbps. In parallel, we will continue our efforts to contribute
our results to the Ieee802.15.3c standard.

HOMEPLANE
Der heutige Heimvernetzungsmarkt ist geprägt durch
die Heterogenität der Endgeräte und Anwendungen
ohne Interoperabilität. HOMEPLANE (Home Media
Platform and Networks) ist ein vom BMWi finanziertes
Projekt mit dem Ziel, bestehende Hemmnisse bei der
Einführung von Heimnetzen zu beseitigen und eine homogene,
benutzerfreundliche Plattform zu schaffen.
In einem Konsortium von fünf Partnern (Universität
Dortmund, Siemens, Microsoft, Lintec, IHP) werden Szenarien
und Geschäftsmodelle, Middleware, Sicherheit,
Benutzerschnittstellen und Medienübertragung behandelt.
Ein spezieller Schwerpunkt ist die drahtlose Übertragung
mit der benötigten Dienstgüte in einem WLAN
nach IEEE 802.11. Neben der Konsortialführung und
Untersuchungen zur Sicherheit ist dieses die wichtigste
Aufgabe des IHP im Projekt.
Ein funkbasiertes System hat deutliche Vorteile gegenüber
einer drahtgebundenen Lösung (Abb. 9). Der
Benutzer kann in einfacher Weise sein Netz zusammensetzen,
ohne eine komplizierte Verkabelung durchzuführen.
Die Funklösung bietet höhere Flexibilität, da
die Geräte ohne Aufwand positioniert werden können.
Darüber hinaus wird der Trend zu mobilen Endgeräten
unterstützt, der Anwender kann seine Dienste dort in
Anspruch nehmen, wo er es gerade bevorzugt.
Abb. 9: Skizze eines Heimnetzes auf WLAN Basis.
Fig. 9: Sketch of a home network based on WlAn.
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
hoMeplane
Currently, home networking is characterized by a mixture
of devices and applications without interoperability.
the project HoMeplAne (Home Media platform
and networks) is financed by the German Federal Ministry
of economics and technology with the aim to
eliminate obstacles in the introduction of home networks
by developing a homogeneous and user-friendly
platform.
A consortium of five partners (university of Dortmund,
Siemens, Microsoft, lintec, IHp) is investigating user
scenarios and business models, middleware, security,
user interfaces, and media data transmission. A special
focus is on wireless transmission with the required
quality of service in an Ieee 802.11 WlAn. Apart from
the consortium leadership and security issues this is
the main effort of the IHp in the project.
A wireless system offers major advantages compared
to wired solutions in a home network (Fig. 9). typical
users want to build up their system without the effort
for cabling. Wireless transmission offers higher flexibility,
since devices can be repositioned easily. Also,
the trend to mobile devices is supported; each user
can invoke his favorite applications wherever he finds
it convenient.
legend
dVb-t Digital Video Broadcast terrestrial
wlan Wireless local Area networks
bs Base Station
Gw Gateway
haG Home Automation Gateway
rc Remote Control
Vr Video Recorder
tV television
stb Set-top Box
dsl Digital Subscriber line
pc personal Computer
A n n u A l R e p o R t 2 0 0 6

Bei der Verwendung von WLAN als Basis der Heimvernetzung
gibt es einige Probleme zu lösen. Diese werden
in Zusammenarbeit mit dem Lehrstuhl für Kommunikationstechnik
der Universität Dortmund untersucht.
Erstens ist der Funkkanal anfällig für Störungen. Daher
sind besondere Maßnahmen nötig, um die Dienstgüte
für Medienübertragung wie z.B. Video zu garantieren.
Zweitens teilen sich alle Benutzer die limitierte Bandbreite.
Es ist insbesondere in Mehrfamilienhäusern eine
Herausforderung, allen Benutzern die erwartete Performance
zu liefern.
Der IEEE 802.11 Standard wurde für die Übertragung
gewählt, weil dieser zum de-facto WLAN-Standard geworden
ist. Dieses Protokoll wurde jedoch für die Computernvernetzung
entworfen und ist wenig geeignet für
Daten mit Echtzeit-Anforderungen. Die Arbeiten hierzu
setzen auf dem vorangegangenen EU-Projekt WINDECT
auf. Abb. 10 zeigt, wie dort die Dienstgüte für Audiodaten
in einem hybriden Telefonie / Daten WLAN Netz
bereitgestellt wurde. Den Audiodaten werden von der
Baisstation im „contention-free period“ Zeitintervalle
zugewiesen, in welchen mit garantierter Priorität übertragen
wird. Im darauf folgenden „contention period“
werden Daten übertragen, welche nach den üblichen
Algorithmen ihre Prioritäten aushandeln. Diese Lösung
setzt eine zentrale Netzstruktur voraus. Für das Heimnetz
wird eine Ad-hoc-Struktur bevorzugt. Die zu entwickelnden
Lösungen sind prinzipiell ähnlich, sind aber
erheblich aufwändiger um den Anforderungen mehrerer
Wohnungen und diverser Dienstgüteklassen gerecht zu
werden. Von zentraler Bedeutung ist, dass der vom IHP
entwickelte WLAN-Chipset an die untersuchten Algorithmen
angepasst werden kann.
2 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
When the home network uses wireless data transmission,
some challenges arise. the IHp is investigating
these in close cooperation with the Communication
technology Institute of the university of Dortmund.
First, the wireless channel is error-prone, requiring
special measures to guarantee the quality of service
needed for, e.g., streaming video. Secondly, all users
share the limited bandwidth. In houses occupied by
several families, specially designed procedures must
be used to supply the required performance to all
users.
the Ieee 802.11 standard was chosen because it has
become the de-facto WlAn standard. However, it was
developed for data transfer between computers and
not for streaming video with real-time requirements.
the project work builds on the previous eu-financed
WInDeCt project. Fig. 10 shows how the quality of
service for audio data was guaranteed in a hybrid telephone
/ data WlAn system. Base stations assign time
slots for audio data in the “contention-free period”.
In the “contention period” other data is transmitted
according to the usual algorithms for channel access.
this solution is based on a centralized structure. For a
home network, a decentralized configuration is preferable.
the newly developed procedures will be similar
in principle, but will be more complicated in order to
handle the requirements of neighboring users and varying
quality of service needs. An important feature
is that the IHp WlAn chipset can be adapted to the
investigated algorithms.

a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Abb. 10: Unterstützung der Dienstgüte für Audiodaten im WLAN.
Fig. 10: Support of quality of service for audio data in a WlAn.
Als weiterer Schwerpunkt bearbeitet das IHP die Sicherheitsaspekte.
Hierbei soll die Privatsphäre sowohl innerhalb
als auch zwischen den Wohneinheiten gewährleistet
sein, der Benutzer soll sicher von extern auf sein
Heimnetz zugreifen können. Eine sichere Fernwartung
des Netzes soll unterstützt werden, und es müssen die
Medieninhalte geschützt werden. Die entwickelten Verfahren
zur WLAN-Optimierung und Sicherheit werden in
einem Demonstrator vorgeführt.
the IHp is also working on the security aspects in
home networks. the goals are that privacy is protected
between neighbors as well as within a family,
that remote servicing can be done safely, that users
can access their network externally without security
risks, and that media content is protected adequately.
the developed methods for WlAn optimization
as well as security support will be presented in a demonstrator.
A n n u A l R e p o R t 2 0 0 6

Sichere Kommunikation mit Endgeräten
beschränkter Ressourcen
Der Einsatz mobiler Endgeräte sowie die Verwendung
von Sensornetzen stellen neue Herausforderungen an
die Realisierung einer sicheren Kommunikation. Die
auszutauschenden persönlichen und geschäftlichen
Daten müssen gegen unerlaubtes Mithören und Verfälschen
geschützt werden. Die hierfür verwendeten
kryptographischen Verfahren sind jedoch sehr rechenintensiv
und verbrauchen somit relativ viel Energie. Um
lange Nutzungszeiten bei sicherer Kommunikation zu
realisieren werden in diesem Projekt energieeffiziente
Hardwarebeschleuniger untersucht. Neben dem Energieverbrauch
sind auch die Kosten eines Hardwarebeschleunigers
von großer Bedeutung, da die Kosten für
einen Sensorknoten durch die zusätzliche Hardware nur
minimal erhöht werden dürfen.
Die Elliptische Kurven Kryptographie (ECC) ist ein
asymmetrisches Verschlüsselungsverfahren, das eine
herausragende Sicherheit bei relativ kurzen Schlüssellängen
aufweist. Die aufwändigste Operation hierbei
ist die Multiplikation von zwei jeweils mehrere hundert
Bit langen Polynomen. Diese kann bis zum Tausendfachen
beschleunigt werden, wenn geeignete Hardwarebeschleuniger
eingesetzt werden. Im Rahmen dieses
Projektes wurde eine Lösung entwickelt, die sich mit
geringem Designaufwand an die Anforderungen der jeweiligen
Einsatzumgebung anpassen lässt (Abb. 11).
A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
secure communication for resource
constraint devices
the use of mobile devices as well as the advent of
sensor networks raises new challenges for ensuring
a secure communication. personal and business data
have to be protected against eavesdropping and falsification.
this can be achieved by applying cryptographic
means. the problem is that they require a
lot of computing and significantly consume battery
power. In order to ensure long up times while still
communicating securely this project investigates energy
efficient hardware accelerators. For this class of
devices, cost is also an important issue since material
costs of e.g. sensor nodes should only increase by a
few euro cents.
elliptic Curve Cryptography (eCC) is a public key approach
that ensures a high level of security with relatively
short keys. the most complex operation is the
multiplication of two polynomials of several hundred
bits length. this operation can be sped up by three
orders of magnitude if appropriate hardware accelerators
are used. In this project we developed a solution
which can easily be adapted to current design goals
such as extremely small area consumption or low power
consumption (Fig. 11).
Abb. 11: Struktur einer 4-Segment 233 Bit Multiplikationseinheit.
Fig. 11: Structure of the 4-segment 233 bit multiplication unit.

Tabelle 1: Größe der Selektions- und Akkumulationseinheit
verschiedener Konfigurationen im Vergleich zu der
bisherigen fest-verdrahteten Lösung.
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Diese Flexibilität wird dabei durch den Einsatz der im
Rahmen des Projektes entwickelten Iterativen Karatsuba
Multiplikation ermöglicht. Anstelle eines monolithischen
Multiplikationsblockes ist die Multiplikation
dreigeteilt. Zuerst wird in einem Selektionsblock die
Multiplikation in eine Anzahl kleinerer Teil-Multiplikationen
aufgeteilt. Die Anzahl und Größe dieser partiellen
Multiplikationen bestimmt, wie schnell und groß
das Design am Ende wird. Wir haben drei bevorzugte
Designs: Ein 2-Segment-Setup, das 3 Clockzyklen
benötigt, das 4-Segment-Setup (9 Zyklen) und das
8-Segment-Setup (27 Zyklen). Im zweiten Schritt wird
in jedem Clockzyklus eine partielle Multiplikation in
einem kombinatorischen Multiplizierer berechnet. Die
Ergebnisse werden im dritten Schritt in der so genannten
Akkumulationseinheit zum Endergebnis zusammengefügt.
Die Selektions- und Akkumulationseinheiten sind dabei
hochregulär gestaltet. Das ermöglicht nicht nur ein hohes
Maß an Flexibilität, sondern benötigt auch weniger
Siliziumfläche. Im Vergleich zu einer ersten am IHP realisierten
fest verdrahteten Lösung können bis zu 70%
Fläche für das 8-Segment-Setup eingespart werden
(siehe Tabelle 1).
Flexibility was achieved by exploiting the Iterative
Karatsuba approach which was developed earlier in
this project. our multiplier does not apply one monolithic
multiplication block but three smaller pieces.
First, the large multiplication is broken down into a
set of smaller partial multiplications. the number
and the size of these partial multiplications determine
the performance and the size of the whole design.
We normally use the following three designs: a
2-segment design that needs only three clock cycles
for the complete multiplication, the 4-segment and
8-segment design which need 9 and 27 clock cycles,
respectively. the second step is the actual execution
of the partial multiplications in a combinatorial
multiplier. Its results will be finally aggregated in an
accumulation unit.
Both the selection and the accumulation units were
designed as a highly regular structure. the regularity
in the design is not only cornerstone of the flexibility,
but also implies benefits regarding silicon area.
A comparison of our current solution with its hardwired
predecessor shows that we can save up to 70%
of the silicon area (table 1).
selection accumulation summation original
sel. + acc. Method
2 segment 0.05 0.08 0.13 0.15
4 segment 0.05 0.09 0.14 0.39
8 segment 0.06 0.10 0.16 0.59
table 1: Silicon area of selection and accumulation unit of
different configurations compared to their predecessor
version.
A n n u A l R e p o R t 2 0 0 6

6 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Die benötigte Siliziumfläche und Energie pro Multiplikation
für eine Auswahl von Multiplizierern mit unterschiedlichen
Operanden und damit auch Schlüssellängen
sind in Abb. 12 dargestellt. Für fünf verschiedene
Operandengrößen sind je drei Setups aufgeführt, wobei
die Anzahl der Segmente angibt, in wie viele Teile die
Operanden zerlegt werden. Anhand der Parameter kann
man dann eine für die Anwendung optimale Konfiguration
aus Sicherheit (Schlüssellänge), Siliziumfläche
und Energieverbrauch wählen.
Mit den hier entwickelten Hardwarebeschleunigern wird
der Einsatz asymmetrischer Verschlüsselungsverfahren
sogar für den Bereich der ubiquitären Systeme ermöglicht.
Sie verbrauchen einerseits zur Realisierung ihrer
Aufgaben kaum Energie und andererseits kosten sie
nur wenige Euro-Cent wegen ihres geringen Flächenbedarfes.
the required silicon area and the energy per multiplication
for a set of multiplication units supporting
diverse operand sizes (i.e. key lengths) is depicted in
Fig. 12. For each operand size three setups are shown.
the number of segments represents the proportion of
the partial multiplication to the full size. Based on
the presented results one can find the optimal configuration
for each application – with the parameters
security (key length), silicon area and energy consumption.
the hardware accelerators developed in this project
allow the use of public key cryptography even for
ubiquitous systems. this is due to the fact that our
solution requires almost no energy and its production
cost is only a few euro cents due to its small size.
Abb. 12: Siliziumfläche (Blöcke) und Energieverbrauch (Linien)
verschiedener am IHP verwendeter Multiplizierer für
Schlüssellängen von 163 bis 571 Bit. Fläche und Energie-
verbrauch pro Multiplikation wurden für die 0,25-µm-
CMOS-Technologie des IHP gemessen.
Fig. 12: Silicon area (bars) and energy consumption (lines) of
diverse IHp multipliers and key length from 163 to 571 bit.
Area and energy per multiplication have been measured
for the IHp 0.25 µm CMoS technology.

Strahlungsresistente Chips
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Ziel des Projektes ist es, mit vorwiegend schaltungs-
technischen Mitteln, d.h. mit fehlertolerantem (FT) Design,
eine höhere Resistenz integrierter Schaltungen gegen
Fehlfunktionen zu erreichen, die insbesondere durch
hochenergetische Strahlung hervorgerufen werden.
Es existieren viele verschiedene Strahlungsarten sowohl
im Weltraum als auch in Kernreaktoren oder in den Teilchenbeschleunigern
der Hochenergiephysik. Elektronische
Bauteile sind dort erhöhter Belastung z.B. durch
Strahlung energiereicher Protonen oder schwerer Ionen
sowie Alpha-, Röntgen- oder Gammastrahlung ausgesetzt.
Neben den unterschiedlichen Langzeiteffekten im Halbleitermaterial,
die vorwiegend mit technologischen oder
Layout-technischen Mitteln reduziert werden müssen,
treten auch sogenannte Single-Event-Effekte auf, die
mit spezieller Schaltungstechnik unterdrückt werden
können. Der häufigste Effekt ist der Single-Event-Upset
(SEU), bei dem z.B. eine durch ein einzelnes Proton
hervorgerufene Ionisierung des Halbleitermaterials
zur fehlerhaften Änderung eines gespeicherten Bit-Zustandes
führt.
radiation-hardened chips
the objective of the project is to increase the resistance
of CMoS integrated circuits against functional
failures caused by the high-energy radiation using
predominantly circuit-design techniques, i.e. faulttolerant
(Ft) design techniques.
Many different types of radiation exist in space, in nuclear
reactors and in particle accelerators. electronic
components in these environments are subjected to
enhanced stress due to radiation (for example, beams
of energetic protons or heavy ions, alpha-, gamma- or
x-radiation, etc.).
long-term radiation effects in semiconductor materials
are usually reduced by the use of technological or
layout techniques, while short-term radiation effects
like the so-called Single-event-upset (Seu is one of
the most frequent radiation effects in semiconductor
materials) can also be minimized by the use of special
circuit-design techniques. Failures caused by Seu
are the change of a bit-state in a circuit sequential
element caused by a single particle (proton) induced
ionization of the semiconductor material.
Abb. 13: Für Strahlungstests ausgewähltes LEON3-FT-Chip.
Fig. 13: leon3 Ft chip selected for radiation tests.
A n n u A l R e p o R t 2 0 0 6
7

Für die Implementierung von FT-Schaltungstechniken
wurde ein 150 MHz LEON3-FT-Prozessorkern mit jeweils
2 kByte Befehls- und Daten-Cache, einem AMBA-Systembus
sowie daran angeschlossenen Systemkomponenten
ausgewählt. Zur Erweiterung der Testmöglichkeiten
wurde eine Scan-Chain sowie ein JTAG-Interface
eingebaut. In Abb. 13 ist das Blockschaltbild dargestellt
Im ersten Schritt wurden fehlertolerante Schaltungen
eingebaut, die sowohl sämtliche Flipflops als auch alle
internen Speicherblöcke vor SEUs schützen sollen. Die
Flipflops wurden mit dreifacher Redundanz und anschließender
Auswahlschaltung versehen. Die Speicher
erhielten zusätzliche Parity-Bits, die mit einer entsprechenden
Error-Detection-and-Correction (EDAC) Logik
verwaltet wurden. Wegen der etwas komplizierteren
Technik wurde das Registerfile in den SEU-Schutz noch
nicht mit einbezogen.
Die Strahlungstests fanden bei der ESA (Nordwijk, Niederlande)
statt und wurden über unsere Partnerfirma
Gaisler Research (Göteborg, Schweden) organisiert und
vorgenommen. Abb. 14 zeigt den Versuchsaufbau und
Abb. 15 den für die Strahlungstests geöffneten LEON3-
FT Chip.
Abb. 14: SEU-Test Vakuumkammer mit Zielsystem.
Fig. 14: Seu test vacuum chamber and target system.
8 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
As the fault-tolerant (Ft) test-chip for investigating
the short-term radiation effects (specially, the Seu),
a 150 MHz leon3-Ft processor core with instruction
and data caches (2 kByte each), AMBA system-bus
and attached system components has been selected.
For improved test purpose, a scan-chain and a JtAG
interface has been implemented. Fig. 13 shows the
block-diagram of the test-chip.
In the first step of building, fault-tolerant integrated
circuits were introduced to protect all flip-flops
and internal memory blocks against the Seus. In
this case, the flip-flops are protected by the use of
triple-module redundancy (tMR) and corresponding
voter circuitry. the memory blocks included additional
parity-bits that were controlled by corresponding
error Detection and Correction (eDAC) logic. In this
first step the register file is not protected against the
Seus due to complex correction technique and limited
core area.
the radiation test was organized and performed at
eSA (noordwijk, the netherlands) by our partner
company Gaisler Research (Göteborg, Sweden). Fig.
14 shows the test chamber and target system, while
Fig. 15 shows the de-lidded leon3-Ft chip.
Abb. 15: Geöffneter LEON3-FT Chip.
Fig. 15: De-lidded leon3-Ft chip.

a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Obwohl weder Technologie- noch Layout-Anpassungen
vorgenommen wurden und das Registerfile noch nicht
geschützt war, wurden in einem 3-stündigem Test
(Strahlungsquelle Cf-252) nur 281 SEUs registriert, von
denen 99% korrigiert wurden. Allerdings traten etwa
halbstündlich Latchup-Effekte auf, die jedoch nicht zur
Zerstörung des Chips führten.
In einem weiteren Zwischenschritt wurden kleinere Design-Änderungen
durchgeführt, u.a. wurden schnellere
statische Speicher (SRAMs) eingesetzt. Die anschließend
durchgeführten Strahlungstests führten zu ähnlichem
SEU-Verhalten (99,5% korrigiert), doch es traten
keine Latchup-Effekte mehr auf.
Diese sehr schnell und ohne aufwändige Technologieänderung
erreichten Ergebnisse werden in der dritten
Phase sowohl durch weitere schaltungstechnische Maßnahmen
als auch durch die Entwicklung einer speziellen
Bibliothek für strahlungsresistente Schaltungen
ergänzt. Das Ziel ist die Registrierung des IHP als zugelassener
Hersteller von strahlungsresistenten Schaltungen
und Baugruppen durch die ESA.
the test-chip was subjected to heavy-ion error injection
using Californium (Cf-252). the tests were carried
out for 3 hours and although no changes were made
neither in technology nor layout only 281 effective
Seus were reported and 99% of these were corrected.
one latch-up event was registered approximately every
30 minutes with the given ion flux.
In the meantime, an improved version of the testchip
with faster static memories (SRAMs) was implemented.
the results of the performed radiation tests
showed similar Seu behaviour with 99.5% of the Seus
corrected but no latch-up effect occurred during the
whole test.
these preliminary results (achieved in a short time
and without expensive technological changes) will
be improved in a third phase of the project using a
new circuit design technique as well as developing
a special radiation-hardened cell library. the main
goal is to qualify and register IHp for european Space
Agency (eSA) as an approved provider of radiationhardened
CMoS integrated circuits and systems.
A n n u A l R e p o R t 2 0 0 6

0 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Hochfrequenz-SiGe-MMICs für einen Umsetzer
und einen Lokaloszillator (SiMs)
Das Ziel des Projektes SiMs ist es, Lokaloszillatoren als
monolithische Mikrowellenbauteile (MMICs) zu entwerfen
und zu testen, jeweils eins für 18,3 GHz und für den
10-GHz-Bereich. Diese Frequenzen sind für die Verwendung
von Hardware im Weltraum üblich.
Die Projektkoordination erfolgt durch die Kayser-
Threde GmbH, München als Prime Contractor zur ESA als
Kunde, mit dem IHP, Frankfurt (Oder) und dem IMST,
Kamp-Lintfort als Subauftragnehmer.
Der Kommunikationsmarkt benötigt Breitband-Übertragungen,
High Definition Television (HDTV) und Interaktivität,
wobei HDTV die führende Rolle übernehmen
wird. Alles zusammen erfordert eine große Anzahl von
individuellen Übertragungskanälen, was zu einer großen
Anzahl von Auf- und Abwärtskonvertern führt. Diese
hohen Anforderungen können optimal durch hochintegrierte
SiGe MMICs bedient werden. Als Demonstrator
wird deshalb in diesem Projekt ein Lokaloszillator (LO)
Synthesizer entwickelt, da diese HF-Schaltung sehr gut
geeignet ist, die Vorteile der SiGe-Technologie nachzuweisen.
Die beiden kritischsten Bausteine des LO sind
der Voltage-Controlled-Oscillator (VCO) mit der zu erreichenden
Phasenrauschspezifikation, und der Fraktional-N
Teiler mit seinem starken Einfluss auf das Phasenrauschen
und die Spurs.
Es wurde ein differentieller Colpitts-Oszillator mit einem
speziellem Varaktor-Design entwickelt, um das Phasenrauschen
zu verbessern. Abb. 16 zeigt das Layout des VCO. Für
den 10-GHz-VCO wurden sehr gute Phasenrauschwerte mit
-119 dBc für 1 MHz Offset erreicht, und die Ausgangsleistung
erreicht 6 dBm. Für den 18-GHz-VCO wurde ein Phasenrauschen
von -112 dBc für 1 MHz Offset erhalten.
Das aktuelle Design ist ein Fraktional-N Frequenzsynthesizer,
für den sowohl die ausgezeichneten HF-Eigenschaften
der SiGe-Transistoren als auch das hohe
Integrationsniveau durch Verwendung von CMOS-Transistoren
genutzt werden. Der IC des Fractional-N Frequenzsynthesizers
enthält eine vollständige Phase-
Locked-Loop (PLL) zusammen mit einem digitalen
high Frequency siGe MMics for converter
and local oscillator (siMs)
the goal of the SiMs project is to design and test two
local oscillators as monolithic microwave integrated
circuits (MMICs), one for 18.3 GHz and one for 10 GHz
range. these frequencies are common for hardware
applications in space.
the project is conducted by Kayser-threde GmbH,
Munich, as the prime Contractor to the customer eSA,
with IHp, Frankfurt (oder) and IMSt, Kamp- lintfort as
sub-contractors.
the communication market demands broadband
transmission, high density television (HDtV) and interactivity,
whereby HDtV will become the leading
application. All applications require a high number
of individual channels, leading to a large number of
up- and down-converters. these high demands can be
served best with highly integrated SiGe MMICs. therefore,
in this project a local oscillator (lo) synthesizer
was developed and chosen as a demonstrator, because
this RF-element is particularly well suited to prove
the advantages of SiGe technology. the most critical
building blocks of the lo are the voltage controlled
oscillator (VCo) which is challenging in its phase noise
behavior, and the fractional-n divider with its large
influence on phase noise and spurs.
A differential Colpitts oscillator with special varactor-design
was developed to improve the phase noise
performance. the layout is presented in Fig.16. the
phase noise is very good for the 10 GHz VCo with
-119 dBc at 1 MHz offset, and the output power is
about 6 dBm. For the 18 GHz VCo a phase noise of
-112 dBc at 1 MHz offset is obtained.
the current design is a fractional-n frequency synthesizer
taking advantage of the excellent high-frequency
performance of SiGe as well as the integration
potential when using silicon CMoS processing. the
fractional-n frequency synthesizer IC contains the
entire phase-locked-loop (pll) along with the digital
fractional SDM (Sigma Delta Modulator) and a serial
processor interface (SpI). the pll has been designed

a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
fraktionalen SDM (Sigma Delta Modulator) und einem
Serial Processor Interface (SPI). Die PLL wurde als
Dual-Loop PLL entworfen, die eine Coarse und eine Fine
Loop besitzt, die mit den entsprechenden Varaktor-Eingängen
des VCO verbunden sind. Abb. 17 zeigt die Architektur
des Lokaloszillators als Blockschaltbild.
Abb. 16: Layout des 10-GHz-VCO mit Umschaltung von Varaktoren.
Fig. 16: layout of the 10 GHz VCo with varactor switching.
In der ersten Version besteht der LO aus zwei MMIC-Chips.
Für den HF-Chip des Lokaloszillators (VCO, Prescaler,
Dual Modulus Divider, und PFD) wurden vorwiegend die
Bipolarelemente der IHP SGB25VD SiGe- Technologie verwendet,
wobei für den anderen Chip der PLL (Reference
Divider, Main Divider und Fractional-N Controller) die
digitale Bibliothek der 0,25-µm-CMOS-Technologie des
IHP genutzt wurde. Diese Trennung berücksichtigte, dass
der Fractional-N Divider und der Phasen-Detektor voneinander
ausreichend isoliert werden müssen, um Spurs zu
vermeiden. Die gemessenen Phasenrauschwerte des LO
sind nahe der Spezifikation (< 10 dB Unterschied).
Obwohl das vorliegende Synthesizer-Design bereits gute
Werte liefert, wurden die beiden MMIC- Bausteine für
eine zweite LO-Version durch einige Änderungen verbessert.
Insbesondere ist zu nennen, dass der BiCMOS- und
der CMOS-Teil nun in einem Single-Chip-LO integriert
wurden, wobei die IHP SGB25VD Technologie verwendet
wurde. Außerdem wird nun eine höhere Referenzfrequenz
(100 MHz statt 33 MHz) verwendet, um mittels einer
größeren Loop-Bandwidth bessere Phasenrauschwerte
zu ermöglichen. Dies erforderte jedoch ein neues Design
für den programmierbaren Main Counter, da nun
die maximale Eingangsfrequenz statt 400 MHz größer
als 1 GHz ist. Der Programm- und Swallow-Counter wurden
deshalb in BiCMOS-ECL entworfen.
as a dual-loop pll featuring a coarse and a fine loop,
which connect to the coarse and fine tuning varactor
inputs of the VCo. the architecture of the local oscillator
is depicted as a block diagram in Fig. 17.
Abb. 17: Blockschaltbild des Lokaloszillators für 18,0-18,5 GHz.
Fig. 17: Block diagram of the 18.0 to 18.5 GHz local oscillator.
In the first version, the lo consists of two MMICs. the
high frequency section of the lo (VCo, prescaler, dual
modulus divider, and pFD) was realized using mainly
the bipolar components of the IHp SGB25VD SiGe
technology, the other part of the pll (reference divider,
main divider, and fractional n controller) has
been realized using the digital library of the 0.25 µm
IHp CMoS technology. this separation takes care of
the critical isolation between the fractional n divider
and the phase detector to avoid spurs. the measured
phase noise values of the lo are close to the specification
(< 10 dB difference).
Although the current synthesizer design is working
quite well, the MMICs are improved in several ways for
the second version of the lo. First of all, the BiCMoS
and the CMoS part are now integrated into a singlechip
lo using the IHp SGB25VD technology. Furthermore,
a higher reference frequency (100 MHz instead
of 33 MHz) is used in order to achieve better phase
noise values by increasing the loop bandwidth. this
however required a new design of the programmable
main counter as the maximum input frequency is now
> 1 GHz instead of 400 MHz. therefore, program and
swallow counter are designed in BiCMoS eCl logic.
A n n u A l R e p o R t 2 0 0 6

Rauscharme Frequenzsynthesizer für OFDM:
Von der Theorie zu Systemen
Integrierte Frequenzsynthesizer für drahtlose Transceiver
stellen eine große Herausforderung dar, weil ihre
Performance oft die Datenrate begrenzt. Der Abstimmbereich
muss relativ groß sein, um Schwankungen der
Bauelementeparameter zu kompensieren. Ein großer Abstimmbereich
erhöht wiederum das Rauschniveau. Des
Weiteren müssen Spulen und Kondensatoren normalerweise
integriert werden, um geringe Kosten zu erreichen.
Das begrenzt den Q-Faktor in spannungsgesteuerten Oszillatoren
und die Größe der Filterkondensatoren in Phase-locked
Loops (PLL). Infolge des relativ starken Phasenrauschens
kann die Bitfehlerrate in OFDM-basierten
drahtlosen Systemen stark beeinträchtigt sein.
In den letzten drei Jahren wurde viel Arbeit geleistet,
um den Einfluss von Phasenrauschen auf OFDM-
Systeme zu modellieren und zu optimieren. In die Beschreibung
von PLL- und VCO-Rauschen im Frequenzbereich
wurden weißes Rauschen, Funkelrauschen und
Substratrauschen einbezogen. Die Standardabweichung
des PLL-Phasenfehlers wurde auf Bauelemente- und
Systemparameter zurückgeführt. Mit Hilfe eines Zeitbereichsmodels
des PLL Phasenrauschens können realistische
Bitfehlerraten mit einem Systemsimulator
simuliert werden. Das verwendete stochastische Modell
basiert auf dem Wienerprozess und dem Ornstein-Uhlenbeck-Prozess,
welche aus der Theorie der optischen
Spektroskopie gut bekannt sind.
2 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
low-noise Frequency synthesizers for
oFdM: From theory to systems
Integrated frequency synthesizers for wireless transceivers
are challenging since their performance often
limits the achievable data rate. the tuning range
has to be relatively large to compensate variations in
the device parameters. A large tuning range, in turn,
increases the noise level. Furthermore, inductances
and capacitors must generally be integrated for low
cost. this limits the quality factor in the voltagecontrolled
oscillator (VCo) and the capacitor size in
the filters of the phase-locked loops (pll). As a result
of the relatively high phase noise, the bit-error rate
(BeR) in oFDM-based wireless systems may be strongly
affected.
During the past three years, a lot of work was carried
out in modeling and optimizing the effect of phase
noise on the performance of oFDM systems. White
noise, flicker noise and noise in the substrate were
included in the frequency-domain description of
pll and VCo noise. the rms phase error (jitter) of a
pll was attributed to device and system parameters.
A time-domain model for pll phase noise was used
to allow realistic bit-error-rate simulations with a
system simulator. the stochastic model used is based
on the Wiener process and the ornstein-uhlenbeck
process, which are well known from theory in optical
spectroscopy.

a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Auf der Basis unseres Phasenrauschmodells haben wir
Frequenzsynthesizer für das 60-GHz- und das 24-GHz-
Frequenzband entwickelt. Diese stellen Weltrekorde
bezüglich Geschwindigkeit und Phasenrauschen unter
den siliziumbasierten Synthesizern dar. Abb. 18 zeigt
ein Chip-Photo einer experimentellen PLL für drahtlose
Anwendungen im 60-GHz- und im 24-GHz-Band.
Das Phasenrauschen in einem integrierten 60-GHz-Transceiver
ist extrem wichtig in OFDM-Systemen, da die Bitfehlerrate
stark mit dem Phasenrauschen korreliert ist.
Systemparameter für ein 60-GHz-OFDM-System wurden
vorgeschlagen, die zum Teil auf den BER-Simulationen
beruhen (Abb. 19). Dabei wurde die Rauschfilterung
im Basisband mittels moderner Signalverarbeitung in
dem verwendeten Model berücksichtigt. Unser OFDM-
Systemkonzept wird gegenwärtig zur Aufnahme in einen
IEEE-Standard vorgeschlagen.
Abb. 18: Chipfoto eines integrierten Frequenzsynthesizers für
drahtlose Anwendungen im 60-GHz- und 24-GHz-Band.
Fig. 18: Chip photo of integrated frequency synthesizer for
wireless applications in the 60 GHz and the 24 GHz band.
Based on our phase noise model, frequency synthesizers
for the 60 GHz and the 24 GHz ISM bands have
been developed. they represent world records in
terms of operating frequency and phase noise for silicon-based
synthesizers. Fig. 18 shows a chip photo of
an experimental pll for wireless applications in the
60 GHz and the 24 GHz ISM band.
phase noise in a 60 GHz integrated transceiver is crucial
for oFDM systems, since the BeR is strongly correlated
with the pll phase noise. System parameters
for a 60 GHz oFDM system have been proposed, which
are partly based on BeR simulations as illustrated in
Fig. 19. Here we have included the baseband noise
filtering by state-of-the-art signal processing. our
oFDM system concept is currently actively proposed
for adoption as an Ieee standard.
Abb. 19: Berechnete Standardabweichung des Phasenfehlers der
PLL als Funktion der Loop-Bandbreite für drei OFDM-
Symbollängen.
Fig. 19: Calculated pll jitter as a function of the loop bandwidth
for three oFDM symbol lengths.
A n n u A l R e p o R t 2 0 0 6

Technologieplattform
SiGe-BiCMOS-Technologie für 77 /79 GHz
Auto-Radar (Projekt KOKON)
Im Verbundprojekt KOKON untersuchen deutsche Automobilhersteller
(DaimlerChrysler), Zulieferer, Mikroelektronikfirmen
(Infineon, Atmel) und Forschungsinstitute
gemeinsam die Einsatzfähigkeit von Schaltungen
in SiGe-Technologie für Radarsensoren bei 77 GHz bzw.
79 GHz. Am IHP werden dafür als Demonstratorschaltung
für einen Radarsignalgenerator spannungsgesteuerte
Oszillatoren (VCO) mit Leistungsverstärkern
entworfen und hergestellt.
Radarsysteme in modernen Autos erhöhen sowohl
die Sicherheit (Stop-and-go-Funktion, Kollisionswarnung),
als auch den Fahrkomfort (Parkhilfe). Leider
sind heutige Systeme entweder sehr teuer oder wie das
kürzlich eingeführte 24-GHz-System aus frequenz-regulatorischen
Gründen nur Interimslösungen (in der EU
zu ersetzen ab 2013). Eine sinnvolle Alternative sind
Schaltungen in SiGe-Technologie für die zwei Radarvarianten:
• 77 GHz Weitbereichsradar,
• 79 + / - 2 GHz Ultra-Weitband Nahbereichsradar.
Neben den zu erfüllenden technischen Spezifikationen
(möglichst hohe Ausgangsleistung bei niedrigem Phasenrauschen),
werden an die Schaltungen auch hohe Anforderungen
bezüglich Stabilität und Zuverlässigkeit bei
Temperaturen zwischen –40°C und +125°C gestellt.
A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
technology platform
siGe bicMos technology for 77 / 79 Ghz
automotive radar (KoKon project)
Within the BMBF funded project KoKon German automobile
manufacturers (DaimlerChrysler), suppliers,
microelectronics companies (Infineon, Atmel), and
research institutes jointly investigate the capability
of 77 / 79 GHz radar sensors in SiGe technology. At
IHp voltage controlled oscillators (VCo) with output
buffers are to be designed and manufactured as demonstrator
circuits for a radar signal generator.
Radar sensors in modern cars enhance safety (“stopand-go”
function, collision warning) and comfort
(parking aid). unfortunately, today’s systems are either
very expensive or like the 24 GHz system just interim
solutions (to be replaced in the eu from 2013).
promising alternative solutions are circuits in SiGe
technology for two radar variants:
• 77 GHz long range radar,
• 79 + / - 2 GHz short range ultra-wideband radar.
Besides meeting the technical specifications (high
output power but low phase noise) high demands are
also made on temperature stability and system reliability
between –40°C and +125°C.

Abb. 20: Kennlinien zweier VCO mit zwei unterschiedlichen
SiGe HBTs und Ausgangsleistungen bis +15 dBm.
Fig. 20: Characteristics of two VCos with two different
SiGe HBt types showing output power up to +15 dBm.
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Für das IHP ergeben sich innerhalb des Projekts folgende
Arbeitsschwerpunkte:
- Entwurf des Oszillators und Optimierung seiner
Kernparameter (anhand der Spezifikationen der
Automobilzulieferer),
- Optimierung der Temperaturstabilität (beispielsweise
möglichst geringe Änderung der Oszillatorschwingfrequenz),
- Untersuchung der Zuverlässigkeit von Halbleiterbauelementen
und der Oszillatorschaltung.
Dabei sollen die Ergebnisse mit denen einer alternativen
SiGe-Bipolartechnologie verglichen werden.
Letztere unterscheidet sich von der des IHP in den HBT
Spezifikationen (z.B. andere Grenzfrequenzen), dem
Backend (Al-Metallisierung (IHP) zu Kupfer-Metallisierung)
und den passiven Bauelementen (NMOS-Akkumulationsvaraktoren
(IHP) als variable Kapazitäten zu
reinen Bipolar-Varaktoren).
there are three priorities for the IHp within the project:
- design of the oscillator and optimization of its
core parameters (according to the specifications
of automotive suppliers),
- optimization of temperature stability (e.g. lowest
possible change of oscillator frequency),
- investigation of device and circuit reliability.
Additionally, these results will be compared with results
of an alternative SiGe bipolar process. this process
differs from the IHp technology by HBt specifications
(e.g. different transit frequencies), backend (Al
(IHp) to Cu metallization), and passive components
(nMoS accumulation (IHp) to bipolar varactors).
0.93 mm
0.85 mm
Abb. 21: Spannungsgesteuerter Oszillator mit zweistufigem
Leistungsverstärker für 77 / 79 GHz Radarsignalgeneratoren.
Fig. 21: Voltage controlled oscillator with two-stage output buffer
for 77 / 79 GHz radar signal generators.
A n n u A l R e p o R t 2 0 0 6

6 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Folgende Resultate konnten im Rahmen des Projektes
bisher erreicht werden:
Für die IHP SG25H1 Technologie wurden spannungsgesteuerte
Oszillatoren in differentieller Colpitts-Topologie
entworfen. Die bisherigen Schaltungen liefern mit
einem einstufigen Leistungsverstärker Ausgangsleistungen
je nach gewähltem SiGe-Transistortyp bis zu
+15 dBm [32 mW] (Abb. 20) und ein Phasenrauschen
bei 77 GHz von –90 dBc / Hz @ 1 MHz Offset. In Verbindung
mit einem zweistufigen Leistungsverstärker
(Abb. 21) werden bis zu +18 dBm [63 mW] erwartet.
Damit wird dann die Spezifikation von +16 dBm übertroffen.
Die Anforderungen der Automobilindustrie bezüglich
Temperaturstabilität und Zuverlässigkeit verlangen einen
großen Aussteuerbereich des VCO bzw. eine möglichst
geringe Änderung der Oszillatorfrequenz und
Ausgangsleistung bis 125°C. Der Oszillator in Abb. 20
zeigt einen Aussteuerbereich von 7 GHz. Die Drift
der Oszillatorfrequenz beträgt deutlich weniger als
-2 GHz / 100 K. Diese Werte können durch die Kombination
von SiGe HBT mit den NMOS-Varaktoren des
CMOS-Moduls erreicht werden; es müssen dafür keine
speziellen Bipolarvaraktoren entwickelt und integriert
werden.
Bei Zuverlässigkeitsuntersuchungen an den HBT bei
125°C und sehr hohen Strömen (bis zu 35 mA / µm 2 )
konnte nachgewiesen werden, dass die Hochfrequenzparameter
stabil bleiben. Das weist darauf hin, dass im
Vergleich zur Kupfer-Metallisierung auch die Aluminium-Metallisierung
diesen Anforderungen gewachsen
ist.
the following results were achieved within the project
until now.
Differential voltage controlled oscillators in Colpitts
topology were designed for IHp’s SG25H1 technology.
present differential circuits with single-stage output
buffers deliver output powers up to +15 dBm [32 mW]
(Fig. 20) – depending on the transistor type - and
phase noise levels at 77 GHz of about –90 dBc / Hz
@ 1 MHz offset. For a VCo with a double stage buffer
(Fig. 21) up to +18 dBm [63 mW] are expected. this is
well above the specification of +16 dBm.
the automotive industry‘s demand for sufficient temperature
stability and reliability requires a large tuning
range combined with small changes of oscillator
frequency and output power up to 125°C. the oscillator
in Fig. 20 shows a tuning range of 7 GHz and additionally
an oscillator frequency drift of significantly
less than –2 GHz per 100 K has been measured. these
results were obtained by the combination of SiGe HBt
and the nMoS varactors of the CMoS module; no special
bipolar varactors had to be introduced for this.
With reliability stress tests of the HBts at 125°C and
very high current densities (up to 35 mA / µm 2 ) it was
shown that the high frequency parameters remained
unchanged.
this indicates that like the copper metallization the
aluminium backend copes with these standards.

130-nm-BiCMOS-Technologie
Ziel des Projektes ist die Entwicklung einer Technologie
für integrierte Kommunikationssysteme auf einem Siliziumchip
(System-on-Chip) mit höchsten Datenraten und
Übertragungsfrequenzen. Die 130-nm-BiCMOS-Technologie
wird Basis für die zukünftige technologische Forschung
und für die Untersuchung neuer Schaltungs- und
Systemkonzepte sein. Darüber hinaus wird die Technologie
Forschungs- und Entwicklungspartnern über den
Prototyping-Service des IHP zur Verfügung gestellt.
SiGe-BiCMOS-Technologien der nächsten Generation
stellen durch die Integration von HF-Schaltungen im
mm-Wellenbereich mit schnellen Digitalschaltungen
hoher Packungsdichte einen Schlüssel für die kostengünstige
Realisierung integrierter Kommunikationssysteme
mit großer Bandbreite dar. Durch HBTs mit
Grenzfrequenzen oberhalb von 200 GHz werden Anwendungen
wie drahtlose Kommunikation im 60-GHz-Band,
lichtleiterbasierte Kommunikationssysteme mit Datenraten
oberhalb 40 Gbps und automobile Radarsysteme
bei 77 GHz ermöglicht.
Abb. 22: HF-Charakteristik von high-performance HBTs.
Fig. 22: RF characteristics of high-performance HBts.
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
130 nm bicMos technology
the objective of the project is the development of a
technology suitable for system-on-a-chip (SoC) solutions
for wireless and broadband communication at
highest data rates and highest transmission frequencies.
the 130 nm BiCMoS process will be the platform
for future technology research and for the investigation
of new circuit and system concepts. Moreover,
the technology will be available to research and development
partners via the IHp prototyping service.
the integration of mm-wave RF circuits with highspeed,
high-density digital blocks in next generation
SiGe BiCMoS technologies is a key for cost-effective
realizations of high-bandwidth communication systems.
HBts with cut-off frequencies above 200 GHz
facilitate new applications such as wireless links in
the 60 GHz band, fiber optics communication systems
with data rates above 40 Gbps, and automotive
radar at 77 GHz.
Abb. 23: Transferkennlinien von 130 nm NMOS- und
PMOS-Transistoren.
Fig. 23: Transfer characteristics of 130 nm NMOS and
pMoS transistors.
A n n u A l R e p o R t 2 0 0 6
7

8 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Im Jahr 2006 wurde erstmals der vollständige technologische
Ablauf des 130-nm-BiCMOS-Prozesses realisiert.
In der Technologie werden zwei Typen von SiGe-HBTs,
die für hohe Frequenzen bzw. hohe Durchbruchspannungen
optimiert wurden, sowie CMOS-Transistoren mit
zwei Gateoxiddicken für Betriebsspannungen von 1,2 V
und 3,3 V bereitgestellt.
Die HBTs zeichnen sich gegenüber vorangegangenen
Technologiegenerationen u.a. durch selbstjustierte Basis-
und Emittergebiete und durch eine Reduzierung der
Emitterweite auf 120 nm aus. Für die high-performance
HBTs wurden Grenzfrequenzen f T und f max im Bereich von
250-300 GHz realisiert (Abb. 22). Der CMOS-Prozess wurde
für Anwendungen mit geringem Leistungsverbrauch
optimiert. Die 1,2-V-NMOS- und PMOS-Transistoren zeigen
Leckströme von 50 pA / µm und Betriebsströme von
440 bzw. 200 µA / µm (Abb. 23).
Eine Aluminium-Metallisierung mit bis zu sieben Metallebenen
wurde entwickelt. Darunter sind zwei für
HF-Anwendungen optimierte 2 µm bzw. 3 µm dicke
Metallebenen, die die Integration von passiven Komponenten
wie Spulen, Transformatoren und Übertragungsleitungen
hoher Güte ermöglichen.
Die erste Version des Designkit für die 130-nm-BiCMOS-
Technologie wurde 2006 erarbeitet und wird z.Z. für die
Entwicklung von Schaltungen für die Bewertung der
HF-Eigenschaften der Technologie und für die Erstellung
von Bibliotheken für digitale CMOS-Schaltungen
eingesetzt. Die Nutzbarkeit der Technologie für hochintegrierte
Schaltungen wurde durch erste funktionsfähige
4-Mbit-SRAM-Chips demonstriert (Abb. 24).
In 2006, the full-flow 130 nm BiCMoS process was
realized for the first time. the technology provides
two types of SiGe HBts optimized for high frequencies
and high breakdown voltages, respectively, and CMoS
transistors with two gate oxide thicknesses for operating
voltages of 1.2 V and 3.3 V.
new features of the HBt devices compared to previous
generations are self-aligned base and emitter regions
and minimal emitter widths of 120 nm. Cut-off
frequencies f t and maximum oscillation frequencies
f max in the 250 to 300 GHz range were realized for
the high-performance HBts (Fig. 22). the CMoS process
was optimized for low-power applications. the
1.2 V nMoS and pMoS transistors exhibit off-currents
of 50 pA / µm and on-currents of 440 µA / µm and
200 µA / µm, respectively (Fig. 23).
An aluminum back-end-of-line with up to seven metal
layers was developed. these include two metal layers
with thicknesses of 2 µm and 3 µm facilitating the
integration of passive components such as inductors,
transformers, and transmission lines with high quality
factors.
A first revision of the design kit for the 130 nm BiCMoS
technology was developed in 2006. It is now used
for designing benchmark circuits for the evaluation
of the RF performance of the technology and digital
CMoS libraries. the capability of the technology for
VlSI circuit fabrication was demonstrated by first fully-functional
4 Mbit SRAM chips (Fig. 24).
Abb. 24: Aufnahme einer SRAM-Zelle (Raster-TEM).
Fig. 24: Scanning transmission electron microscope
image of an SRAM cell.

Kostengünstiger SiGe CBiCMOS Prozess
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Projektziel war es zu prüfen, ob ein kostengünstiger
CBiCMOS-Prozeß realisierbar ist, der mit minimaler Anzahl
an bipolaren Masken- und Prozessschritten ausreichend
gute npn- und pnp-Transistorparameter für ein
breites Spektrum von Anwendungen liefert.
Eine komplementäre BiCMOS-(CBiCMOS-)Technologie,
die npn- und pnp-Transistoren mit ähnlichen Parametern
liefert, ist sehr vorteilhaft und innovativ für eine Vielzahl
analoger Schaltungen. Der ideale CBiCMOS-Prozeß
sollte auf bipolarer Seite npn- und pnp-Transistoren mit
besten HF-Parametern liefern, gleichzeitig aber auch
Transistoren mit höherer Durchbruchsspannung, und
das bei Kosten, die möglichst nicht über denen eines
BiCMOS- oder sogar RF-CMOS-Prozesses liegen. IHP’s
erste CBiCMOS-Technologie (SG25H2) bietet ein npn-f T
von 170 GHz und ein pnp-f T von 90 GHz, die beste jemals
erreichte CBiCMOS pnp-Grenzfrequenz. Allerdings wurde
diese Technologie vor allem hinsichtlich bester HF-
Parameter optimiert, ohne allzu große Rücksicht auf die
Prozesskosten. Im Gegensatz dazu bestand die große
Herausforderung dieses Projektes darin, attraktive HF-
Parameter mit einem Prozessfluß zu erhalten, der mit
deutlich weniger bipolaren Masken- und Prozessschritten,
verglichen mit dem Stand der Technik, auskommt.
Um einen einfachen CBiCMOS-Prozeß zu erhalten, wurde
der Prozessablauf des 1-Masken Bipolar-Moduls der
IHP npn-BiCMOS-Technologie SGB25VD für die pnp-Herstellung
adaptiert. Außerdem wurde ein zweiter Isolationsgraben
eingeführt, der eine geringere Tiefe aufweist
als der des Basisprozesses. Der flachere Graben
trennt das aktive Transistorgebiet vom Kontaktgebiet
und erlaubt uns, gleichzeitig niedrige Kollektorwiderstände
und Basis-Kollektor-Kapazitäten mit einer einfachen,
Epitaxie-freien Kollektorstruktur zu erreichen
(Abb. 25).
cost-optimized siGe cbicMos process
the objective of this project was to investigate the
feasibility of a cost-optimized SiGe CBiCMoS process,
which provides ample npn and pnp transistor
performance for a wide range of applications, while
utilizing a minimum of dedicated bipolar mask and
processing steps.
A complementary BiCMoS (CBiCMoS) technology containing
both npn and pnp devices with matched performance
offers compelling advantages in many types
of analog circuits. An ideal CBiCMoS process should
provide both npn and pnp devices with best RF performance
on the bipolar side, combined with higher
voltage transistors, but preferably not above the cost
of a BiCMoS or even an RF-CMoS process. IHp`s first
SiGe CBiCMoS technology (SG25H2) combines a 170
GHz f t npn device with a 90 GHz f t pnp transistor demonstrating
a level of pnp RF performance not seen
before. For this unique technology, however, performance
was clearly the priority, while cost was not in
the main focus. the big challenge of this particular
CBiCMoS project was to demonstrate attractive npn
and pnp device performance in a process flow with
a much lower number of dedicated bipolar mask and
processing steps compared to the state-of-the-art.
to obtain a low-cost CBiCMoS process, we adapted the
process sequence applied in the 1-mask, npn-only bipolar
module of IHp’s low-cost npn-BiCMoS process
SGB25VD also for pnp fabrication. Moreover, we introduced
a second shallow trench (SStR) which has
a lower depth compared to the trench of the process
core. the SStR separates the active bipolar transistor
regions from the collector contact regions and allows
us to simultaneously reach low values of collector resistance
(RC) and base-collector capacitance (CBC)
with a simple, epi-free collector structure (Fig. 25).
A n n u A l R e p o R t 2 0 0 6

Abb. 25: REM Querschnittsbilder eines pnp SiGe HBT zur Illustration der benutzten zwei Typen von Isolationsgräben.
Fig. 25: SeM X-sections of a pnp SiGe HBt illustrating the two trench types used.
Folgende Hauptergebnisse des Projektes wurden erreicht:
1) Unter Hinzufügung von nur drei Maskenschritten
zur unterliegenden HF-CMOS-Linie ist ein CBiCMOS-
Prozeß realisierbar, der 3 Typen von npn-Transistoren
(120 GHz f T / 2,1 V BV CEO , 63 GHz f T / 3,5 V BV CEO und
40 GHz f T / 5 V BV CEO ) zusammen mit einem 32 GHz
f T , 35 GHz f max , 4,2 V pnp SiGe HBT liefert.
2) Mit zwei weiteren Implant-Masken, d.h. mit insgesamt
nur 5 Bipolar-Masken können zusätzlich (npn-
Fall) oder alternativ (pnp) zu den Transistoren des
3-Masken-Moduls ein 150 GHz f T , 2,2 V npn HBT und
entweder ein 43 GHz f T , 65 GHz f max , 4,2 V pnp HBT
oder ein 38 GHz f T , 70 GHz f max , 5,8 V pnp HBT hergestellt
werden. Abb. 26 zeigt f T und f max dieser pnp-
Transistoren in Abhängigkeit vom Kollektorstrom.
Abb. 27 vergleicht die pnp HF-Parameter des neuen Prozesses
mit den Daten anderer CBiCMOS-Technologien.
Tabelle 2 bezieht zusätzlich noch die npn HF-Parameter
und die Anzahl der Bipolarmasken als Maß für die Prozesskomplexität
in den Vergleich ein. Es wird deutlich,
dass der neue Prozess hinsichtlich der Kombination von
Prozesskomplexität / -Kosten und erreichbarer HF-Parameter
der komplementären Bipolartransistoren derzeit
unerreicht ist.
0 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
the primary results of this project can be summarized
as follows:
1) With a minimum of only three bipolar mask
adders, the new CBiCMoS process provides 3 types
of npn SiGe devices featuring 120 GHz f t
(at 2.1 V BV Ceo ), 63 GHz f t (3.5 V BV Ceo ), and
40 GHz f t (5 V BV Ceo ), together with a 32 GHz
f t , 35 GHz f max , 4.2 V pnp SiGe HBt.
2) With two additional implant masks, i.e. with only
5 bipolar masks in total, a 150 GHz f t , 2.2 V npn
HBt and either a 43 GHz f t , 65 GHz f max , 4.2 V pnp
or a 38 GHz f t , 70 GHz f max , 5.8 V pnp device can be
fabricated additionally (in the npn case) or alternatively
(pnp case) to the devices of the 3-mask
module. Fig. 26 shows f t and f max vs collector current
for these pnp devices.
Fig. 27 compares the pnp RF data of the new process
with data of other CBiCMoS technologies. table
2 additionally includes npn parameters and the no.
of dedicated bipolar masks as a measure of process
complexity and thus cost. It is obvious that the new
process provides by far today’s best combination of
complexity / cost and RF performance of the complementary
bipolar devices in a fully featured CBiCMoS
process.

parameter IHp (this project) IHp tI IBM Jazz Semi
(f t / f max in GHz, BV Ceo in V) SG25H2 (BCtM03) (SiRF07) (Homepage)
High-BV npn-f / f / BV t max Ceo 40 / 80 / 5 + 63 / 95 / 3.5 - 27 / 90 / 6 29 / 51 / 6 + 38 / 150 / 6 +
45 / 73 / 4.5 78 / 190 / 3.5
low-BV npn-f / f / BV 120 / 110 / 2.1 150 / 160 / 2.2 170/170/1.9 - t max Ceo 60 / 85 / 3.3 155/200/2.2
pnp-f / f / BV t max Ceo 32 / 35 / 4.4 38 / 70 / 5.8 or 90/120/2.5 27 / 60 / 6 28 / 26 / 6 17 / f not max
43 / 65 / 4.2 available / 7
Bipo-mask no. over RF-CMoS 3 5 10 see* >8** >8**
* not simply formed by an integration of a bipolar module in an RF-CMoS baseline
** Mask no. by a rough estimation only
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Abb. 26: f T und f max in Abhängigkeit vom Kollektorstrom für die
pnp-Transistoren, die alternativ mit dem komplementären
5-Masken Bipolar-Modul herstellbar sind.
Fig. 26: f t and f max vs. collector current for pnp transistors which
can be fabricated alternatively in the 5-mask,
complementary bipolar module.
Abb. 27: f T und f max in Abhängigkeit von BV CEO für pnp-Transistoren
verschiedener CBiCMOS-Technologien.
Fig. 27: f t and f max vs. BV Ceo for pnp transistors from different
CBiCMoS technologies.
(1 tI data from BCtM03, 2 IBM data from SiRF07,
3 Jazz data from homepage)
Tabelle 2: Vergleich verschiedener CBiCMOS-Technologien (bzw. npn-BiCMOS-Technologien mit pnp-Option).
table 2: Comparison of CBiCMoS technologies (and npn BiCMoS technologies with a pnp option, respectively).
A n n u A l R e p o R t 2 0 0 6

Zuverlässigkeit von HBTs
Ziel des Projektes ist es, das Degradationsverhalten von
SiGe Heterobipolartransitoren (HBT) in Abhängigkeit
von Strom, Spannung und Temperatur zu untersuchen,
um Maximalparameter festzulegen, die ein ausreichend
gutes Funktionieren über 10 Jahre garantieren.
Die Entwicklung unserer BiCMOS-Technologien findet
durch den Nachweis ihrer Zuverlässigkeit gemäß internationaler
Standards ihren Abschluss. Dabei gibt
es Forschungsbedarf insbesondere zur Zuverlässigkeit
von Höchstgeschwindigkeits-SiGe-HBTs, da auf diesem
Gebiet noch relativ wenig bekannt und kaum etwas publiziert
ist. Die grundlegende Idee ist es dabei, bei Einhaltung
definierter Designregeln eine Lebensdauer von
10 Jahren bei weniger als 0,01 % Ausfällen zu garantieren.
Neben verschiedenen Stresstests mit komplexen
Schaltkreisen, Untersuchungen zur Elektromigration,
zur Oxidstabilität, zur Heißladungsträgerinjektion u.
a., ist die Bestimmung der Zuverlässigkeit von HBT-
Strukturen von zentraler Bedeutung.
Mit der SG25H1-Technologie präparierte npn200-Transistoren
wurden in unserem Intrinsic-Testsystem MIRA
von QualiTau bei Temperaturen von 60 °C, 125 °C, und
150 °C mit Emitterströmen (I E ) von 0,7 bis 10 mA bei
Kollektor-Basis-Spannungen (V CB ) zwischen 0 und 3 V
gestresst. In definierten Intervallen wurden Gummel-
Plots bei Stresstemperatur und V CB = 0 V mit V BE zwischen
0,2 und 1,0 V gemessen (siehe Abb. 28). Die
Degradation der Stromverstärkung Beta = I C / I B wird bei
verschiedenen Werten von V BE betrachtet, wobei 10 %
Degradation als Fehlerkriterium definiert wird.
2 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
reliability of hbts
The objective of the project is to characterize the degradation
behavior of SiGe heterobipolar transistor
(HBT) structures as a function of current, voltage, and
temperature to define maximum allowed parameters to
guarantee 10 years of sufficient operation.
The final point in the development of our BiCMOS technologies
is the proof of their reliability according to
international standards. This requires the basic understanding
of different degradation mechanisms. There is
a strong research demand especially for the reliability
of high speed SiGe HBTs, since there is still little known
on this field and nearly nothing has been published so
far. The general idea of technology qualification is to
guarantee a lifetime of ten years with less than 0.01 %
failures under defined design rules. Besides different
stress tests of complex circuits, tests for electromigration,
gate oxide integrity, hot carrier injection and
others, it is of fundamental importance to characterize
the reliability of HBT structures.
For this purpose, we stressed npn200 transistors pre-
pared with the SG25H1 technology at temperatures of
60 °C, 125 °C, and 150 °C with emitter currents (I E ) between
0.7 and 10 mA and collector base voltages (V CB )
between 0 and 3 V in our intrinsic reliability test system
MIRA from QualiTau. Gummel plots were measured after
defined stress sequences at stress temperature with
V CB = 0 V in a V BE range from 0.2 to 1.0 V (see Fig. 28).
Degradation parameter is the current gain Beta = I C / I B
at a given V BE value. The typical failure criterion is a 10 %
degradation of Beta.

Abb. 28: Gummel-Plots (links), Beta vs. V BE (mitte) und über
9 Transistoren gemittelte relative Beta-Degradation
vs. Stresszeit (rechts) unter Stressbedingungen
V CB = 2,0 V , I E = 2,5 mA und T = 60 °C.
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Die in Abb. 28 gezeigte Zeitabhängigkeit der Degradation
von Beta ist so nur für schwachen und mittleren
Stress typisch. Bei höheren Emitterströmen oder V CB -
Werten beobachtet man eine Sättigung der Degradation
und anschließende Abnahme mit zunehmender
Stresszeit. Dies ist die Folge zweier konkurrierender
Mechanismen. Für die Sättigung der Beta-Degradation
oder gar die Umkehr des Degradationstrends sind
Auf- und Entladungsprozesse im Isolationsmaterial
zwischen Emitter und Basis, hervorgerufen durch heiße
Ladungsträger, verantwortlich.
Als Beispiel für den Einfluss von V CB auf das Degradationsverhalten
zeigt Abb. 29 für verschiedene V BE die
mittlere Lebensdauer für eine 10 %-ige Beta-Degradation
bei I E = 2,5 mA und T = 60 °C. Die Degradation ist
deutlich stärker bei niedrigen V BE -Werten und nimmt mit
V CB zu. Die auf eine Lebensdauer von 10 Jahren extrapolierten
Linien für V BE = 0,6 – 0,95 V in der Darstellung
der Lebensdauer vs. V CB schneiden sich alle bei etwa
V CB = 1,2 V. Das bedeutet, dass unabhängig von V BE unter
diesen Stressbedingungen für V CB < 1,2 V eine Lebensdauer
von 10 Jahren garantiert werden kann.
Fig. 28: Gummel plots (left), Beta vs. V Be (middle) and relative
Beta degradation (averaged over nine devices) vs. stress
time (right) under stress conditions
V CB = 2.0 V, I e = 2.5 mA, and t = 60 °C.
the time dependence of Beta degradation shown in
Fig. 28 is typical for weak and medium stress conditions
only. At higher emitter currents or higher
V CB values, we observe that the degradation reaches
a maximum and starts to decrease with increasing
stress time. this is caused by the competition of two
different mechanisms. Charging and discharging processes
in the isolation material between emitter and
base caused by hot carriers are responsible for the saturation
and even the reversal of Beta degradation.
As an example for the role of V CB , Fig. 29 shows for different
V Be the mean time to failure (mean lifetime) for
10 % Beta degradation at I e = 2.5 mA and t = 60 °C.
the degradation is significantly stronger at low V Be
values, and it increases with V CB . the lines extrapolated
for V Be = 0.60 - 0.95 to a lifetime of 10 years in
the MttF vs. V CB plot all cross at about V CB = 1.2 V. this
means that independent of the V Be value it is possible
to guarantee a lifetime of ten years for V CB < 1.2 V
under these stress conditions.
A n n u A l R e p o R t 2 0 0 6

Abb. 29: Mittlere Lebensdauer (MTTF) für 10 % Beta-Degradation
vs. V BE für unterschiedliche V CB -Werte (links) und vs.
V CB für verschiedene V BE -Werte (rechts) nach Stress
mit I E = 2,5 mA bei T = 60 °C.
A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Das Degradationsverhalten im gesamten V CB – V BE – I E
– T-Parameterraum ist sehr komplex. So ist es z.B. möglich,
dass abhängig von den anderen Parametern die
Degradation von Beta mit der Temperatur zu- oder abnehmen
kann. Das Verstehen und Modellieren dieses
komplexen Verhaltens ist Gegenstand weiterer Untersuchungen.
the degradation behavior in the whole V CB – V Be – I e
– t parameter space is rather complex. thus it is for
example possible that the degradation of Beta increases
or decreases with temperature depending on the
other parameters. the understanding and modeling
of this complex behavior is subject of further investigation.
Fig. 29: Mean time to failure (MttF) of 10 % Beta degradation
vs. V Be for different V CB values (left) and vs. V CB for
different V Be values (right) at I e = 2.5 mA and t = 60 °C
stress.

Materialien für die Mikro- und Nanoelektronik
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Modellierung der quadratischen Spannungsabhängigkeit
von Hoch-k-MIM-Kondensatoren
Die Einführung von Hoch-k-Dielektrika in Metall-Isolator-Metall-Kondensatoren
(MIM) zur Flächenreduzierung
erregt viel Aufmerksamkeit. Das Erreichen einer
ausreichenden Kapazitäts-Spannungs-Linearität in
Hoch-k-MIM-Kondensatoren ist immer noch eine Heraus-
forderung.
Die Ursache des nichtlinearen Kapazitäts-Spannungs-
Verhaltens C(V) von MIM-Kondensatoren mit Al 2 O 3 -,
Y 2 O 3 -, HfO 2 - oder Pr 2 Ti 2 O 7 -Dielektrika wurde untersucht.
Basierend auf dem elektrooptischen Kerr-Effekt, wurde
ein physikalischer Ausdruck für den quadratischen
Spannungskoeffizienten α abgeleitet.
Materials for Micro- and nanoelectronics
Modeling the Quadratic Voltage dependence
of high-k MiM capacitors
the introduction of high-k dielectrics into Metal-
Insulator-Metal (MIM) capacitors to reduce the area
attracts much attention. nevertheless, it is still a
challenge to achieve sufficient capacitance voltage
linearity in high-k MIM capacitors.
the origin of the nonlinear capacitance-voltage
behavior of MIM capacitors with Al 2 o 3 , Y 2 o 3 , Hfo 2 or
pr 2 ti 2 o 7 dielectrics is investigated. Based on the electro-optical
Kerr effect, a physical expression for the
quadratic voltage coefficient α is derived.
Abb. 30: C(V)-Kurven von MIM Kondensatoren verschiedener
Dielekrika mit 20 – 30 nm Schichtdicke.
Die durchgezogenen Linien repräsentieren das Modell.
Fig. 30: C(V) curves of MIM capacitors for different dielectrics with
thicknesses of 20 – 30 nm. the solid lines represent the model.
A n n u A l R e p o R t 2 0 0 6

6 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Die gemessenen C(V)-Kurven ausgewählter Hoch-k-Materialien
und die entsprechenden Anpassungen, repräsentiert
durch die Linien, sind in Abb. 30 dargestellt.
Mit Hilfe der erhaltenen intrinsischen Parameter ist es
mittels des Modells möglich, die kritische Schichtdicke
für jedes Hoch-k-Material zu bestimmen, bei der α kleiner
als der erforderliche Wert von 100 ppm / V 2 bleibt.
Mit Kenntnis der kritischen Schichtdicke ist es ebenfalls
möglich, die maximal mögliche Kapazitätsdichte
für die Hoch-k-Materialien zu berechnen. In Abb. 31 ist
dargestellt, wie die kritische Kapazitätsdichte mit der
Dielektrizitätskonstante wächst. Kapazitätsdichten von
3-4 fF / µm 2 können durch den Gebrauch von Hoch-k-
Materialien anstelle von SiO 2 erreicht werden, und die
Kondensatorfläche kann um einen Faktor 2 reduziert
werden.
the measured C(V) curves of selected high-k dielectrics
and the corresponding fits, represented by the
lines, are shown in Fig. 30. By using the determined
intrinsic parameters, the model is capable to provide
the critical thickness of the high-k material. thereby,
α is fixed to the required value of 100 ppm / V 2 . With
the knowledge of the critical thickness, it is also possible
to calculate the maximum capacitance density
with α-values smaller than 100 ppm / V 2 . As shown
in Fig. 31, the critical capacitance density increases
with the dielectric constant. Capacitance densities of
3-4 fF / µm 2 can be achieved by using high-k materials
instead of Sio 2 . therefore, the capacitor area can
be reduced by a factor of 2.
Abb. 31: Berechnete kritische Kapazitätsdichten als Funktion
der Dielektrizitätskonstanten bei α = 100 ppm / V 2 .
Fig. 31: Calculated critical capacitance density as a function
of k-values with α = 100 ppm / V 2 .
[1] J. e. Babcock et al., Ieee eDl 22, 230-233, (2001).
[2] S.-Y. Yun et al., Apl 82 2874-2876, (2003).

Hoch-k-PrAlO 3 auf TiN-bedecktem Si(001)
und Grenzflächenreaktion
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
In der Arbeit wurden PrAlO 3 / TiN auf Si(001) und der
Einfluss von Defekten auf die Leckstromdichte in diesem
Material für die Anwendung in der nächsten Generation
von Halbleiterbauelementen untersucht.
Die fortschreitende Verkleinerung mikroelektronischer
Bauelemente erfordert Isolatoren mit höherer dielektrischer
Konstante k. Der Austausch von SiO 2 durch ein
alternatives Hoch-k-Material erzeugt eine Reihe von Defekten
an den Grenzflächen, welche die dielektrischen
Schichteigenschaften beeinflussen. Das Verstehen der
Thermodynamik und Kinetik des Schichtwachstums
während der Herstellung des Hoch-k-Stapels ist wesentlich,
um die Grenzschichten atomar zu kontrollieren
und die Zahl der Defekte zu minimieren.
Diese Arbeit ist darauf gerichtet, den Einbau von Verunreinigungen
in Hoch-k-Schichten zu untersuchen und
zu vermeiden.
Die Wechselwirkung zwischen dem Substrat und der
Schicht kann leicht zur Bildung schädlicher Defekte
führen, manchmal mit makroskopischem Charakter.
Diese Tendenz kann durch Oberflächenkontamination
und / oder Stöchiometrieschwankungen unterstützt
werden. Wir haben mikroskopische Eigenschaften
(elektrische Aktivität und Formationsenergie) von
Punktdefekten im PrAlO 3 -Dielektrikum untersucht. Es
wurde gefunden, dass die Kontamination durch Sauerstoff
und TiO aus der Schicht zwischen PrAlO 3 und TiN
(Abb. 32) und / oder Wasser (PrAlO 3 ist schwach hygroskopisch)
(Abb. 33) ein Problem im Praseodymaluminat
darstellen können.
Die Zugabe von Al 2 O 3 stabilisiert die Schicht in ihrer
amorphen Struktur und scheint das multivalente Verhalten
von Pr zu unterdrücken.
high-k pralo 3 on tin covered si(001) and
interfacial reaction
the work was done to investigate prAlo 3 / tin on
Si(001) with regard to the influence of defects on the
leakage current density in next generation semiconductor
devices.
the proceeding scaling of microelectronic devices
requires insulator layers with a higher dielectric
constant k. the substitution of Sio 2 by an alternative
high-k material creates a series of defects at the
interfaces which influence the dielectric properties
of the film. understanding the thermodynamics and
kinetics of film growth during fabrication of high-k
gate stacks is vital to establish atomic level control
of interfacial layers and to minimize the number of
defects.
the paper is directed to explore and avoid the incorporation
of impurities into the dielectric high-k layer.
the interaction between the substrate and the film
may readily lead to the formation of detrimental
defects: point defects as well as extended defects,
sometimes of true macroscopic character. this tendency
may be enhanced by surface contamination
and / or local variations in stoichiometry. We analyzed
the microscopic properties (electrical activity
and formation energies) of major point defects in
prAlo 3 dielectrics. We found that contamination with
oxygen and tio coming from tiox interlayer between
prAlo 3 and tin (Fig. 32) or / and water (hygroscopicity
of prAlo 3 ) (Fig. 33) is a problem in the case of
pr 2 o 3 / Al 2 o 3 alloying.
the addition of Al 2 o 3 to pr 2 o 3 stabilizes the film in its
amorphous structure and seems to suppress the multivalent
behavior of pr.
A n n u A l R e p o R t 2 0 0 6
7

Der Leckstrom ist nach dem Tempern über 700°C unabhängig
von der Ausheizart (z.B.: schnelles Heizen
[RTA] oder bei konventionellem Ofenheizen) signifikant
erhöht. Wir argumentieren, dass die Wechselwirkung
zwischen der PrAlO 3 Schicht und dem TiN Substrat
(Abb. 32) so genannte „Hot Spots“ verursacht, welche
mit der Anwesenheit von TiAl+ Donatoren verbunden
sind. Wir erwarten, dass durch das Ausheizen über 700 °C
in der Umgebung der Zwischenschicht zu TiN Donatoren
in höherer Konzentration erzeugt werden und dabei
vorzugsweise in der Region in der ein Überschuss von
Pr-Oxiden und eine hohe Konzentration von Volumendefekten
vorliegt.
Abb. 32: Schichtstruktur von PrAlO 3 / TiN auf Si(001) TiO 2 / TiNO x
bzw. Hydroxid an den Grenzen von PrAlO 3 .
Fig. 32: layered structure of prAlo 3 / tin on Si(001).
tio 2 / tino x and hydroxide flank the prAlo 3 layer.
8 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
the leakage current is significantly increased if the
anneal takes place at temperatures higher than 700 °C,
independent of the annealing method (i.e. by rapid
thermal anneal or by using a conventional oven). We
argue that the interaction between prAlo 3 film and
the tin substrate (Fig. 32) causes the formation of
hot spots which are possibly associated with the presence
of tiAl+ donors. We expect that annealing at
temperatures above 700 °C produces these donors at
a high concentration in the vicinity of the interface
with tin and preferably in regions where there is an
excess of pr oxide and a high concentration of open
volume defects.
Praseodymium Oxygen / Sauerstoff
Abb. 33: OH-Gruppen, eingebaut in einer Pr 2 O 3 -Matrix:
auf Zwischengitterplätzen als (OH) I - und im Gitter
als (OH) O + .
Fig. 33: oH groups trapped in pr 2 o 3 matrix:
interstitial (oH) I - and substitutional (oH) o + .

Halbleiter/Isolator/Halbleiter Heterostrukturen
hoher Qualität: Grenzflächenund
Gitteranpassungsansätze
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Ziel des Projektes ist die globale bzw. lokale Integration
neuer Materialien in die Silizium-Technologieplattform,
um durch die Verfügbarkeit alternativer Halbleiterschichten
geeigneter Qualität die Funktionalität
und Leistung der Si-basierten Schaltkreistechnologie
weiter auszubauen.
Halbleiter-basierte integrierte Schaltkreise werden bis
zum heutigen Tage hauptsächlich in monolithischen
Materialien angefertigt, deren Gitterkonstanten von der
Natur vorgegeben sind. Da die Materialeigenschaften
selbstverständlich für die Leistungsfähigkeit der Schaltkreise
wichtig sind, entwickelten sich in der Vergangenheit
je nach Anwendung verschiedene Halbleitermaterialien
als Plattform für verschiedene Technologien.
Die Silizium-Technologie ist ohne Zweifel dominant auf
dem Halbleitermarkt und entwickelt sich aufgrund des
wachsenden Bedarfs an digitaler Prozessierung rasant
weiter. In optoelektronischen Anwendungen nahe der
870-nm-Wellenlänge wiederum ist das ternäre Halbleitersystem
AlGaAs auf GaAs-Substraten führend. Und
für die Telekommunikation wächst z. Z. der Bedarf an
InP-Einkristallscheiben, da hierauf InGaAsP-Schichten
gitterangepasst erzeugt werden können. Letzteres
Materialsystem besitzt hervorragende Emissionseigenschaften
im Bereich der Wellenlängen 1,3 und 1,55 µm,
die für die Signalverarbeitung via optische Fasersysteme
mit niedrigem Verlust von hoher Bedeutung sind.
Heutzutage ist folglich nur sehr selten aufgrund dieser
Trennung der Substratplattformen eine Interaktion
zwischen der Silizium- und der III-V- (als auch mit der
aufkommenden II-VI) Halbleiterwelt zu beobachten.
towards high-quality semiconductor /
insulator / semiconductor – heterostructures:
interface & lattice engineering
the project goal is the global and / or local integration
of new valuable semiconductor materials in the silicon
technology platform to extend the performance
and functionality of silicon based integrated circuits
(ICs) by the availability of high quality alternative semiconductor
layers with appropriate properties.
Semiconductor-based integrated circuits (ICs) are
built – to date on monolithic materials, mainly with
lattice constants defined by nature. As the properties
of the materials are important for the performance
of the electronic circuitry, different semiconductor
materials became the technology platform of choice
for the various, targeted applications. Si technology
is undoubtedly the dominant semiconductor market
driven by the thirst for digital processing capability.
In applications involving optoelectronics near the
870 nm wavelength, the AlGaAs alloy system on GaAs
is widely employed. And for telecommunications, Inp
substrates became the bulk semiconductor platform,
as InGaAsp can be grown lattice matched to achieve
the desired 1.3 and 1.55 µm wavelength emission
required for low-loss transmission in optical fibers.
today, an interaction between the mature Si and the
rapidly evolving III-V (as well as the upcoming II-VI)
semiconductor worlds can be rarely observed, certainly
due to the processing of the various technologies
with their targeted applications on different semiconductor
platforms.
A n n u A l R e p o R t 2 0 0 6

Abb. 34: Transmissionselektronenmikroskopie (TEM) –
Studie entlang des Si Azimuts des
epi-Si 0,5 Ge 0,5 / (Y 2 O 3 ) 1-x (Pr 2 O 3 ) x (x=0,5 bis 0,75 ) /
Si(111) Systems: (a) Übersicht; (b) Grenzflächen;
(c) Heteroepitaktische Stapelfolge (siehe Text).
60 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Die Vision auf dem Forschungsgebiet der „Engineered
Wafer Systems“ ist die Steigerung der Funktionalität
und / oder Leistungsfähigkeit integrierter Schaltkreise
durch die Überwindung dieser Trennung der elektronischen
Systeme, die historisch bedingt ist, durch die
Verfügbarkeit der verschiedenen Substrate. Die Hauptforschungsrichtung
am IHP ist die monolithische Integration
gitterangepasster bzw. gitterfehlangepasster
alternativer Halbleiter in die Silizium-Plattform, da
diese die reifste und daher auch kommerziell dominierende
Technologie darstellt. Methodisch konzentriert
sich der Forschungsansatz auf die Abscheidung ein-
kristalliner Puffer- und alternativer Halbleiterschichten
mittels der Heteroepitaxie, da neben der Flexibilität
diese Technik eine v.a. kosteneffektive Integration in
die Halbleitertechnologie eröffnet.
the vision of engineered wafer systems is to increase
the functionality and / or performance of integrated
circuits by overcoming these limitations of electronic
systems, brought about by the historical separation
of the different semiconductor platforms. the main
research objective at the IHp is the monolithic integration
of lattice matched or mismatched alternative
semiconductor thin film materials on the mainstream
silicon platform, as the latter is the most mature and
in consequence the commercially most dominant semiconductor
technology worldwide. thereby, the film
deposition method of choice in this research project
is focused on the integration via heteroepitaxy by
the subsequent deposition of single crystalline buffer
and alternative semiconductor layers on the silicon
wafer. this method offers besides the high flexibility
to address in principle global as well as local integration
approaches the important advantage to be appropriate
for achieving the cost-effective integration
of alternative semiconductor materials in the silicon
technology platform under conventional cleanroom
conditions.
Fig. 34: transmission electron Microscopy (teM) Study along
the Si azimuth of the epi-Si 0.5 Ge 0.5 /
(Y 2 o 3 ) 1-x (pr 2 o 3 ) x (x=0.5 to 0.75) / Si(111) system:
(a) overview image; (b) interface study;
(c) heteroepitaxial stacking configuration (see text).

a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Der patentierte IHP-Ansatz besteht in der Erzeugung
von einkristallinen, ternären (A 2 O 3 ) 1-x (B 2 O 3 ) x
(x = 0 bis 1) Mischoxidpuffern auf Silizium-Substraten.
Die 100 %ige Mischbarkeit der Oxidkomponenten
A 2 O 3 und B 2 O 3 ist gewährleistet, da beide in der Ia-3
Kristallstruktur kristallisieren. Aufgrund der weiten
Verbreitung dieser A 2 O 3 -Oxidstruktur über das Periodensystem
ergibt sich eine hohe Flexibilität bei der Integration
von Heterostrukturen mit funktionalen Halbleiterschichten
in Bezug sowohl auf die Gitteranpassung
als auch auf das Maßschneidern von Grenzflächenenergien.
Diese Eigenschaften sind von zentraler Bedeutung
für das Züchten funktionaler Halbleiterschichten
auf dem Puffer mit geschlossener Filmstruktur und hoher
einkristalliner Güte. Zur Demonstration sei die Integration
von SiGe-Schichten hohen Ge-Anteils mittels
(Y 2 O 3 ) 1-x (Pr 2 O 3 ) x -Mischoxiden auf Si(111) betrachtet.
TEM-Studien sind in Abb. 34 für das
epi-Si 0,5 Ge 0,5 / (Y 2 O 3 ) 1-x (Pr 2 O 3 ) x (x = 0,5 bis 0,75) / Si(111)-
System gezeigt. Abb. 34(a) demonstriert die geschlossene
epi-Si 0,5 Ge 0,5 (111) Schicht mit atomarer Rauhigkeit.
Abb. 34(b) zeigt die amorphe Grenzfläche (IF)
zwischen Oxidpuffer und Si(111), die zur Isolation
durch thermische Behandlung nach der Oxid-Epitaxie
erzeugt wird. Die hoch auflösende TEM-Studie 34(c) bezeugt
anhand der Pfeile die für eine Typ A / Typ B / Typ
A Epitaxie typische Stapelfolge. Detaillierte synchrotronbasierte
Röntgenstudien erfolgten an der European
Synchrotron Radiation Facility (E.S.R.F) in Frankreich
zur Verifikation der hier skizzierten Ergebnisse an
epi-Si 1-y Ge y (y = 0 bis 1) / (Y 2 O 3 ) 1-x (Pr 2 O 3 ) x (x = 0 bis 1) / Si(111)
Systemen.
the patented IHp materials science approach consists
of the growth of single crystalline, ternary
(A 2 o 3 ) 1-x (B 2 o 3 ) x mixed oxide buffers on silicon substrates.
Mixed oxide buffers with stoichiometries
varying over the full range from x = 0 to 1 can be
prepared due to the fact that both oxide components
crystallize in the Ia-3 crystal structure. As this A 2 o 3
oxide structure type is quite widespread over the
periodic system of elements, the approach offers a
high flexibility for the integration of functional semiconductor
layers by adjusting the lattice dimension
as well as by tailoring the interface energy of the
oxide buffer. these properties are of central importance
for achieving the integration of valuable semiconductor
layers of closed film morphologies and
of high single crystalline quality. the integration of
SiGe films with high Ge content via (Y 2 o 3 ) 1-x (pr 2 o 3 ) x
buffers on Si(111) is discussed in the following to
demonstrate the feasibility of the approach. Fig.
34 summarizes cross section teM studies of the
epi-Si 0.5 Ge 0.5 / (Y 2 o 3 ) 1-x (pr 2 o 3 ) x (x = 0.5 to 0.75) / Si(111)-
system. Fig. 34(a) shows an overview, confirming the
growth of a closed epi-Si 0.5 Ge 0.5 layer with roughness
limited to the atomic scale. Fig. 34(b) shows an amorphous
interface (IF) between the oxide and Si(111),
prepared after the oxide epitaxy step by post deposition
annealing to improve the electrical properties.
the high-resolution study in Fig. 34(c) illustrates by
dashed arrows the stacking configuration, typical for
type A / type B / type A epitaxy. Detailed Synchrotron
based X-ray diffraction studies at the european Synchrotron
Radiation Facility (e.S.R.F) in France were
applied to verify the here sketched results on the epi-
Si 1-y Ge y (y = 0 bis 1) / (Y 2 o 3 ) 1-x (pr 2 o 3 ) x (x = 0 bis 1) / Si(111)
systems.
A n n u A l R e p o R t 2 0 0 6
6

Si-basierte Nanostrukturen für neue
Bauelementeanwendungen
62 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Si-basierte Nanostrukturen besitzen interessante Eigenschaften,
die für zukünftige Anwendungen in der
Elektronik, Optik, Photovoltaik usw. von Bedeutung
sind. Hier berichten wir über Untersuchungen (a) an
multiplen Stapeln aus alternierenden Si- und SiO 2-
Schichten (MQWs = Multi-Quantum-Wells) und (b) an
Si-Nanodrähten (NWs = Nano-Wires).
(a) Die Si / SiO 2 -MQWs haben wir von der RWTH Aachen
erhalten. Sie wurden mit plasmagestützter CVD abgeschieden,
wobei die Dicke der a-Si-Schichten zwischen
2 und 5 nm variiert wurde und die SiO 2 -Schichten eine
Dicke von 3 nm aufwiesen. Der Einfluss von Wärmebehandlungen
(Ofen, RTA, Laser) und Substratmaterialien
(Quarz, Saphir) auf das Kristallisationsverhalten der Si-
Schichten wurde analysiert.
Dabei zeigt z.B. die Mikro-Raman-Spektroskopie, dass
Si-Nanokristalle, die bei RTA entstehen, stark verspannt
sind. Weiterhin wird die metastabile Si-III-Phase gebildet.
Anschliessende Laserbehandlungen reduzieren
die Druckspannung erheblich. Aus PL-Untersuchungen
geht hervor, dass die elektronische Bandlücke mit sinkender
Dicke der Si-Schichten zunimmt, siehe Abb. 35.
Somit erlauben diese MQWs eine kontrollierte Steuerung
der Bandlücke und sind Kandidaten für neue Sibasierte
Tandem-Solarzellen mit sehr hoher Effizienz.
si-based nanostructures for novel device
applications
Si-based nanostructures offer interesting features
for future applications in electronics, optics, photovoltaics,
etc. Here, we report our observations (a)
on multiple quantum wells (MQWs) consisting of alternating
Si and Sio 2 layers and (b) on Si nanowires
(nWs). the objective is to obtain a deeper insight in
such nanostructures which will help to engineer their
properties.
(a) Stacks of Si / Sio 2 MQWs were provided by RWtH
Aachen. they were deposited by remote plasma enhanced
CVD, with a-Si layer thickness ranging from
2-5 nm and Sio 2 -layer thickness of 3 nm. the influence
of thermal treatments (furnace, RtA, laser) and
substrate materials (quartz, sapphire) on Si crystallization
was analyzed.
For example, micro-Raman investigations showed
that Si nanocrystals formed after RtA are under high
residual stress. Moreover, the metastable Si III phase
was detected. the compressive stress could be
relaxed considerably upon laser annealing. From pl
observations we deduce an increase of the bandgap
with decreasing thickness of the Si layer (Fig. 35).
Accordingly, such MQWs structures are candidates for
bandgap engineering which may allow to realize novel
Si based tandem solar cells with high efficiency.

a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
(b) Die Si-NWs mit einem Durchmesser von ca. 20 nm
wurden durch thermische Verdampfung von SiO hergestellt
und uns von der Zhejiang Universität in Hangzhou,
China bereitgestellt. Sie wurden mit Lumineszenzverfahren
untersucht (PL und CL).
Die Spektren weisen eine Reihe von Linien auf, die auf
ausgedehnte Kristalldefekte innerhalb der Si-NWs, auf
die Grenzfläche zwischen dem Si-Kern und der SiO 2 -
Schale der NWs oder auf die Band-Band-Linie zurückzuführen
sind. Besonders interessant ist, dass mit ansteigender
Temperatur die defekt-bedingten D-Linien
stärker werden. Für Raumtemperatur dominiert die D1-
Linie bei 1550 nm das Spektrum mit effizienter Emission
(Abb. 36).
Erst kürzlich wurde beschrieben, dass die Lichtextraktion,
für LEDs aus Verbindungshalbleiter-Material, stark
anwächst, wenn Nanostab / Nanodraht-Anordnungen
an Stelle von kompakten LEDs verwendet werden. Dieser
Ansatz sollte auch für LEDs, die aus Si-NWs bestehen,
gültig sein.
Abb. 35: Aus der Verschiebung des Maximums der Fotolumineszenz
bei Verringerung der Dicke der Siliziumschicht kann auf
die Vergrößerung des Bandabstandes geschlossen werden.
Der Einsatz zeigt ein Fotolumineszenz-Spektrum von 2 nm
dicken Si-Schichten im MQW-Stapel.
Fig. 35: the increase of the bandgap with decreasing thickness of
the Si layers can be deduced from the peak position
measured by pl. the insert shows a pl spectrum for 2 nm
thick Si layers in the MQW stack.
(b) Si nWs with a diameter of about 20 nm fabricated
by thermal evaporation of Sio were provided by Zhejiang
university Hangzhou, China. they were studied
by luminescence (Cl and pl).
the spectra showed a number of lines which are related
to extended crystal defects inside the nWs, to the
interface between the Si core and Si oxide shell surrounding
the Si nWs or to the Si band-band line. Most
interestingly, with increasing temperature the defect
related D lines become stronger. At room temperature
the D1-line at 1550 nm dominates the spectrum with
efficient emission (Fig. 36).
Recently, it was demonstrated that the light extraction
from an leD was strongly enhanced by using
nanorod / nanowire arrays instead of the entire area
of the leD fabricated from direct compound material.
this approach might also be applied for leDs making
use of Si nWs.
Abb. 36: Die Fotolumineszenz-Spektren von Si-Nanodrähten bei
Raumtemperatur zeigen ein neues intensives Band 4
um 1550 nm. Das obere Spektrum wurde bei planarem
Einfall des Elektronenstrahles beobachtet. Das untere
Spektrum wurde am Querschnitt nach Aufspaltung der
Probe gemessen.
Fig. 36: Cl spectra of Si nanowires measured at room temperature
exhibit a new intensive band 4 around 1550 nm. the
upper spectrum was observed with planar incidence of
the electron beam and the lower spectrum was measured
on the cross-section after cleaving the sample.
A n n u A l R e p o R t 2 0 0 6
6

1,5 µm Emission aus einer
Si MOS-LED
6 A n n u A l R e p o R t 2 0 0 6
a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Unser Ziel war es, eine Si-basierte MOS-LED für die
Lichtemission bei 1,5 µm zu demonstrieren, die mit der
Si-Technologie herstellbar ist.
Die optische Übertragung von Daten auf dem Chip wird
in Zukunft benötigt. Für viele Schlüsselkomponenten
konnte bereits gezeigt werden, dass sie mit der Si-Technologie
realisierbar sind. Ein CMOS-kompatibler elektrisch
gepumpter Lichtemitter ist jedoch noch nicht
verfügbar. Dieser Lichtemitter muss bei Raumtemperatur
(RT) eine ausreichend hohe Effizienz aufweisen und
räumlich begrenzt Licht bei 1,5 µm ausstrahlen.
Kürzlich haben wir gezeigt, dass Si-Waferbonden die reproduzierbare
Herstellung von Versetzungsnetzwerken
mit einer geeigneten Struktur erlaubt, die eine dominante
Lumineszenz der D1-Versetzungslinie bei der geforderten
Wellenlänge von 1,5 µm hervorbringt.
Das Auftreten der Band-Band-Linie bei 1,1 µm bei der
Elektrolumineszenz (EL) von MOS-Tunneldioden ist
bereits bekannt. Ein derartiges EL-Spektrum von einer
MOS-Tunneldiode, das bei RT aufgenommen wurde und
bei dem die BB-Linie dominiert, ist in Abb. 37 gezeigt.
Die entsprechenden physikalischen Grundprozesse für
MOS-LEDs auf n- bzw. p-Si sind in Abb. 38 schematisch
dargestellt. Wenn nun ein Versetzungsnetzwerk mit geeigneter
Struktur in der Nähe der Grenzfläche Si / Oxid
platziert wird - und zwar dicht an der Akkumulationsrandschicht
bzw. innerhalb von ihr – dann dominiert
die D1-Line bei 1,5 µm und nicht mehr die BB-Linie.
Dies zeigt das EL-Spektrum in Abb. 39 deutlich. Der
Tunnelstrom wächst mit zunehmender Vorspannung an
der Gate-Elektrode und führt zu einem Anwachsen der
Lumineszenzintensität. Für die hier gezeigte MOS-LED
auf p-Si befindet sich das Versetzungsnetzwerk in etwa
45 nm Tiefe unterhalb der Si / Oxid-Grenzfläche. Auf
dem etwa 1,8 nm dicken Si-Oxid wurde eine 134 nm dicke
Ti-Gate-Elektrode abgeschieden (mit 7,9 x 10 -3 cm 2
Fläche).
1.5 µm emission from a
si Mos-led
our objective is to demonstrate a Si-based MoS-leD
which emits at 1.5 µm and can be made with Si technology.
on-chip optical interconnects will be essential for future
integrated circuits. Many key components that
can be integrated on the chip have already been realized
using Si technology. A CMoS-compatible electrically
pumped Si-based light emitter is still not available.
the desired light emitter should not only exhibit
a high luminescence efficiency at room temperature
(Rt), but must also be spatially confined and emit at
about 1.5 µm.
Recently, we have demonstrated that Si wafer bonding
allows the reproducible formation of dislocation
networks that exhibit a dominating light emission at
the desired wavelength of about 1.5 µm which is originated
by the dislocation-related D1-line.
electroluminescence (el) with emission of the bandto-band
(BB) line at about 1.1 µm has been observed
from a MoS tunnel diode. A corresponding el spectrum
of a MoS tunnel diode exhibiting BB luminescence
at Rt is shown in Fig. 37. the basic processes
in MoS-leDs on n-type and p-type Si, respectively, are
schematically represented in Fig. 38. When a dislocation
network with appropriate structure is positioned
near the Si / oxide interface, close to / within the accumulation
layer, the radiative recombination is dominated
by the D1 line at about 1.5 µm instead of the
BB line. this is clearly seen from the el spectra shown
in Fig. 39. the tunnelling current increases with increasing
gate voltage, leading to an enhancement of
the el intensity. the MoS-leD on p-type Si, with the
dislocation network at a depth of about 45 nm, consisted
of a 134 nm thick ti gate (7.9 x 10 -3 cm 2 ) deposited
on 1.8 nm thick Si oxide.

a u s G e w ä h l t e p r o J e K t e – s e l e c t e d p r o J e c t s
Die von uns demonstrierte neuartige Si-LED für Infrarot-Emission
kommt beispielsweise ohne eine zusätzliche
Er-Dotierung aus und ist voll mit der Si-Technologie
kompatibel. Unsere Abschätzungen zeigen, dass
wir eine RT-Effizienz von etwa 1 % erwarten können,
wenn die von uns vorgeschlagenen Verbesserungen umgesetzt
werden.
Abb. 37: Die Elektrolumineszenz einer MOS Tunneldiode auf p-Si
zeigt bei Raumtemperatur Band-Band Lumineszenz mit
einer Effizienz >0,1 %. Der Einschub zeigt die Abhängigkeit
der Elektrolumineszenz vom Strom.
Fig. 37: el of a MoS tunnel diode on p-Si exhibiting BB luminescence
at Rt with an efficiency > 0.1 %. the insert
shows the dependence of the el signal on the current
level.
the novel Si leD for IR emission does not require
additional er doping and is fully compatible with Si
technology. According to our estimates and proposed
improvements it offers the capability for an efficiency
around 1 % at Rt.
Abb. 38: Modell einer MOS-LED, (a) p-Material mit einem Versetzungsnetzwerk,
das sowohl Versetzungs-Lumineszenz
als auch Band-Band-Lumineszenz zeigen kann (b) n-Si
ohne Versetzungsnetzwerk zeigt nur Band-Band-
Lumineszenz.
Fig. 38: Scheme of MoS-leD, (a) p-type material with dislocation
network, capable of yielding both dislocation and BB
luminescence, (b) n-type Si without network yielding BB
luminescence only.
Abb. 39: Elektrolumineszenz einer MOS-LED bei 80 K unter
negativer Gatespannung mit durch ein Versetzungsnetzwerk
nahe der Si / Oxid-Grenzfläche hervorgerufener
Strahlung bei 1,5 µm. Die Intensität wächst unterpropor-
tional mit zunehmendem Tunnelstrom, wie in den Spektren
bei 2, 5 und 8 mA erkennbar ist. Der Einsatz zeigt die
Strom-Spannungs-Abhängigkeit der LED bei 300 K.
Fig. 39: electroluminescence at 80 K of a MoS-leD under
negative gate bias with 1.5 µm radiation caused by the
dislocation network near the Si / oxide interface. the
intensity is found to increase sub-linearly with
increasing tunneling current as seen from the spectra
measured at 2, 5 and 8 mA, respectively. the insert
represents the I-V characteristic of the leD at 300 K.
A n n u A l R e p o R t 2 0 0 6
6

66 A n n u A l R e p o R t 2 0 0 6
G e M e i n s a M e l a b o r e – J o i n t l a b s
Joint Labs

Gemeinsames Labor IHP/BTU
Das Gemeinsame Labor IHP / BTU auf dem Campus
der Brandenburgischen Technischen Universität (BTU)
Cottbus besteht seit 2000. Es bündelt die Forschungspotentiale
beider Partner und leistet – unter maßgeblicher
Einbeziehung von Studenten – interdisziplinäre
Forschung auf dem Gebiet der Halbleitermaterialien.
Dabei bezieht es Lehrstühle der BTU in seine Forschungstätigkeit
ein, wie Experimentalphysik II / Materialwissenschaften,
Theoretische Physik, Physikalische
Chemie oder Schaltkreisentwurf. Darüber hinaus ist
auch die Fachhochschule Lausitz mit dem Gemeinsamen
Labor assoziiert und beteiligt sich durch technisch-präparative
Arbeiten.
National arbeitet das Gemeinsame Labor im Rahmen
seiner Projektarbeit mit einer ganzen Reihe von Forschungseinrichtungen
wie dem MPI Halle, den Universitäten
Göttingen, Jena, Stuttgart, RWTH Aachen, HMI
Berlin oder dem IPHT Jena und dem Unternehmen Siltronic
AG, Burghausen, vertraglich zusammen.
Eine wichtige Aufgabe stellt auch der Ausbau der internationalen
Vernetzung des Gemeinsamen Labors dar.
Die BTU und das IHP sind über das Gemeinsame Labor
Mitglied im internationalen Konsortium SiWEDS (Silicon
Wafer Engineering & Defect Science Center, siehe
www.mse.ncsu.edu / siweds / ), dem renommierte Halbleiterfirmen,
wie z.B. Texas Instr., Toshiba, Samsung,
Siltronic AG, Centrotherm GmbH, und namhafte Universitäten,
wie z.B. MIT, Stanford, UC Berkeley, angehören.
International wurden neben den bestehenden Verbindungen
in 2006 Zusammenarbeiten mit dem Institut
MESA+ an der Universität Twente (Niederlande) und
mit dem Unternehmen SOITEC S.A. (Frankreich) begonnen.
Ebenso arbeitet das Gemeinsame Labor aktiv im
Europäischen Projekt CADRES (Coordinated Action on
Defects Related to Engineering Advanced Silicon Based
Devices) mit an dem eine große Zahl europäischer Universitäten,
Forschungseinrichtungen und Unternehmen
beteiligt sind.
G e M e i n s a M e l a b o r e – J o i n t l a b s
Joint lab ihp / btu
the Joint lab IHp / Btu located at the campus of the
Brandenburg technical university Cottbus (Btu) was
founded in 2000. It pools the research potential of
the partners IHp and Btu and conducts interdisciplinary
research – with substantial participation of
students – in the field of semiconductor materials.
the Btu chairs experimental physics II / Materials
Science, theoretical physics, physical Chemistry and
Circuit Design are closely involved in its research activities.
the nearby university of Applied Sciences
lausitz is also associated with the Joint lab and contributes
engineering and preparation work.
Within the framework of its research projects, the
Joint lab collaborates on contract basis nation-wide
with various research facilities such as e.g. MpI Halle,
universities in Göttingen, Jena, and Stuttgart, RWtH
Aachen, HMI Berlin or IpHt Jena, and with the wafer
manufacturer Siltronic AG, Burghausen.
the expansion of its international networking is a further
important task of the Joint lab. Btu Cottbus and
the IHp - via IHp / Btu Joint lab - are a member of the
international consortium SiWeDS (Silicon Wafer engineering
& Defect Science Center, see www.mse.ncsu.
edu / siweds / ), associating noted semiconductor
companies, e.g. texas Instruments, toshiba, Samsung,
Siltronic AG, Centrotherm GmbH and well-known universities
such as MIt, Stanford and uC Berkeley. In
addition to the already existing international scientific
contacts, new collaborations with the institute
MeSA+ at university twente (netherlands) and with
the company SoIteC S.A. (France) were started in
2006. Moreover, the Joint lab actively participates
in the european project CADReS (Coordinated Action
on Defects Related to engineering Advanced Silicon
Based Devices), which involves numerous european
universities, research facilities and companies.
A n n u A l R e p o R t 2 0 0 6
67

Im Jahr 2006 bearbeitete das Gemeinsame Labor vier
Drittmittelprojekte, darunter zwei BMBF-Projekte, ein
Projekt der Volkswagenstiftung und ein Industrieprojekt.
Der Bund und das Land Brandenburg förderten
bis Ende 2006 im Rahmen des Hochschul- und Wissenschaftprogramms
HWP im Gemeinsamen Labor den
Aufbau eines Kompetenzzentrums für Halbleitermaterialien
und -technologien. In diesem Zusammenhang
wurde die Kernkompetenz des Gemeinsamen Labors
„Maßschneidern der Eigenschaften des Silizium-Materials“
durch grundlagenorientierte Vorlaufforschung
weiter ausgebaut. Im Bewusstsein, dass die entwickelte
Si-Technologie heute über breite Möglichkeiten verfügt
und nach neuen Anwendungen sucht, beteiligt sich das
Gemeinsame Labor an Arbeiten, dem Silizium Eigenschaften
„anzutrainieren“, die seinen künftigen Einsatz
auf neuen Einsatzfeldern gestatten soll.
Basierend auf den Ergebnissen dieser Vorlaufforschung
– zu der z.B. Si-basierte Lichtemitter, Si-basierte Nanostrukturen
wie c-Si / SiO 2 -Schichtstapel und Si-Nanodrähte
oder die kontrollierte Platzierung von Biomolekülen
auf Si für Biochips zählen – werden für das
IHP Entscheidungen für seine zukünftige inhaltliche
Ausrichtung vorbereitet.
Die langfristigen Forschungsschwerpunkte des Gemeinsamen
Labors zum Komplex „Silizium“ sollen Beiträge
zur Weiterentwicklung der Mikroelektronik, zur Einführung
einer Si-basierten Nanoelekronik, zur Einführung
einer Si-basierten Photonik, zur Verknüpfung von Si mit
der Biologie und zur Unterstützung der Si-basierten
Photovoltaik liefern. Auf dem letztgenannten Gebiet
ist das Gemeinsame Labor in der BTU-Forschungeinrichtung
CeBra (Centrum für Energietechnologie Brandenburg,
siehe www.tu-cottbus.de / cebra / ) verankert.
68 A n n u A l R e p o R t 2 0 0 6
G e M e i n s a M e l a b o r e – J o i n t l a b s
In 2006 the Joint lab worked on four projects funded
by third parties, among them two projects funded
by the BMBF (Federal Ministry of education and
Research), one project funded by Volkswagenstiftung
and one industry project. Within the framework of
their university and science program, the Federal Republic
of Germany and the State of Brandenburg provided
support for the development of a centre of expertise
for semiconductor materials and technology
in the Joint lab until the end of 2006. this grant allowed
conducting fundamental cutting-edge research
and strengthening the Joint lab’s core competency
“tailoring of Si material properties”.
Aware of the high capabilities of advanced Si technology
and the constant search for new applications,
the Joint lab participates in research aimed at “teaching”
the silicon material new properties that are
to enable the use of Si in new application areas. the
results of this cutting-edge research, comprising Sibased
light emitters, Si-based nanostructures such
as c-Si / Sio 2 stacks or Si nanowires, and controlled
binding of biomolecules to Si for future biochips,
will serve as a basis for decisions regarding future research
directions at IHp.
the long-term research topics of the Joint lab in the
field of silicon aim to contribute to future developments
in microelectronics, implementation of Sibased
nanoelectronics, implementation of Si-based
photonics, interfacing Si electronics with biology, and
support for Si-based photovoltaics. With the latter research
field, the Joint lab is connected to the Btu
research facility CeBra (Center for energy technology
Brandenburg, see www.tu-cottbus.de / cebra / ).

Die Arbeiten zum Komplex „Silizium“ sind inhaltlich
wie folgt strukturiert und werden im Rahmen von Projekten,
meist in Arbeitsteilung mit externen Partnern,
verfolgt:
Mikroelektronik
- Si für zukünftige Halbleitertechnologien
(Forschungsvertrag mit Siltronic AG)
- Si-basierte Lichtemitter (BMBF-Projekt
„SILEM“ mit MPI Halle und Universität Stuttgart)
- Diagnostik für die Si-Material- und Technologieentwicklung
(Vereinbarung mit SOITEC S.A.,
Frankreich)
Nanoelektronik
- Si / SiO 2 – Schichtstapel mit Dicken im nm-Bereich
(Kooperation mit der RWTH Aachen)
- Si-Nanodrähte (Kooperation mit Zhejiang Univ.,
Hangzhou, VR China)
Verknüpfung Si mit Biomolekülen
- Kontrollierte Platzierung von Biomolekülen auf Si
(Volkswagen-Projekt „SOBSI“ mit MPI Halle,
IPHT Jena, Universität Göttingen)
Photovoltaik
- Bandstrukturdesign für zukünftige Höchsteffizienz-
Solarzellen (BMBF-Projekt „Bandstrukturdesign…“
mit RWTH Aachen, HMI Berlin, Universitäten
Stuttgart und Jena)
- Einfluß von Verunreinigungen auf die elektrische
Wirkung von Kristalldefekten in Si (Vorbereitung
des BMU-Verbundrojektes „SolarFocus“ an dem
sich deutsche Unternehmen der Photovoltaikbranche
und Forschungseinrichtungen wie FhG
ISE Freiburg oder ISF Hameln sowie Hochschulen
wie u.a. Universitäten Konstanz, Freiberg …
beteiligen)
Transport in Si-basierten Quantenstrukturen
- Theorie für schnelle Si-Nanodraht-FETs
Pulsed Laser Deposition
- Erzeugung von Nanostrukturen
Im Jahr 2006 wurden von den IHP-Mitarbeitern im Gemeinsamen
Labor mehr als 24 Publikationen veröffentlicht,
46 Vorträge, darunter 7 eingeladene, gehalten und
4 Patente angemeldet. Ein Vortrag auf der Internationalen
Konferenz EDS-2006 wurde mit dem „Helmut Alexander
Award“ ausgezeichnet.
G e M e i n s a M e l a b o r e – J o i n t l a b s
the research activities within the complex “Silicon”
are organized in the form of projects as given below
and are mostly carried out in collaboration with external
partners:
Microelectronics
- Si for future semiconductor technologies
(research contract with Siltronic AG)
- Si-based light emitter (project “SIleM”, funded
by BMBF, collaboration with MpI Halle and
university Stuttgart)
- Diagnostics for Si materials and technology
development (non-disclosure agreement with
SoIteC S.A., France)
nanoelectronics
- Si / Sio 2 stacks of nm thickness
(cooperation RWtH Aachen)
- Si nanowires (cooperation with Zhejiang
university, Hangzhou, p.R. China)
interfacing si with biomolecules
- Controlled binding of biomolecules on Si
(project “SoBSI”, funded by Volkswagenstiftung,
collaboration with MpI Halle, IpHt Jena and
university Göttingen)
photovoltaics
- Band structure design for future high-efficiency
solar cells (project funded by BMBF, collaboration
with RWtH Aachen, HMI Berlin, university
Stuttgart, university Jena)
- Impact of impurities on the electrical effect of
crystal defects in Si (preparation of joint project
“SolarFocus”, to be funded by BMu, participation
of German pV companies, research institutes
and universities )
transport in si-based Quantum structures
- theory of fast Si nanowire Fets
pulsed laser deposition
- Manufacturing of nanostructures
In 2006, more than 24 publications, 46 presentations
(among them 7 invited) and 4 patents originated
from research of IHp scientists in the Joint lab. A
contribution at the international conference eDS-
2006 received the “Helmut Alexander Award”.
A n n u A l R e p o R t 2 0 0 6
6

Für die laufenden Projekte standen für das Jahr 2006
mehr als 600 T Euro eingeworbene Drittmittel zur Verfügung.
Hervorzuheben ist auch die Beteiligung des Gemeinsamen
Labors an der Ausrichtung von Internationalen
Konferenzen wie der International Conference „Extended
Defects in Semiconductors“ (EDS 2006) vom
17.- 22. September 2006 in Halle und dem Symposium
„Advanced Silicon for the 21 st Century“ auf dem
EMRS / IUMRS Spring Meeting vom 29.05.-02.06.2006
in Nizza.
Das Gemeinsame Labor unterstützt das Lehrangebot
der BTU mit Vorlesungen, Übungen und Praktika.
Weiterführende Informationen über das Gemeinsame
Labor sind unter www.jointlab.de abrufbar.
Gemeinsames Labor IHP/TFH Wildau
Das gemeinsame Forschungs- und Ausbildungszentrum
(Joint Lab) des IHP und der Technischen Fachhochschule
Wildau (TFHW) wurde am 20.02.2006 in Anwesenheit
der Ministerin für Wissenschaft Forschung und
Kultur des Landes Brandenburg, Frau Prof. Dr. Johanna
Wanka, des Präsidenten der TFH Wildau, Prof. Dr.
László Ungvári, und des Wissenschaftlich-Technischen
Geschäftsführers des IHP, Prof. Dr. Wolfgang Mehr,
feierlich eröffnet. Auf der Basis des Forschungs- und
Entwicklungsvertrages IHP-TFH Wildau vom 30. April
2005 sind konkrete Schritte zur Koordinierung der Aktivitäten
in Forschung und Lehre an beiden Institutionen
festgelegt worden, die unter dem Dach eines gemeinsamen
Labors, dem „Joint Lab IHP / TFHW“ stattfinden
sollen.
Der Forschungsschwerpunkt des Joint Lab ist die Entwicklung
neuartiger siliziumbasierter Devicekonzepte.
70 A n n u A l R e p o R t 2 0 0 6
G e M e i n s a M e l a b o r e – J o i n t l a b s
third party funding of more than 600,000 euR was obtained
for the current projects in 2006.
Worth emphasizing is the participation of the Joint
lab in the organisation of international conferences
such as the International Conference “extended Defects
in Semiconductors” (eDS 2006) in Halle and the
Symposium “Advanced Silicon for the 21 st Century” at
the eMRS Spring Meeting 2006 in nice (France).
the Joint lab supports teaching at Btu Cottbus by
lectures, exercises and practical courses.
For further information about the Joint lab IHp / Btu
please visit the website www.jointlab.de.
Joint lab ihp / tFh wildau
the common research and education centre (Joint
lab) of the IHp and the university of Applied Sciences
Wildau (tFHW) was inaugurated on February 20,
2006 in presence of the minister for science, research
and culture of Brandenburg, prof. Johanna Wanka,
the president of the tFH Wildau, prof. lászló ungvári,
and the scientific director of the IHp, prof. Wolfgang
Mehr. on the basis of the research and development
contract between IHp and tFH Wildau dated April 30,
2005, concrete steps were defined for the coordination
of activities in research and teaching in both institutions
which are to take place under the auspices of
a common lab, the “Joint lab IHp / tFHW”.
the main research focus is on the development of
new silicon-based device concepts.

Im Rahmen des Projektes: „Deposition und Strukturierung
von Funktionsschichten für neuartige Bauelemente
der Informationstechnologie und Sensorik“ wurde ein
siliziumbasierter Testchip entwickelt, der eine detaillierte
Charakterisierung elektronischer Transporteigenschaften
erlaubt. Erste Versuchsmuster dieser Testchips
befinden sich gegenwärtig in der Evaluierungsphase.
Diese Entwicklung wurde im Rahmen des Europäischen
Forschungsnetzwerkes EUROFET (http:www.tfh-wildau.
de / iplpt / eurofet / ) durchgeführt, welches die TFHW
koordiniert. Durch die Entwicklung des Testchips steht
eine schnelle Methode zur Erfassung relevanter elektronischer
Materialparameter zur Verfügung.
Für das Projekt „Minimal-invasiver Glucose Sensor
(MIBS)“ wurden durch Joint-Lab-Mitarbeiter der TFHW
Beiträge bei der Auswahl unterschiedlicher Materialien
geleistet.
Ein weiteres, zentrales Arbeitsgebiet des Joint Lab ist
die gemeinsame Lehre. Dazu gehört die Einbindung
fachlicher Aspekte der Chipherstellung (IHP) in das
Studium der „Physikalischen Technik“ an der TFH Wildau.
Ziel ist es, die vorhandenen Module des Hauptstudiums
mit anwendungsorientierten Lehrinhalten aus
dem Bereich der Mikroelektronik zu untersetzen. Damit
wird eine weitere Praxiskomponente, die sich in die
Hauptlinie der Ausbildung an der TFH einordnet, für die
Studierenden angeboten. Zwei Praktika am IHP sind
als Pflicht- und Wahlpflichtfach in das Hauptstudium
der „Physikalischen Technik“ integriert. Im Jahre 2006
wurden 12 Praktikums- und Diplomarbeiten durch Studenten
der TFH Wildau am IHP angefertigt und durch
Mitarbeiter des IHP betreut.
G e M e i n s a M e l a b o r e – J o i n t l a b s
Within the scope of the project: “Deposition and
structuring of functional layers for new device elements
in information and sensor technology“, a silicon-based
test chip which permits a detailed characterization
of electronic transport properties was
developed. presently the first experimental models
of these test chips are in the evaluation phase. this
development was carried out within the scope of the
european research network euRoFet (http:www.tfhwildau.de
/ iplpt / eurofet / ) which is coordinated by
the tFHW. By the development of the test chip a quick
method for aquisition of relevant electronic material
parameters is available.
Members of the Joint lab contributed to the selection
of materials in the project “Minimum-invasive
glucose sensor (MIBS)“.
Another central field of activity in the Joint lab is
common teaching. this includes the integration of
technical aspects of chip processing (IHp) into the
study of “physical technology“ at the tFH Wildau.
the objective is to complement the existing modules
of the main study with application-oriented teaching
contents from the field of microelectronics. In this
way another practice-orientated component is integrated
into the outline of the education at the tFHW
and made available to the students. two training
courses at the IHp are integrated as compulsory and
electoral compulsory subjects into the main study of
“physical technology”. In 2006, 12 training course
papers and diploma theses were contributed by students
of the tFH Wildau at the IHp which were supervised
by employees of the IHp.
A n n u A l R e p o R t 2 0 0 6
7

72 A n n u A l R e p o R t 2 0 0 6
K o n F e r e n Z e n u n d w o r K s h o p s – c o n F e r e n c e s a n d w o r K s h o p s
Conferences and Workshops

K o n F e r e n Z e n u n d w o r K s h o p s – c o n F e r e n c e s a n d w o r K s h o p s
Workshop des National NanoFab Center (NNFC),
Korea mit dem IHP zum Thema „Cooperation in
the Field of Nanotechnology”,
12. – 16. Februar 2006, Frankfurt (Oder).
Auf diesem durch das BMBF geförderten Workshop informierten
sich die Partner gegenseitig über ihre aktuellen
Forschungsvorhaben und aussichtsreiche Themen
für eine Kooperation. Bei einem Gegenbesuch in Korea
wurde dazu ein Memorandum of Understanding unterzeichnet.
symposium „silicon Materials science and technology
X” innerhalb der 209. ecs-tagung,
8. – 11. Mai 2006, denver, usa.
Im Mittelpunkt dieser bereits zum zehnten Mal stattfindenden
viertägigen Veranstaltung standen Materialfragen
und technologische Aspekte von Silizium.
Ein Mitarbeiter des IHP war maßgeblich an der Vorbereitung
und Durchführung des Symposiums beteiligt.
Workshop „From Research to Innovation”
17. – 19. Mai 2006, Szczecin, Polen.
Im Rahmen des Workshops wurden Fragen der innovativen
Verwertung von Forschungsergebnissen diskutiert.
Die gemeinsam von Mitarbeitern des IHP und der TU
Szczecin organisierte und durchgeführte Veranstaltung
fand im Rahmen des Deutsch-Polnischen Jahres statt.
E-MRS 2006 Spring Meeting,
29. Mai – 2. Juni 2006, Nizza, Frankreich.
Es wurden drei Symposien maßgeblich durch IHP-Mitarbeiter
organisiert:
Symposium A: „Current Trends in Nanoscience -
from Materials to Applications”
Symposium L: „Characterisation of High-k
Dielectric Materials”
Symposium V: „Advanced Silicon for the 21st Century”
workshop of the national nanoFab center (nnFc),
Korea with the ihp on “cooperation in the Field
of nanotechnology”,
February 12 -16, 2006, Frankfurt (oder).
At this Workshop supported by the BMBF the partners
informed one another about their current research
projects and promising topics for a cooperation. During
a return visit in Korea a Memorandum of understanding
was signed.
symposium “silicon Materials science and technology
X” within the 209th ecs Meeting,
May 8 – 11, 2006, denver, usa.
In the focus of this four-day meeting, taking place for
the tenth time, were material issues and technological
aspects of silicon.
A member of the IHp was significantly involved in the
preparation and implementation of the symposium.
workshop “From research to innovation”
May 17 – 19, 2006, szczecin, poland.
During the workshop questions related to the utilization
of research results for innovations were discussed.
the meeting, jointly organized and implemented by
members of the IHp and the technical university of
Szczecin, took place in the context of the Germanpolish
year.
e-Mrs 2006 spring Meeting,
May 29 – 2 June 2, 2006, nice, France.
three symposia were significantly organized by IHp
staff:
Symposium A: “Current trends in nanoscience -
from Materials to Applications”
Symposium l “Characterisation of High-k
Dielectric Materials”
Symposium V: “Advanced Silicon for the
21st Century”
A n n u A l R e p o R t 2 0 0 6
7

7 A n n u A l R e p o R t 2 0 0 6
K o n F e r e n Z e n u n d w o r K s h o p s – c o n F e r e n c e s a n d w o r K s h o p s
IHP-Symposium „Halbleiter und Nanostrukturen“,
14. Juni 2006, Frankfurt (Oder).
Auf diesem Symposium berichteten namhafte Wissenschaftler
deutscher Forschungseinrichtungen über ihre
aktuellen Arbeiten.
Die vom IHP organisierte Veranstaltung diente auch der
Würdigung verdienstvoller Mitarbeiter des Institutes,
die altersbedingt ausscheiden.
14 th Workshop on Dielectrics in Microelectronics
(WoDiM), 26. – 28. Juni 2006, Catania, Italien.
Hauptziel des Symposiums war es, Spezialisten auf dem
Gebiet der Dielektrika und deren Anwendungen in der
Mikroelektronik zusammenzubringen.
Ein Mitarbeiter des IHP war im internationalen Organisationskomitee
der WoDiM tätig. Im Jahr 2008 wird
diese Tagung durch das IHP organisiert und in Bad
Saarow in der Nähe von Frankfurt (Oder) stattfinden.
Fünfter Internationaler Sommerstudiengang Mikroelektronik,
28. August – 2. September 2006, Frankfurt (Oder).
Zu dieser Veranstaltung zum Thema Technologien und
Materialien für die drahtlose Kommunikation waren
Studenten aus Ost- und Mitteleuropa eingeladen.
Vorbereitet und durchgeführt wurde sie durch das IHP
gemeinsam mit dem Investorcenter Ostbrandenburg
und der Europauniversität Viadrina.
European Microwave Week, Workshop WS2 „SiGeC
HBT: Device Technology and Applications”,
10. September 2006, Manchester, Großbritannien.
Auf diesem Workshop wurden die SiGe BiCMOS-Technologien
des IHP und deren Anwendung für Radar,
60-GHz-Transceiver, schnelle A/D-Wandler und UWB-
Schaltkreise vorgestellt.
Der Workshop wurde von der Universität Paderborn organisiert
und vom IHP durchgeführt.
ihp-symposium “semiconductors and nanostructures“,
June 14, 2006, Frankfurt (oder).
At this symposium well-known scientists from German
research institutions reported on their current work.
the meeting organized by the IHp also served as a
framework for the appraisal of merited members of
the institute, about to retire from office due to age.
14 th workshop on dielectrics in Microelectronics
(wodiM), June 26 – 28, 2006, catania, italy.
the main objective of the symposium was to bring together
specialists working in the field of dielectrics
and all aspects of their applications in microelectronics.
A scientist of the IHp was a member of the international
WoDiM organisation committee. the next symposium
in 2008 will be organized by the IHp and take
place in Bad Saarow near Frankfurt (oder).
Fifth international summer school on
Microelectronics,
august 28 – september 2, 2006, Frankfurt (oder).
the topic of the summer school was technologies and
materials for wireless communication. Students from
east and Central europe were invited to participate.
the meeting was organized and implemented by the
IHp together with the Investor Center ostbrandenburg
and the european university Viadrina.
european Microwave week, workshop ws2 “siGec
hbt: device technology and applications”,
september 10, 2006, Manchester, uK.
IHp’s SiGe BiCMoS technologies and their application
for radar, 60 GHz transceivers, fast A/D converters and
uWB circuits were presented at the workshop.
the event was organized by the university of paderborn
and implemented by the IHp.

K o n F e r e n Z e n u n d w o r K s h o p s – c o n F e r e n c e s a n d w o r K s h o p s
Internationale Konferenz „Extended Defects in Semiconductors“,
17. – 22. September 2006, Halle.
Wichtige Themen waren das Auftreten von Defekten bei
der Erzeugung von Nanostrukturen sowie der Vergleich von
Experimenten und der theoretischen Beschreibung mehrdimensionaler
Defekte und Nanostrukturen in Halbleitern.
Ein Mitarbeiter des IHP war einer der beiden Vorsitzenden
der Veranstaltung.
Fünfter IHP-Workshop „High-Performance SiGe
BiCMOS for Wireless and Broadband Communication”,
25. September 2006, Frankfurt (Oder).
Auf diesem jährlich stattfindenden Kooperationsworkshop
informierte das IHP über seine neuesten
Forschungsergebnisse. Schwerpunkte waren die BiC-
MOS-Technologien und deren Verfügbarkeit für MPW &
Prototyping sowie neueste Hochfrequenzschaltungen.
Der Workshop wurde durch das IHP organisiert und unter
Einbeziehung von Partnern durchgeführt.
Zweites Tutorial „IHP Design Kits”,
26. – 27. September 2006, Frankfurt (Oder).
Im Anschluß an den Workshop vom 25. September fand
ein zweitägiges Tutorial statt, bei dem die Teilnehmer
die zur Nutzung der IHP-Technologien notwendigen
Spezialkenntnisse erlernen bzw. vertiefen konnten.
Die Veranstaltung wurde vom IHP organisiert und durch
die advICo GmbH durchgeführt.
Symposium „SiGe: Materials, Processing, and Devices“
innerhalb der 210. ECS Tagung, 29. Oktober –
3. November 2006, Canun, Mexico.
Die Konferenz war die zweite Veranstaltung im Rahmen einer
Konferenzreihe, die alle zwei Jahre stattfindet. Schwerkunkte
waren SiGe und Ge vom Material über Aspekte der
Prozesstechnologie bis zu Bauelementeanwendungen.
Ein Mitarbeiter des IHP ist für den Prozesstechnologieteil
der Konferenz verantwortlich.
international conference “extended defects in
semiconductors”, september 17 – 22, 2006, halle.
Key subjects were the appearance of defects in relation
to the formation of nanostructures and the comparison
of experiments and the theoretical description of extended
defects and nanostructures in semiconductors.
An IHp member was one of the two chairpersons of
the conference.
Fifth ihp-workshop “high-performance siGe bic-
Mos for wireless and broadband communication”,
september 25, 2006, Frankfurt (oder).
At this annual cooperation workshop the IHp informed
about its newest research results. In the focus
were the BiCMoS technologies and their availability
for MpW & prototyping as well as the latest high-frequency
circuits.
the workshop was organized by the IHp and implemented
together with partners.
second tutorial “ihp design Kits”,
september 26 – 27, 2006, Frankfurt (oder).
Following the workshop on September 25, a two day
tutorial took place during which the participants
learned and reinforced the special knowledge necessary
for the utilization of the IHp technologies.
the tutorial was organized by the IHp and implemented
by the advICo GmbH.
symposium “siGe: Materials, processing, and devices”
within the 210 th ecs Meeting, october 29 –
november 3, 2006, canun, Mexico.
the conference was the second event within a biannual
series. SiGe and Ge, from materials to aspects of
processing and device applications, were in the focus.
An IHp scientist is responsible for the technology
part of the conference.
A n n u A l R e p o R t 2 0 0 6
7

76 A n n u A l R e p o R t 2 0 0 6
Z u s a M M e n a r b e i t u n d p a r t n e r – c o l l a b o r a t i o n a n d p a r t n e r s
Collaboration and Partners

Industrie / Industry*
Z u s a M M e n a r b e i t u n d p a r t n e r – c o l l a b o r a t i o n a n d p a r t n e r s
AdMoS GmbH, Germany
advICo microelectronics GmbH, Germany
Airbus Deutschland GmbH, Germany
AIXtRon AG, Germany
Alcatel Sel AG, Germany
Alcatel-lucent, Germany
Alfa Microonde snc, Italy
Alpha europe GmbH, Germany
Alpha pacific technologies Co ltd., taiwan
Applied Ceramics europe AG, lichtenstein
Applied Materials GmbH, Germany
ASM europe B.V., the netherlands
Atmel Germany GmbH, Germany
Bio Sensor technologie GmbH, Germany
Centellax Inc., uSA
centrotherm GmbH+Co. KG, Germany
Coreoptics GmbH, Germany
DaimlerChrysler Research Centre, Germany
eADS Deutschland GmbH, Germany
enpirion Inc., uSA
eurescom GmbH, Germany
eVision Systems, Germany
Freescale Semiconductor Germany GmbH, Germany
Gaisler Research, Sweden
Genesys ltd., ukraine
GWt-tuD GmbH, Germany
HtC Consulting, Germany
IBM Research GmbH, Switzerland
IMSt GmbH, Germany
Infineon technologies AG, Munich, Germany
Infineon technologies AG, ulm, Germany
InnoSent GmbH, Germany
Kayser-threde GmbH, Germany
KMSD, lithuania
KotuRA Inc., uSA
leica Camera AG, Germany
lesswire AG, Germany
lintec Information technologies AG, Germany
MeDAV GmbH, Germany
Mergeoptics GmbH, Berlin, Germany
MIpS technologies International AG, Germany
nokia Research Centre, Germany
phasor Solutions, uK
philips Consumer electronics B.V. , the netherlands
philips Research laboratories Aachen, Germany
philotech GmbH, Germany
Qimonda AG Dresden, Germany
Robert Bosch GmbH, Germany
Rohde & Schwarz GmbH & Co. KG, Germany
Sennheiser electronic GmbH & Co. KG, Germany
Siemens AG, Germany
Siltronic AG, Germany
Sitec GmbH, Germany
StMicroelectronics S.R.l., Italy
Stratalight Communications Inc., uSA
telefunken Radio Communication Systems GmbH und
Co. KG, Germany
teS electronic engineering GmbH, Germany
teS electronic Solutions GmbH, Germany
texas Instruments Deutschland GmbH, Germany
t-Systems nova GmbH, Germany
umicore, Belgium
Wisair ltd., Israel
* Ausgewählte Partner / Selected partners
A n n u A l R e p o R t 2 0 0 6
77

78 A n n u A l R e p o R t 2 0 0 6
Z u s a M M e n a r b e i t u n d p a r t n e r – c o l l a b o r a t i o n a n d p a r t n e r s
Forschungsinstitute und Universitäten /
research institutes and universities*
Aalen university of Applied Sciences, Germany
Astron, the netherlands
Brandenburg technical university, Germany
Brandenburg university of Applied Sciences, Germany
Budapest university of technology and economics,
Hungary
etH Zurich, Switzerland
etRI, Daejeon, Korea
european Synchrotron Radiation Facility, France
european university Viadrina of Frankfurt (oder),
Germany
Fraunhofer IIS, erlangen, Germany
Fraunhofer IpMS, Dresden, Germany
Fraunhofer IZM, Berlin, Germany
Fraunhofer HHI, Berlin, Germany
Freie universität Berlin, Germany
Friedrich-Alexander-university erlangen-nuremberg,
Germany
Friedrich-Schiller-university Jena, Germany
Georg-August-university of Göttingen, Germany
Georgia Institute of technology, uSA
Hahn-Meitner Institute Berlin, Germany
Humboldt university of Berlin, Germany
Institute of Computer Science, ICS-FoRtH, Greece
Istanbul technical university, turkey
ludwig-Maximilians-university of Munich, Germany
Max planck Institute of Microstructure physics,
Germany
Microsoft Innovation Center, Aachen, Germany
national nanoFab Center (nnFC), Korea
national taiwan university, taiwan
politecnico di torino, Italy
progress Microelectronics Research Institute,
Moscow, Russia
Radiolabs, Rome, Italy
Rome university “la Sapienza”, Italy
Ruhr-university of Bochum, Germany
RWtH Aachen university, Germany
Sabanci university Istanbul, turkey
Southeast university nanjing, China
Szczecin university of technology, poland
technical university of Berlin, Germany
technical university of Braunschweig, Germany
technical university of Dresden, Germany
technical university of Ilmenau, Germany
technical university of Munich, Germany
technical university of ukraine, ukraine
tohoku university Sendai, Japan
university di Firenze, Italy
university of Applied Sciences Wildau, Germany
university of Bergen, norway
university of Bremen, Germany
university of Bristol, uK
university of California, uSA
university of Cantabria, Spain
university of Chicago, uSA
university of Dortmund, Germany
university of Karlsruhe, Germany
university of Kassel, Germany
university of osnabrück, Germany
university of oulo, Finland
university of paderborn, Germany
university of potsdam, Germany
university of Stuttgart, Germany
university of ulm, Germany
Victoria university of Manchester, uK
Zhejiang university, China
* Ausgewählte Partner / Selected partners

Z u s a M M e n a r b e i t u n d p a r t n e r – c o l l a b o r a t i o n a n d p a r t n e r s
A n n u A l R e p o R t 2 0 0 6
7

G a s t w i s s e n s c h a F t l e r u n d s e M i n a r e – G u e s t s c i e n t i s t s a n d s e M i n a r s
80 A n n u A l R e p o R t 2 0 0 6
Guest Scientists and Seminars

G a s t w i s s e n s c h a F t l e r u n d s e M i n a r e – G u e s t s c i e n t i s t s a n d s e M i n a r s
Gastwissenschaftler / Guest scientists
Gastwissenschaftler Institution Forschungsgebiet
Guest scientists institution research area
1. Mr. e. o. Ates Istanbul technical university, turkey process technology
2. prof. M. Bartel Aalen university of Applied Sciences, Circuit Design
Germany
3. prof. M. Bäumler university of Bremen, Germany Materials Research
4. Dr. M. Grudanov Genesis ltd., Kiev, ukraine System Design
5. Dr. p. Hartogh Max planck Institute for Solar System System Design
Research, lindau, Germany
6. Mr. A. Hudyryev national technical university process technology
of ukraine, Kiev, ukraine
7. Dr. K. Maharatna university of Bristol, uK System Design
8. prof. J. Murota tohoku university, Sendai, Japan process technology
9. Mr. A. Schäfer university of Bremen, Germany Materials Research
10. prof. V. e. Stikanov national technical university Circuit Design
of ukraine, Kiev, ukraine
11. prof. Ch. teichert university of leoben, Austria Materials Research
12. prof. J. Wollschläger university of osnabrück, Germany Materials Research
13. Dr. D. Zheng Kotura Inc., Monterey park, uSA process technology
A n n u A l R e p o R t 2 0 0 6
8

G a s t w i s s e n s c h a F t l e r u n d s e M i n a r e – G u e s t s c i e n t i s t s a n d s e M i n a r s
Seminare / seminars
Vortragender Institution Thema
presenter institution topic
1. Dr. K. Bach X-FAB Semiconductor Foundry “SoI CMoS technologies for
AG, erfurt, Germany Higher Voltages“
2. prof. M. Böhm university of Siegen, Germany “technologies and Components for a
Monolithic Integrated Chemical lab
on a Microchip”
3. Mr. H. Campanella Centro nacional de Micro- “thin-film piezoelectric Resonators (FBAR)
electrónica - Instituto de for High-frequency Applications at CnM”
Microelectrónica de Barcelona,
Spain
4. Mr. A. Chakravorty technical university of Dresden, “A perspective of Bipolar transistor Compact
Germany Modeling with HICuM”
5. prof. R. Fornari Institute of Crystal Growth, Berlin, “Growth of Ferroelectric layers by liquid
Germany Injection MoCVD”
6. prof. u. Gösele Max planck Institute of Micro- “Silicon – new Areas of Application“
structure physics, Halle, Germany
7. Dr. p. Hartogh Max planck Institute for Solar ”Solar System Research by passive
System Research, lindau, Germany Microwave Remote Sensing“
8. Dr. M. Frank IBM, t.J. Watson Research Center, ”oxide-semiconductor Interfaces:
Yorktown Hights, uSA High-k Gate Dielectrics on Si, Ge, and GaAs“
9. prof. e. Kasper university of Stuttgart, Germany “Fast IR-sensitive Ge-Detectors on Si“
82 A n n u A l R e p o R t 2 0 0 6

G a s t w i s s e n s c h a F t l e r u n d s e M i n a r e – G u e s t s c i e n t i s t s a n d s e M i n a r s
Vortragender Institution Thema
presenter institution topic
10. prof. p. Kücher Fraunhofer Center nanoelectronic ”nanoelectronics Beyond Atomic Scaling –
technologies, Dresden, Germany How to Integrate Research into
Manufacturing“
11. prof. H. lichte technical university of Dresden, ”electron Microscopy and electron
Germany Holography for the Investigation of
nano-structures“
12. prof. S. Mantl Research Centre of Jülich, ”new Materials and Concepts for
Germany nano-MoSFets“
13. Dr. M. Mertig technical university of Dresden, ”Bio-nanotechnology
Germany (nanowires and networks)“
14. prof. J. Reif Brandenburg technical university, ”laser-Ablation-Initiated Self-organized
Cottbus, Germany nanostructures on Silicon Surface“
15. Mr. R. Richter Max planck Institute of physics, ”Silicon Radiation Detectors for X-ray
Munich, Germany Astronomy and High-energy physics”
16. prof. H. Strunk Friedrich Alexander university ”Stress Relaxation in Semiconductor
of erlangen-nuremberg, Germany Heterostructures“
17. prof. Ch. teichert university of leoben, Austria ”Self-organization of Semiconductor
nanostructures“
18. prof. e. Weber Fraunhofer Institute for Solar ”the Future of Silicon-based
energy Systems, Freiburg, Germany photovoltaics“
A n n u A l R e p o R t 2 0 0 6
8

8 A n n u A l R e p o R t 2 0 0 6
p u b l i K a t i o n e n – p u b l i c a t i o n s
Publications

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
A Wireless Communication Platform for Long-Term Health Monitoring
Daniel Dietterle, Jean-Pierre Ebert, Gerald Wagenknecht, and Rolf Kraemer
IHP microelectronics GmbH, Wireless Communication Systems, PO Box 1466,
15204 Frankfurt (Oder), Germany
{dietterle, ebert, wagenknecht, kraemer}@ihp-microelectronics.com
Abstract
Recent advances in wireless communication technology
have opened the way for long-term health monitoring applications.
In this paper, we introduce the BASUMA project,
which will develop novel biomedical sensors and a wireless
communication platform that provides connectivity among
these sensors. This enables new, intelligent medical applications.
The design and implementation of the wireless medium
access control (MAC) protocol is the major focus of
this paper. We describe our work-in-progress on hardware/software
co-design, in particular, our co-simulation
framework for profiling and performance estimation.
1. Introduction
The application of sensor networks in health care has
attracted much research work ( [6], [7]) in recent years.
Advances in system-on-chip (SoC) design and wireless
communication technology enable the development of tiny,
battery-powered sensor nodes that can be worn on the human
body. Wireless communication among the sensors and
to external medical devices allow patients to move more
freely in a hospital environment or even return to their
homes while their health is being monitored.
This can lead to cost savings due to shorter stays in a
hospital and to an increased quality of life. Furthermore,
long-term continuous health monitoring for chronically ill
patients or patients belonging to a risk group helps to diagnose
symptoms of a disease much earlier than at regular or
emergency visits of a doctor.
Several technological challenges have to be faced before
a working health monitoring system can be deployed. One
aspect concerns the development of miniaturized biomedical
sensors that are battery-powered and still provide sufficient
accuracy. Moreover, new algorithms for diagnosing
the patient’s health state based on possibly inaccurate, however
continuous sensor measurements and combining mea-
proc. ubiCare‘06, 474 (2006)
surements from different sensors have to be designed and
validated in practice. Reliability of the system is another
major concern as it must operate correctly without human
intervention for several weeks or months under any circumstances.
The long operating times without replacing batteries
requires an efficient system and the application of effective
power management strategies.
These challenges are addressed by the BASUMA (Body
Area System for Ubiquitous Multimedia Applications) research
project [12]. Within the scope of this interdisciplinary
project, novel biomedical sensors and medical algorithms
for the evaluation of sensor readings as well as
a generic wireless communication platform will be developed.
This paper focuses on the design and implementation
of the BASUMA wireless medium access control (MAC)
protocol for a body area network (BAN). The protocol implementation
needs to be reliable, fulfill the tight resource
constraints, and in particular consume very low power. Because
of its power saving mechanisms and reservationbased
channel access method we base our MAC protocol
on the IEEE 802.15.3 standard [1].
We have modeled the MAC protocol in the Specification
and Description Language (SDL) [2]. However, the timecritical
protocol functionality cannot be realized completely
in software, unless an extremely fast processor is used, leading
to unacceptably high power consumption. Therefore,
our approach is to partition the protocol functionality into
hardware and software.We use profiling of the system to decide
about the hardware/software partitioning and have developed
a co-simulation framework that allows connecting
an instruction set simulator with an SDL simulator. Hardware/software
co-design is not yet completed, therefore we
cannot report any results of this process.
The paper is organized as follows. In Sect. 2, we briefly
introduce the technical objectives of the BASUMA project.
After that, in Sect. 3, our design flow of the MAC protocol
development and results achieved so far are presented. In
Sect. 4, our co-simulation framework is described in detail.
Finally, in Sect. 5, we give a summary of the paper.
A n n u A l R e p o R t 2 0 0 6
85

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
2. Objectives of the BASUMA Project
BASUMA [12] (Body Area System for Ubiquitous Multimedia
Applications) is a research project started in 2004
that has the objective to develop a platform for wireless
communication around the human body. This platform
will consist of hardware and software components that are
specifically designed for small, low-power devices.
The capabilities of the BASUMA platform are to be
demonstrated with a medical application. A number of
battery-powered sensor nodes measuring various bioparameters,
such as heart rate, temperature, or ECG are attached
to the human body and form a wireless network. Additionally,
novel biomedical sensors, such as lactate or ROS
(reactive oxygen species) sensors, are developed within the
scope of the project. While being subject to imperfections
in the measuring environment and much less available energy
compared to stationary laboratory equipment, the sensors
need to be sufficiently sensitive to draw sound conclusions
about the state of health of the patient.
The body area (sensor) network forms the basis for longterm
health monitoring of chronically ill patients. The signals
measured by the sensor nodes are locally analyzed (preprocessed)
and evaluated within the node or network, and
communication with a remote medical center is only initiated
when necessary. An application scenario and the BA-
SUMA hardware architecture are shown in Fig. 1. All nodes
ECG
Lung
sound
Blood
pressure
Accelerometer
86 A n n u A l R e p o R t 2 0 0 6
BASUMA wireless sensor node Sensor
LEON2
Processor
Digital
Baseband
Memory
Body Area Network
(BAN)
Input /
Output
UWB
Frontend
Figure 1. Body area network and BASUMA
hardware architecture
in the BAN are in communication range of each other, hence
multi-hop communication is not required. We investigate
ultra-wide band (UWB) technology as the means of communication.
We assume the IEEE 802.15.3 MAC protocol
[1] as very suitable for medical applications due to its offered
functionality such as reserved time slots, power management,
security features, and network coordinator han-
dover. We have reduced the complexity of the protocol by
omitting not required functions.
Our MAC protocol design flow including hardware/software
co-design is described in more detail in the
following sections. It can be applied not only to communication
protocol implementation, but to any embedded systems
application development as it puts special emphasis on
reliability and efficiency.
3. MAC Protocol Design and Implementation
The starting point of our design flow was the IEEE
802.15.3 MAC protocol specification [1]. We have modeled
the MAC protocol in the Specification and Description
Language (SDL) [2]. SDL is a formal language that
allows systems to be modeled, simulated, verified, and implemented.
It is a popular language for protocol modeling
(cf. [14], [15]). Telelogic TAU SDL Suite [3] is a commercially
available SDL tool that we are using for our research
work. SDL implementations derived by that tool consist
of automatically generated C code and a run-time environment.
By extensively simulating the model we could verify
the correct functionality of our model.
The next step was to target the model to the real-time
operating system (RTOS) Reflex. For this purpose, we developed
a so-called Tight Integration model for Reflex. This
replaces the SDL run-time environment with a tailored, very
efficient RTOS integration layer.
Some of the MAC protocol functionality underlies tight
timing constraints, for instance acknowledgment frame
transmission has to start exactly 10 microseconds after the
end of a received frame. This cannot be achieved with a
pure software implementation as it would require a processor
clocked at a very high frequency leading to high
power consumption. Therefore, some protocol functions
need to be realized in hardware. To find a reasonable hardware/software
partitioning, we apply profiling of the software
model. The functionality that has been mapped to the
hardware partition will then be designed using the hardware
description language VHDL. Finally, software and hardware
are integrated in a test system.
Our design flow is further explained in the following
paragraphs.
3.1. Protocol Modeling in SDL
The MAC protocol was modeled in SDL and simulated
using Telelogic TAU SDL Suite. The SDL description of
system behavior is based on communicating extended finite
state machines (CEFSM) that are executed concurrently.
State machines are represented by SDL processes. Processes
communicate with each other and the system environment
by exchanging asynchronous signals that may

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
carry any number of parameters. SDL also provides timers
that can be configured to generate signals at defined points
in time. Each process in an SDL system contains a FIFO
(First-In-First-Out) input buffer into which the received signals
and timer events are queued.
In our model, the protocol functionality has been divided
into a number of SDL processes, similar to an objectoriented
design approach. Each process is responsible for a
well-defined functionality. For instance, there are processes
that are only needed for devices that are capable to act as
piconet coordinator (PNC). A more detailed description of
our SDL model can be found in [11].
It is possible to connect several instances of the MAC
protocol model to form a network that can be simulated. It
is also possible to formally verify the protocol, however we
used extensive simulation runs in order to validate correct
protocol behaviour. An SDL testbench drives different test
scenarios, for instance, starting and joining a piconet, or
asynchronous and isochronous data exchange.
3.2. Operating System Integration
The validated SDL model is the basis for the MAC protocol
implementation by an automatic transformation. The effort
of re-implementing the protocol in C/C++ would be too
high and error-prone compared to an optimization approach
where inefficient SDL concepts in the model are replaced
by equivalent functions with less overhead. Additionally,
the time to achieve a fully tested implementation is considerable
shortened. Here, instead of using an SDL run-time
environment, we tightly integrate the SDL model with the
underlying OS, in our case Reflex.
Reflex [9] is a tiny, event-flow oriented OS for
deeply embedded systems [8]. Although quite similar to
TinyOS [10] — the operating system most often used for
wireless sensor nodes — we believe it is better tailored
for our system because of its earliest-deadline-first process
scheduling strategy. While TinyOS tasks run to completion
before any other task is scheduled, time-critical tasks
(activities) in Reflex will interrupt lower-priority activities.
Such a behaviour is difficult to achieve in TinyOS. We have
ported Reflex for the LEON2 processor, which we selected
as the general-purpose processor for the BASUMA hardware
platform.
The required memory space for the operating system Reflex,
the integration layer, and a simple SDL system was
measured to be about 20 kbytes for a system targeted for
the LEON2 processor. Further details can be found in [13].
3.3. Hardware/Software Co-Design
The objective of the hardware/software co-design is to
partition the pure software system into hardware and soft-
ware. While being less flexible and more time-consuming
to design than software, hardware implementations can
achieve an order of 100 or 1000 higher processing efficiency.
Thus, by mapping time-critical tasks to hardware, it
is possible to clock the system at a moderate (10-50 MHz)
frequency, thereby minimizing the energy consumption.
To identify bottlenecks in the pure software implementation
and to estimate the required clock frequency to meet
all timing constraints, we perform a profiling of the software.
For that purpose, the software is simulated using the
LEON2 instruction set simulator (ISS) TSIM [4]. TSIM
allows profiling of individual functions. This way, we can
identify functions that are most often called or that consume
most of the processing time.
In order to see whether the protocol implementation
meets its timing requirements, we couple the ISS with the
SDL simulator that simulates a body area network on an
abstract time basis. Only the ISS consumes real time when
executing instructions while, in the SDL simulation, time
advances only when SDL timers expire. Both simulators
are synchronized, so that there is a common time basis and
the correct order of events is ensured. Our co-simulation approach
is presented in the following Sect. 4 in more detail
and shown schematically in Fig. 2.
Abstract
protocol
model
SDL simulator
Abstract
protocol
model
Wireless link model
Instruction set
simulator
Protocol
implement.
model
Figure 2. Co-simulation framework
3.4. Hardware Accelerator Design
The protocol functionality that has been mapped to hardware
in the previous step will be designed in VHDL. As we
are targeting system-on-chip (SoC) implementations, this
protocol accelerator becomes a block of our SoC hardware
platform, attached to the on-chip AMBA high performance
bus (AHB).
Additionally, the protocol accelerator has got an interface
to the physical layer implementation, such that the payload
of received and transmitted frames passes through the
accelerator and can be processed (e.g., by CRC and AES
algorithms) on the fly. When the hardware accelerator is
designed to be a bus master, it can access the RAM to store
or read frame data independently of the processor.
A n n u A l R e p o R t 2 0 0 6
87

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
The use of hardware accelerators as an addition to a
general-purpose processor, which handles all non-timecritical
protocol functionality, has been reported previously
in the literature (cf. [16], [17]) for wireless MAC protocol
implementations. Our hardware platform around
the LEON2 processor including the protocol accelerator is
shown in Fig. 3.
LEON2
proc.
AHB
Controller
Protocol
Accelerator
Memory
Controller
PROM
Memory bus
88 A n n u A l R e p o R t 2 0 0 6
I/O port
Baseband
Processing
IrqCtrl Timers
SRAM
UARTS
APB
RF Frontend
AHB
AHB/APB
Bridge
Figure 3. Block diagram of the BASUMA hardware
platform
3.5. Integration and Test
The final step in the design flow is the integration of the
hardware and software implementations and a test of the
complete system. We are planning to fabricate the wireless
communication platform as a single chip to minimize the
overall power consumption. However, before we tape out
the first SoC, we will test the complete digital system on
an FPGA board and connect it to an external RF frontend
board. The GR-CPCI-XC2V development board [5] from
Pender Electronic Design is well suited for this purpose.
4. Co-Simulation Approach
In this section, we will describe our co-simulation framework
that allows us to join together the Telelogic TAU SDL
simulator with the LEON2 instruction set simulator TSIM
[4]. An application of this co-simulation approach is shown
in Fig. 2.
The SDL simulation as well as the TSIM simulation
both have their own simulation time. In order to guarantee
semantically correct co-simulation runs, both simulations
must be synchronized. In the case of the ISS, time
advances at each processed instruction, while our (abstract)
SDL simulation does not consume time when transitions are
simulated. Only when there are no more active transitions,
the simulation time can advance to the next scheduled SDL
timer or external event.
In our framework, the co-simulation is controlled by the
SDL simulator. The SDL simulator processes transitions in
the SDL model and queries the environment for input signals
by calling the function xInEnv(). It can also output
signals to the environment through the function xOutEnv().
Together with the functions xInitEnv() and xCloseEnv() this
is the interface that Telelogic provides to interact with external
software components from the SDL simulator (Fig. 4).
SDL simulator TSIM library
SDL
model
xInitEnv()
xCloseEnv()
xInEnv()
xOutEnv()
Environment
tsim_init()
tsim_exit()
tsim_cmd()
I/O module
get_signal()
put_signal()
Part of the co−simulation framework
write mem
read mem
Figure 4. Components of the co-simulation
framework
At simulation start, the xInitEnv() function is called by
the SDL simulator. From this function, the ISS is initialized
and the application to be simulated by it is loaded. The
SDL simulator then simulates all active transitions at timestamp
0. When there are no more transitions, it calls the
xInEnv() function to check whether there are external signals
as inputs for the SDL model.
As a parameter of the xInEnv() function, the timestamp
of the next SDL timer that is going to expire is passed. Since
there are no active transitions and no other sources of signals
that could trigger a transition before the indicated timestamp,
it is safe to advance TSIM until it reaches this point
in time in its simulation. The call to continue TSIM is made
from within xInEnv().
When the external (i.e. TSIM simulated) system sends
a signal to the SDL system during that simulation, TSIM
is stopped immediately and control resumes in the xInEnv()
function. Here, the current TSIM simulation time is read
and the abstract SDL simulation time is advanced to reflect
the same point in time. The signal sent from the external
system is input into the SDL model — this is the purpose of
calling the xInEnv() function by the SDL simulator.
When all active transitions have been simulated,
xInEnv() is called again. Consequently, the ISS will be
resumed. With this approach, the SDL simulation time
cannnot advance ahead of the time of the instruction set simulator,
which might lead to a signal being sent from the ISS
to the SDL simulation too late.

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
It is also possible that signals are sent to the TSIM system
from the abstract SDL simulation. For that purpose, a
signal queue has been implemented that stores these signals
and can be read from the application simulated in the ISS.
Whenever a signal is written into that queue, an interrupt
request is created so that the application — after it has been
resumed from xInEnv() — will first read these signals and
process them, in turn.
5. Conclusions
In this paper, we have presented our design flow for a
body area network communication platform and put special
focus on the MAC protocol hardware/software co-design.
The MAC protocol has been modeled in SDL. We are using
the CAdvanced code generator from the Telelogic TAU
SDL Suite for an automatic transformation of the model. A
Tight Integration model targeting the operating system Reflex
has been developed.
We have demonstrated the feasibility of our approach for
resource-constrained embedded systems such as wireless
sensor nodes enabling SDL-based software development for
this class of devices. This could lead to verified and reliable
systems that can be used for long-term, unsupervised applications.
The use of hardware accelerators that take over timecritical
and processing-intensive tasks from the processor is
intended. This way, the processor can be clocked at a lower
frequency and the power consumption is decreased. A cosimulation
framework joining an SDL simulation with an
instruction set simulator has been presented in this paper.
This co-simulation framework will help us to profile our
implementation model.
6. Acknowledgments
This work was partly funded by the German federal ministry
of economics and labour (BMWA) under grant no. 01
MT 306.
References
[1] IEEE Standard 802, ”Part 15.3: Wireless Medium Access
Control (MAC) and Physical Layer (PHY) Specifications for
High Rate Wireless Personal Area Networks,” 2003.
[2] ITU-T, ”ITU-T Recommendation Z.100. SDL: Specification
and Description Language,” 1999.
[3] Telelogic AB. (2004). Telelogic Tau SDL Suite. [Online].
Available: http://www.telelogic.com/products/tau/sdl
[4] Gaisler Research AB. (2005). TSIM Simulator User’s Manual.
[Online]. Available: http://www.gaisler.com/doc/tsim-
1.3.3.pdf
[5] Pender Electronic Design GmbH. (2005). GR-CPCI-
XC2V Development Board User Manual. [Online].
Available: http://www.pender.ch/docs/GR-CPCI-
XC2V user manual.pdf
[6] E. Jovanov et al. ”A wireless body area network of intelligent
motion sensors for computer assisted physical rehabilitation,”
in Journal of Neuroengineering and Rehabilitation,
2(1):6, 2005
[7] R. Bults et al. ”Body Area Networks for Ambulant Patient
Monitoring Over Next Generation Public Wireless Networks,”
in Proc. 3rd IST Mobile and Wireless Communications
Summit, 2004
[8] K. Walther et al. ”Generic Trigger Variables and Event Flow
Wrappers in Reflex,” in ECOOP — Workshop on Programming
Languages and Operating Systems, 2004
[9] J. Nolte. (2005). Reflex - Realtime Event FLow EXecutive.
[Online]. Available: http://www-bs.informatik.tucottbus.de/38.html?&L=2
[10] J. Hill et al. ”System Architecture Directions for Networked
Sensors,” in Architectural Support for Programming Languages
and Operating Systems, 2000, pp. 93–104
[11] D. Dietterle et al. ”High-Level Behavioral SDL Model for
the IEEE 802.15.3 MAC Protocol,” in Proc. of the 2nd International
Conference on Wired/Wireless Internet Communications
(WWIC), P. Langendörfer et al. (eds). Lecture Notes
in Computer Science, Vol. 2957. Springer-Verlag, Berlin
Heidelberg New York, 2004, pp. 165–176
[12] (2005). BASUMA - Body Area System for Ubiquitous
Multimedia Applications. [Online]. Available:
http://www.basuma.de
[13] G. Wagenknecht et al. ”Transforming Protocol Specifications
for Wireless Sensor Networks into Efficient Embedded
System Implementations,” submitted to the Third European
Workshop on Wireless Sensor Networks (EWSN 2006).
[14] M. Hännikäinen et al. ”Using SDL for Implementing a
Wireless Medium Access Control Protocol,” in IEEE International
Symposium on Multimedia Software Engineering
(MSE 2000), 2000, pp 229–236
[15] E. Grass et al. ”On the Single-Chip Implementation of a
Hiperlan/2 and IEEE 802.11a Capable Modem,” in IEEE
Personal Communications, vol. 8, no. 6, December 2001,
pp. 48–57
[16] M. Haroud et al. ”HW accelerated ultra wide band MAC
protocol using SDL and SystemC,” in Proc. IEEE Radio and
Wireless Conference (RAWCON’04), IEEE, 2004.
[17] D. Dietterle et al. ”Design of a Hardware Accelerator for a
Power-Optimized Implementation of the IEEE 802.11 MAC
Layer,” in Proc. 3rd Int. Conf. on Internet Computing, 2002,
pp. 225–230
A n n u A l R e p o R t 2 0 0 6
89

�
N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
proc. Ieee Workshop on Design and Diagnostics of electronic Circuits and Systems, 50 (2006)
90 A n n u A l R e p o R t 2 0 0 6
LEON�2:�General�Purpose�Processor�
for�a�Wireless�Engine�
�
Z.�Stamenković,�C.�Wolf,�G.�Schoof�and�J.�Gaisler*�
IHP�GmbH,�Frankfurt�(Oder),�Germany�
*Gaisler�Research,�Göteborg,�Sweden�
�
��������� �� ���� ������ ��������� �� ����� ������ ��� ����
������������������������������������������������������������
����� ��� ����� ��� �� �������� �������� ���������� ���� ���� �������� ���
����������������� ���������� ��������� �������� ���� ������������
����������������������������������������������������������������
��� ���� �������� ��������� ���� ��������� ������ ���� ������
������������ ��� ������������ ������� ��� �� ����� ������ �������
��������������������������������������������������������������������
�
I.� INTRODUCTION�
�
To� harness� complexity� and� decrease� time�to�market,� the�
system� design� process� is� developing,� mainly� going� from�
composing�designs�from�low�level�building�blocks�to�the�reuse�
of� very� complex� ones.� Advanced� System�on�Chip� (SoC)�
designs� are� usually� a� mix� of� externally� sourced� Intellectual�
Property� (IP)� blocks� and� in�house� developed� standard�
functions� and� application� specific� blocks.� We� focus� on�
wireless� communication� SoCs� that� strongly� request� both�
energy� saving� and� real�time� processing� solutions� to� enable�
flexible�designs�according�to�customer�demands.�
Our� final� goal� is� to� design� and� implement� a� wireless�
engine� [1]� that� needs� to� result� in� a� multiprocessor� on� a� chip�
including� a� general� purpose� processor,� custom� processors,�
memory,� standard� input/output� component,� digital� baseband�
and�analog�frontend�(Figure�1).�Several�projects�contribute�to�
accomplish�this�task.�
�
��������� ���������
������� �������
���� ����
������������
������������
������� �������
������ ������
�����������
�����������
���������
���������
��� ���
����� �����
������� �������
�
�
Figure�1:�Illustration�of�the�wireless�engine�approach�
�
Wireless� Broadband� Network�(WBN)� project�focuses�on�
highly� integrated� broadband� wireless� modems� according� to�
1-4244-0185-2/06/$20.00 c�2006 IEEE 50
IEEE802.11a� [2]� and� HiperLAN2� [3]� standards.� The� WBN�
team� developed� special� hardware/software� co�designs� that�
allow�the�realization�of�wireless�modems�with�full�throughput�
of�54Mb/s�including�the�MAC�layer�[4].�
Wireless� Internet� (WI)� project� develops� a� new� terminal�
oriented�TCP/IP�for�wireless�systems.�The�focus�is�to�raise�the�
energy�efficiency�by�using�a�vertical�optimization�[5].�
Mobile� Business� Engine� (MBE)� project� seeks� a� specific�
application�processor�for�the�wireless�engine�that�targets�highly�
efficient�encryption�operations�to�increase�wireless�privacy�and�
security�[6].�
Test� project� defines� a� new� Design�for�Testability� (DFT)�
approach�and�techniques�for�testing�multiprocessors�on�a�chip.�
To� support� these� projects,� we� develop� a� library� of�
reusable� ASIC� modules� (Modular� Processor� Library� [7])�
particularly�suitable�for�small,�low�power�devices,�as�required�
for� a� wireless� engine.� Powerful� embedded� processors� always�
play�the�crucial�role�in�such�a�library.�
In� starting� phase,� we� implemented� a� high�performance�
low�power�system�on�chip�based�on�LEON�2�processor�system�
[8]� as� a� general� purpose� processor� of� our� wireless� engine�
targeted� to� run� at� maximum� frequency� of� 80� MHz� and� with�
power�consumption�of�500�mW.�
The� paper� is� organized� as� follows.� The� system�
architecture� as� well� as� configuration� issues� are� presented� in�
Section� 2.� Integration� of� system� components� and� verification�
methodology� are� presented� in� Section� 3.� � The� conclusion� is�
given�in�Section�4.�
�
II.� SYSTEM�ARCHITECTURE�AND�CONFIGURATION�
�
LEON�2� processor� system� [8]� is� highly� configurable,�
allowing� the� user� to� customize� it� for� a� certain� application�
(selecting�different�cache�sizes,�multiplier�performance,�clock�
generation,�etc.)�or�target�technology.�It�is�available�as�an�open�
core� in� form� of� a� VHDL� model� describing� the� SPARC� V8�
processor� core,� system� bus� and� peripheral� components� [9].�
New� modules� can� easily� be� added� using� the� on�chip� system�
bus�[10].�A�graphical�configuration�tool�based�on�UNIX�kernel�
scripts� is� used� to� configure� the� system.� The� configuration�
environment�is�modified�to�include�the�IHP’s�0.25�m�CMOS�
CDR3�library�[11]�as�a�target�technology�library.�
The�architecture�of�the�configured�system�is�presented�in�
Figure� 2.� The� system� is� based� on� LEON�2� core� connected�
through� the� AMBA� bus� to� system� peripherals.� The� core�

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
integrates�both�instruction�and�data�cache�memories�(ICACHE�
and� DCACHE)� and� corresponding� cache� controllers.� It� also�
includes� an� interface� to� the� AMBA� advanced� high�
performance�bus�(AMBA�AHB)�and�its�controller.�A�memory�
controller�is�attached�to�the�AHB.�It�provides�an�interface�to�an�
external� flash� memory� and� static� RAMs.� The� slower� AMBA�
advanced�peripheral�bus�(AMBA�APB)�is�attached�to�the�AHB�
via� a� bridge.� Two� UARTs,� timer,� I/O� port� and� interrupt�
controller�are�connected�to�the�APB.�
�
��������
����
��������
�������
�����������
����
��
����
����
��������� ��������
����
������ �������
�������
�������
����
�����������
����� ������
�
�
Figure�2:�System�architecture�
�
��� �������������
LEON�2� integer� unit� implements� the� full� SPARC� V8�
standard,� including� all� multiply� and� divide� instructions.� It� is�
based� on� a� 5�stage� instruction� pipeline,� and� separate�
instruction� and� data� cache� interfaces.� The� number� of�register�
windows� is� configurable� within� the� limit� of� the� SPARC�
standard�(2���32).�We�have�decided�for�an�inferred�register�file�
(made�of�flip�flops)�of�8�register�windows.�
�
��� �����������������
Separate� instruction� and� data� caches� are� provided,� each�
configurable� to� 1� �� 64� KB,� with� 16�32� bytes� per� line.� Sub�
blocking� is� implemented� with� one� valid� bit� per� 32�bit� word.�
The� instruction� cache� uses� streaming� during� line�refill� to�
minimize� refill� latency.� The� data� cache� uses� write�through�
policy�and�implements�a�double�word�write�buffer.�Both�cache�
types� can� be� configured� as� a� direct�mapped� or� as� a� multi�set�
cache�with�associativity�of�2���4�implementing�either�the�least�
recently�used� or� the� random� replacement� policy� (a� 2�way�
associative� cache� implements� the� least�recently�replaced�
algorithm).��
We�have�implemented�a�configuration�consisting�of�an�8�
KB� instruction� cache� and� an� 8� KB� data� cache� with� 16� bytes�
per�line.�Each�of�the�caches�consists�of�a�tag�array�and�a�data�
array.�As�associativity�is�one,�the�tag�array�is�23�bit�wide�and�
the�data�array�is�32�bit�wide�in�both�caches.�
Two� embedded� SRAM� blocks� with� size� of� 8� KB� and� 2�
KB�are�used�for�implementation�of�the�tag�and�data�arrays.�The�
tag�arrays�have�been�implemented�of�a�block�of�2�KB�(the�size�
51
is�512�x�32).�Also,�the�data�arrays�have�been�implemented�of�a�
block�of�8�KB�(the�size�is�2048�x�32).�
�
��� ������������������
The�external�memory�bus�is�controlled�by�a�programmable�
memory�controller.�The�controller�acts�as�a�slave�on�the�AHB.�
The�function�of�the�memory�controller�is�programmed�through�
memory�configuration�registers�through�the�APB.�The�memory�
bus�provides�a�direct�interface�to�PROM,�memory�mapped�I/O�
devices� and� asynchronous� static� RAM� (SRAM).� Chip�select�
decoding�is�done�for�two�PROM�banks,�one�I/O�bank�and�five�
SRAM�banks.�Therefore,�there�are�eight�chip�select�signals�in�
the�memory�controller.�
�
��� �����������������������������
LEON�2� processor� system� includes� hardware� debug�
support� to� aid� software� debugging� on� target� hardware.� The�
support�is�provided�through�two�modules:�a�debug�support�unit�
(DSU)�and�a�debug�communication�link�(DCL).�The�DSU�can�
put�the�processor�in�debug�mode,�allowing�read/write�access�to�
all� processor� registers� and� cache� memories.� The� DSU� also�
contains� a� trace� buffer� which� stores� executed� instructions� or�
data�transfers�on�the�AMBA�AHB�bus.�For�simplicity�and�area�
saving,� we� have� not� included� this� buffer� in� the� implemented�
configuration.� The� debug� communications� link� implements� a�
simple� read/write� protocol� and� uses� standard� asynchronous�
UART�communications.�
The� debug� support� unit� is� used� to� control� the� processor�
debug�mode.�The�DSU�is�attached�to�the�AHB�bus�as�a�slave,�
occupying�a�2�MB�address�space.�Through�this�address�space,�
any�AHB�master�can�access�the�processor�registers.�The�DSU�
control� registers� can� be� accessed� at� any� time,� while� the�
processor�registers�and�caches�can�only�be�accessed�when�the�
processor� has� entered� debug� mode.� In� debug� mode,� the�
processor� pipeline� is� held� and� the� processor� is� controlled� by�
the�DSU.�
The� debug� communication� link� consists� of� a� dedicated�
UART� connected� to� the� AHB� bus� as� a� master.� A� simple�
communication� protocol� is� supported� to� transmit� access�
parameters� and� data.� A� link� command� consists� of� a� control�
byte,� followed� by� a� 32�bit� address� and� optional� write� data.�
Through�the�communication�link,�a�read�or�write�transfer�can�
be�generated�to�any�address�on�the�AHB�bus.�
�
��� �������������������
Two�on�chip�buses�are�provided:�AMBA�AHB�and�APB.�
The� APB�is�used�to� access�peripherals�and�on�chip�registers,�
while�the�AHB�is�used�for�high�speed�data�transfers.�The�full�
AHB/APB�standard�is�implemented.��
The� processor� is� connected� to� the� AHB� through� the�
instruction� and� data� cache� controllers.� Access� conflicts�
between� the� two� cache� controllers� are� resolved� locally.� The�
processor� will� perform� burst� transfers� to� fetch� instruction�
cache� lines� or� reading/writing� data� as� results� of� double�
load/store� instructions.� Byte,� half�word� and� word� load/store�
instructions� will� perform� single� (non�sequential)� accesses.�
A n n u A l R e p o R t 2 0 0 6
91

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
Locked� transfers� are� only� performed� on� LDST� and� SWAP�
instructions.� Double� load/store� transfers� are� however� also�
guaranteed�to�be�atomic�since� the�arbiter�will�not�re�arbitrate�
the�bus�during�burst�transfers.�
AHB� is� designed� for� high�performance,� high�clock�
frequency� system� modules.� It� acts� as� a� high�performance�
system� backbone� bus.� This� bus� supports� the� efficient�
connection� of� processors,� on�chip� memories� and� off�chip�
external� memory� interfaces� with� low�power� peripheral�
functions.� LEON�2� uses� the� AMBA�2.0� AHB� to� connect� the�
processor�cache�controllers�to�the�memory�controller�and�other�
high�speed� units.� In� our� configuration,� two� masters� are�
attached�onto�the�bus:�the�processor�and�the�UART�of�debug�
communication� link,� and� three� slaves� are� provided:� the�
memory�controller,�the�debug�support�unit�and�the�AHB/APB�
bridge.�
AHB/APB�bridge�acts�as�the�only�master�on�the�APB.�All�
communication�between�masters�on�the�AHB�and�slaves�on�the�
APB� pass� through� this� bridge.� The� APB� is� optimized� for�
minimal�power�consumption�and�reduced�interface�complexity�
to�support�peripheral�functions.�It�is�configured�to�connect�five�
slaves:� interrupt� controller,� timer,� two� UARTs,� and� parallel�
I/O�port.�
�
��� ���������������������
The�interrupt�controller�is�used�to�prioritize�and�propagate�
interrupt� requests� from� internal� or� external� devices� to� the�
integer�unit.�In�total�15�interrupts�are�handled,�divided�on�two�
priority�levels.�
�
��� �����������
The� timer� unit� implements� two� 24�bit� timers,� one� 24�bit�
watchdog�and�one�10�bit�shared�prescaler.�We�do�not�use�the�
watchdog.�
�
��� ������
Two�identical�UARTs�are�used�for�serial�communications.�
The�UARTs�support�data�frames�with�8�data�bits,�one�optional�
parity� bit� and� one� stop� bit.� To� generate� the� bit�rate,� each�
UART� has� a� programmable� 12�bits� clock� divider.� Hardware�
flow�control� is� supported� through� the� RTSN/CTSN� hand�
shake�signals.�
�
��� ������������������
A� partially� bit�wise�programmable� 32�bit� I/O� port� is�
provided�on�the�chip.�The�port�is�split�in�two�parts���the�lower�
16�bits�are�accessible�via�the�PIO[15:0]�signal�while�the�upper�
16�bits�uses�DATA[15:0]�and�can�only�be�used�when�all�areas�
(ROM,�RAM�and�I/O)�of�the�memory�bus�are�in�8��or�16�bit�
mode.�We�have�used�the�lower�16�bits�of�the�I/O�port�that�can�
be�individually�programmed�as�an�output�or�input.�
�
��� �����������������������
Since� LEON�2� processor� system� is� synthesized� from� an�
extensively� configurable� VHDL� model,� a� configuration�
register� (read�only)� is� used� to� indicate� which� options� were�
92 A n n u A l R e p o R t 2 0 0 6
52
enabled� during� synthesis.� For� each� option� present,� the�
corresponding�register�bit�is�hardwired�to�‘1’.�
�
��� ��������������������
The� processor� can� be� powered�down� by� writing� an�
arbitrary�value�to�the�power�down�register.�Power�down�mode�
will�be�entered�on�the�next�load�or�store�instruction.�To�enter�
the�power�down�mode�immediately,�a�store�to�the�power�down�
register� should� be� performed� followed� by� a� ‘dummy’� load.�
During�power�down�mode,�the�integer�unit�will�effectively�be�
halted.� The� power�down� mode� will� be� terminated� (and� the�
integer� unit� re�enabled)� when� an� unmasked� interrupt� with�
higher�level�than�the�current�processor�interrupt�level�becomes�
pending.� All� other� functions� and� peripherals� operate� as�
nominal�during�the�power�down�mode.�
�
III.� SYSTEM�IMPLEMENTATION�AND�VERIFICATION�
�
For�system�implementation�and�verification,�we�have�used�
the� original� simulation� and� synthesis� scripts� [9]� having�
provided� necessary� modifications.� First,� modifications� have�
been� done� to� incorporate� custom� SRAM� Verilog� simulation�
models�into�the�original�VHDL�processor�model.�
�
��� ����������
The� system� is� fully� synthesizable� with� most� synthesis�
tools.�After�the�configured�processor�system�including�SRAM�
models� had� been� verified,� we� have� modified� the� synthesis�
scripts� to� map� the� design� into� the� target� library.� The� design�
with� directly� instantiated� SRAM� blocks� and� pads� has� been�
synthesized�for�a�target�frequency�of�80�MHz�using�Synopsys�
Design�Compiler� [12].�An�SDF�(Standard�Delay�Format)�file�
of�the�synthesized�gate�level�netlist�has�been�generated�too.�
�
��� �������������
A� generic� testbench� is� provided� for� generation� of� a� few�
testbench�configurations:�FUNC�testbench�performing�a�quick�
check� of� most� on�chip� functions,� MEM� testbench� testing� all�
on�chip�memory�with�patterns�of�0x55�and�0xAA,�and�FULL�
testbench� combining�memory�and�functional� tests,�suitable�to�
generate�test�vectors�for�manufacturing�testing�[9].�Numerous�
simulations�using�these�testbenches�have�been�carried�out�after�
synthesis�to�prove�the�correct�functionality�of�the�design�gate�
level� netlist.� All� the� simulations� without� and� with� the�
corresponding� SDF� file� have� been� done� using� ModelSim�
Simulator� [13].� The� same� simulations� (using� the� original�
testbenches� and� self�made� assembler� program)� are� used� for�
verification�of�the�netlist�of�the�generated�layout.�
�
��� �������
After� functionality� of� the� synthesized� netlist� had� been�
verified,� we� have� created� a� floorplan� using� Cadence� First�
Encounter� [14].� In� floorplanning� phase,� the� memory� blocks�
have� been� placed� as� hard� macros.� Design� layout� has� been�
generated� using� a� standard� sequence� of�the�back�end� process�
steps:� power� planning,� placement,� clock� tree� generation,�

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
routing�and�verification�of�geometry.�The�processor�system�is�
fabricated� in� the� IHP’s� 0.25�m� CMOS� technology.� The� chip�
photo�is�shown�in�Figure�3.�Geometrical�and�electrical�features�
of�the�chip�are�summarized�in�TABLE�1.�The�data�show�high�
performance� and� low� power� of� the� implemented� system�on�
chip.�
�
TABLE�1�
CHIP�FEATURES�
Area� 27.2�mm 2�
Number�of�transistors� ~1.500.000�
Number�of�ports� 128�signal�+�16�power�
Maximum�frequency� 85�MHz�
Power�consumption� 530mW@2.5V,�60�MHz�
�
�
�
�
Figure�3:�Chip�photo�
�
��� ������������
The� design�is� highly�testable� as�in�addition�to�functional�
testing�of�the�complete�system�on�chip,�the�SRAM�blocks�have�
been�tested�by�integrated�BIST�and�the�rest�of�the�logic�by�a�
chain�of�scanable�flip�flops�(a�scan�chain).�
Each� SRAM� block� includes� the� BIST� logic,� and�
subsequently,� four� additional� ports:� an� enable� signal,� a� reset�
signal,�a�‘fail’�signal�(which�is�asserted�in�case�of�a�fault)�and�a�
‘done’� signal� (which� is� asserted�when�the�test�is� finished).�A�
Verilog� BIST� testbench� has� been� prepared� for� simulation�
purposes.�
�
�
�
�
�
�
�
�
�
�
53
For� the� inserted� scan�chain� (made� of� more� than� 11000�
scanable� flip�flops),� we� have� generated� more� than� 1300�
manufacturing�test�vectors�by�Synopsys�TetraMAX�Automatic�
Test�Pattern�Generator�in�form�of�a�WGL�file.�A�Verilog�DPV�
testbench� has� been� prepared� for� serial� simulation� of� all� scan�
data�too.��
All�the�tests�(FULL�test,�BIST�and�scan�test)�are�executed�
on�the�Agilent's�chip�tester�93000.�
�
IV.� CONCLUSION�
�
This� paper� presents� an� experience� in� implementation� of�
LEON�2� processor� system� configured� to� play� the� role� of� a�
general� purpose� processor� for� the� IHP’s�wireless�engine.�We�
have� demonstrated� the� performance� and� features� of� this�
processor� system� (fabricated� in� the� IHP’s� 0.25�m� CMOS�
technology)� that� meet� requirements� imposed� by� target�
application.� The� implemented� processor� system� has� been�
verified�and�become�a�reusable�module�of�our�modular�library.�
�
REFERENCES�
�
1.� IHP�–�Innovations�for�High�Performance�microelectronics,�
http://www.ihp�ffo.de/wireless/WLEindx.htm�
2.� http://grouper.ieee.org/groups/802/11�
3.� http://www.hiperlan2.com�
4.� E.�Grass,�K.�Tittelbach�Helmrich,�U.�Jagdhold,�A.�Troya,�G.�Lippert,�O.�
Krüger,� J.� Lehmann,� K.� Maharatna,� K.F.� Dombrowski,� N.� Fiebig,� R.�
Kraemer,� and� P.� Mähönen,� “On� the� single�chip� implementation� of� a�
Hiperlan/2� and� IEEE� 802.11a� capable� modem,”� ����� ���������
�����������������������,�vol.�8,�pp.�48�57,�2001.�
5.� M.�Methfessel,�K.F.�Dombrowski,�P.�Langendörfer,�H.�Frankenfeldt,�I.�
Babanskaja,�I.�Matthaei,�and�R.�Kraemer,�“Vertical�optimization�of�data�
transmission� for� mobile� wireless� terminals,”� ����� ���������
��������������,�vol.�9,�pp.�36�43,�2002.�
6.� P.� Langendörfer,� “Integration� moderner� Hand�
Implementierungstechniken� in� Codegeneratoren,”� ����������� ���
��������,�2001.�
7.� Z.�Stamenković,�G.�Panić,�U.�Jagdhold,�H.�Frankenfeldt,�K.�Tittelbach�
Helmrich,�G.�Schoof,�and�R.�Kraemer,�“Modular�Processor:�A�Flexible�
Library� of� ASIC� Modules,”� ������ ���� ������� ��������������
����������������������������������������������,�pp.�428�432,�2004.�
8.� LEON�2�Processor�User’s�Manual,�http://www.gaisler.com/�
9.� LEON�2�VHDL�Model,�http://www.gaisler.com/products/leon2�
10.� AMBA�On�Chip�Bus�Standard,�ARM�Inc.,�
http://www.arm.com/armtech/AMBA�
11.� IHP�–�Innovations�for�High�Performance�microelectronics,�
http://www.ihp�ffo.de/ihpoffer/OFFindx.htm�
12.� Synopsys�Inc.,�http://www.synopsys.com�
13.� Model�Technology,�http://www.model.com�
14.� Cadence�Design�Systems,�http://www.cadence.com�
A n n u A l R e p o R t 2 0 0 6
93

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
An Improved Highly-Linear Low-Power Down-Conversion
Micromixer for 77 GHz Automotive Radar in SiGe Technology
94 A n n u A l R e p o R t 2 0 0 6
Li Wang 1,2
, Rolf Kraemer 1,2
, and Johannes Borngraeber 1
1
IHP Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany,
2
Technical University of Brandenburg, 03013 Cottbus, Germany
Abstract — This paper proposes a method to improve the nonlinearity
of the differential RF signals, the noise figure and
conversion gain in the existing micromixer through inserting a
transistor that is connected in diode form in the mirrored RF
branch. These improvements are demonstrated by three
micromixers designed at different frequency bands. A 77 GHz
micromixer in 0.25 µm SiGe:C BiCMOS technology using the
proposed method is fabricated and measured. Additionally,
current injection technique is applied in the circuit to increase
gain and reduce power consumption. 13.4 dB gain, 18.4 dB NF
and 1.4 dBm OP1dB are achieved with 176 mW power
consumption at 4.5 V. To the authors’ knowledge, this is the first
reported 77 GHz micromixer.
Index Terms — Automotive radar, BiCMOS, Downconversion,
Gilbert mixers, micromixer, 77 GHz, SiGe.
I. INTRODUCTION
Up to now, most of the reported millimeter-wave radar
front-end were realized with Schottky diodes and
implemented in GaAs technologies for their excellent device
performance. However, the application of GaAs circuits in the
fields such as 77 GHz automotive radar is limited by the high
cost. With the advent of 200 GHz f T SiGe:C technology, it is
attractive to realize the circuits with lower cost and excellent
performance. The so far reported two active mixers in SiGe
technologies in mm-wave range such as V-band (50 to 75
GHz) and W-band (75 to 110 GHz) are a single-balanced (SB)
mixer at 60 GHz [1] and a double-balanced Gilbert (DBG)
mixer at 77 GHz [2]. However, single-ended double- balanced
(SEDB) micromixer in the mm-wave range has not yet been
reported.
In this paper, after a detailed analysis of the existing mixer
structures, we propose an improved micromixer structure,
which improves the RF asymmetry, conversion gain (CG) and
noise figure (NF) compared with other existing micromixer
topologies. The improvement is demonstrated by three designs
using this structure. A 77 GHz down-conversion micromixer
circuit using the proposed structure is fabricated in IHP’s lowcost
0.25 µm SiGe:C BiCMOS technology. To the authors’
knowledge, this is the first reported SiGe 77 GHz micromixer.
Compared with the previously published SiGe 77 GHz active
down-conversion mixer [2], measured results of the fabricated
chip demonstrate a 60% better linearity with 41% less power
consumption.
0-7803-9542-5/06/$20.00 ©2006 IEEE
proc. Internat. Microwave 1834 Symposium (2006)
II. ANALYSIS OF CURRENT MIXER STRUCTURES
The current structures of mixer are: SB mixer, DBG mixer,
and SEDB micromixer. SB mixer has the advantages such as
low power consumption, lower requirement for LO power,
good NF, no need of RF balun. However it is limited by the
following: low CG, limited linearity due to the V-I converter,
narrow dynamic range, more IM products, and large LO
leakage. In comparison with SB mixer, DBG mixer has the
double-balanced structure which overcomes the disadvantages
of SB mixer. However it requires higher LO power and either
a differential low noise amplifier (LNA) to provide differential
RF signals or a single-ended LNA with a single-ended to
differential converter. The differential LNA consumes double
power and chip area of the single-ended LNA. Additionally,
the single-ended LNA requests an active single-ended-todifferential
converter whose phase and amplitude unbalance
greatly worsen the linearity of the mixer at the mm-wave
range. Although RF LC balun also converts single-ended
signal to differential signals, it occupies a larger chip area and
can’t provide well-balanced differential signals. SEDB
micromixer has an inherent single-ended port for the RF
signal without using the RF balun, and provides balanced
signal paths for the LO and RF, thus overcomes the
disadvantages of the SB mixer. Furthermore, the advantages
of DBG are preserved in SEDB micromixer. Based on the
above consideration, we choose SEDB structure in our design.
So far, the SEDB mixer were reported only at very low
frequencies. In the next section, we propose a method to
reduce the residual non-linearity caused by asymmetry in RF
signal path and to improve the gain and noise figure compared
to the existing micromixers. The improvement is verified in
W-band.
III. IMPROVED MICROMIXER STRUCTURE
The circuit of mixer consists of a mixer core, an LO buffer,
and an IF buffer. Three existing micromixer structures
reported in [3], [5], and [6] are shown in Fig. 1 (a), (b), and
(c). The improved structure is depicted in Fig. 2. What
differentiates our proposed method from the existing methods
is the mirrored RF upper branch which is marked in a dashed
circle. In other reported micromixer structures shown in Fig.
1, Q6 is either connected in different ways or not used. We
propose to connect a transistor Q6 in a diode form as shown in

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
RF
Q5
Q7
R1
R2
R3
R4
Q6
Q10
Q8
Q11
R11
Vbias
Fig. 2. Circuit of 77 GHz micromixer core with single-ended RF and
differential LO and IF
Delta Gain (dB)
Quad
transistors
Fig. 2. The most important benefit of this way of connecting
Q6 is the better balancing of the amplitude and phase of the
differential RF signals, this is realized by providing a more
symmetric structure for RF signals at node A and B. Then this
results in the cancellation of the individual non-linearity of I1
and I3 and improves the performance of micromixer.
R6
R5
C3
RF
Q5
Q7
Quad
transistors
R1
R2
R3
R4
2
Q8
Q10
Q11
R11
Vbias
(a)
(b)
Fig. 1. Current existing structures of micromixer: (a) Structure in [3], (b) Structure in [5], (c) Structure in [6]
LO+
LO-
RF
4.0
3.0
2.0
1.0
0.0
-1.0
-2.0
-3.0
Vcc
R7 R8 C1 C2 R9 R10
I1
Q1 Q2 Q3 Q4
A
B
I2
Q5
Q7
R1
R2
R3
R4
Q6
I3
Q8
Q10
Q11
a b c
Structures of mixer
R11
R6
R5
C3
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
dG_a@70 GHz dG_b@77 GHz
dG_c@84 GHz dNF_a@70 GHz
dNF_b@77 GHz dNF_c@84 GHz
Fig. 3. Gain and NF comparison among the proposed mixer
structure and existing structures at different frequency bands
IF+
IF-
Vbias
Delta NF (dB)
1835
R6
R5
C3
RF
Q5
Q7
Quad
transistors
R1
R2
R3
To verify the improvement, three circuits were designed at
70 GHz, 77 GHz and 84 GHz, respectively. The gain and NF
between the proposed mixer structure and the existing
mircomixers are compared and illustrated in Fig. 3. We define
dG_x = G_new − G_x, and dNF_x = NF_new − NF_x, where
G_new (or NF_new) and G_x (or NF_x) are conversion gain
(or NF) of the mixer with the new structure and the structure
(x) in Fig. 1 respectively, x denotes a, b, and c. Our structure
reduces the NF compared to the other three structures and the
reduction is more noticeable at higher frequencies. The reason
is that the individual non-linearities of the two output currents
I1 and I3 are cancelled, thus the noise interference part is
removed. The improvement for gain is also positive compared
to structure (a) and (b) with the same reason. Compared to
structure (c), the gain is reduced by 0.09 dB, 0.51 dB, and 0.15
dB for 70 GHz, 77 GHz, and 84 GHz respectively. This is
because that in (c), the incidental inequality of VCE of Q8 helps
to recover some of the current gain in the mirror lost due to its
finite ac beta. Since the structure depicted in Fig. 1. (c) uses
no components in the mirrored RF upper branch, Q8 suffers
avalanche risk. This is particularly important for SiGe
technologies which have a low BVCEO. Since the BVCEO is 1.9
V in the 200 GHz fT SiGe technology, VCE of Q8 is on the
border of BVCEO. Therefore, structure (c) is not suitable for
low BVCEO technologies. In sum, our proposed structure
improves the linearity of the two differential RF signals and
thus increases the gain, reduces the NF without increasing the
complexity of the circuit and avoids the avalanche.
III. CIRCUIT DESIGN
R11
Vbias
The proposed micromixer structure is used in the design of
a 77 GHz mixer. Additionally, current injection [4] is realized
by using R 7 and R 10 to increase the gain without increasing the
tail current; thus, the gain can be improved by using larger
collector load with lower supply voltage. While the internal
circuit has a differential architecture, the LO and RF ports are
single-ended. The input matching for RF port is greatly
facilitated by feeding the single-ended RF signal to the small
resistor R1 which is connected to the emitter of Q5. This
further linearizes the mixer and matches the RF port to 50
R4
(c)
Q8
Q10
Q11
R6
R5
C3
A n n u A l R e p o R t 2 0 0 6
95

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
Ohm. Additionally, the matching still can be finely optimized
by the control voltage Vbias. The internal differential RF
signals are achieved by the current mirror Q 7 and Q 8 without
using RF balun and provides differential RF signals with
improved linearity. At the collector node, RF and LO signals
are filtered out by a Metal-Insulator-Metal (MIM) capacitor to
feed only the low frequency IF signals to the IF buffer.
50 Ohm
LO
Vcc
Fig. 4. Circuit diagram of LO buffer
The differential LO signals are provided by the LO buffer as
shown in Fig. 4. A 50 Ohm resistor and a transmission line are
used at the input to provide a good match to the LO input
probe. Additionally, the LO buffer provides constant gain for
the LO differential signals to provide sufficient power to drive
the mixer. AC coupling is used to remove the DC offset of the
differential LO signals. Furthermore, emitter followers behave
as low impedance interfaces to the mixer core. The circuit of
an IF buffer (not shown) is a one-stage differential amplifier
with emitter degeneration, and it is only used to provide a
matching circuit for the 50 Ohm measurement port without
influencing the linearity and gain of the mixer.
The circuits were fabricated in a SiGe:C HBT self-aligned
single-polysilicon technology with 0.25 µm minimum
lithographic emitter width and four Al metal layers described
in [7]. Collector emitter breakdown voltage BV CEO is 1.9 V.
The f T and f max are up to 200 GHz. The highly lossy substrate’s
resistance is 50 Ωcm.
IV. MEASUREMENT RESULTS AND DISCUSSIONS
The chip photograph is shown in Fig. 5. The chip area is 0.5
mm × 0.55 mm including pads, and 0.3 mm × 0.2 mm without
pads. RF and LO are fed from the opposite sides to improve
the isolation in layout. All the measurements were done on
wafer with mm-wave source module HP 83558A and
multiplier for W-band. The exact input power of LO and RF is
measured by Agilent W8486A W-band power sensor and HP
HP E4419B power meter. The noise figure (NF) was
measured by using the W-band noise source and Aeroflex
PN9000 Phase Noise Test System.
The mixer operates at a supply voltage of 4.5 V with a total
current consumption only 39 mA, and consumes 176 mW
power with 49.5 mW for the mixer core. With 2 dBm LO
96 A n n u A l R e p o R t 2 0 0 6
LO+
LO-
1836
3
Gain (dB)
Gnd Vcc Vb Gnd
Gnd
Gnd
Mixer
LO LO
B uffer
C ore
IF B uffer
R F
Gnd
Gnd
G nd IF+ IF- Gnd
Fig. 5. Chip photo of mixer with chip area of 0.5 × 0.55 mm 2
IF Output Power(dBm
20
15
10
-10
-15
5
0
-5
5
0
-5
-10
-15
-20
-25
-30
-35
-40
Freq_LO= 77 GHz
Power_LO=1 dBm.
Freq_RF=77.1 GHz
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0
RF Input Power (dBm)
Fig. 6. Measured IF power versus RF input power
Freq_IF=100 MHz
Power_LO=1 dBm.
versus LO frequency
versus RF frequency
-20
70 75 80 85 90
LO / RF Input Frequency (GHz)
Fig. 7. Measured conversion gain versus RF and LO input
frequency
power, a maximum gain of 13.4 dB at 77 GHz is measured.
Fig. 6 depicts the output power for an IF frequency of
100MHz versus the RF input power. The LO frequency and
power is 77 GHz and 1 dBm respectively. The mixer shows a
wide dynamic range with input 1 dB compression point of -12
dBm. In Fig. 7, the measured CG versus LO and RF input
frequency is shown for 100 MHz IF frequency and 1dBm LO
power. The measured CG versus RF frequency is larger than
10 dB at the center frequency of 77 and 84 GHz and peaks
also for LO frequency at 77 GHz. This demonstrates that good

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
Gain (dB)
15
12
9
6
3
Freq_LO= 77 GHz
Freq_RF=77.1 GHz
Power_RF=-27.7dBm
0
-15 -10 -5 0 5
LO Power ( dBm )
Fig. 8. Measured conversion gain versus LO input power
TABLE I
COMPARISON TO REPORTED 77 GHZ ACTIVE SIGE MIXER
Ref. Technology Gain
[2] 0.18µm
This
work
200GHz f T
0.25µm
200GHz f T
IF
P 1dB
(dB) (MHz) (dBm) (dB)
matching is achieved at both ports. Fig. 8 shows the linearity
of CG versus LO power. CG saturates at 2 dBm LO power.
For 77 GHz LO, CG is 12.6 dB and 13.4 dB gain for LO
power of 1 dBm and 2 dBm respectively. The signals emitting
to the substrate at such band and the highly lossy substrate
result in loss and medium isolation. The measured port
isolation of LO-RF and LO-IF is larger than 34 dB and 28 dB
respectively. 18.4 dB SSB NF is obtained by measuring the
output noise power density utilizing the Gain Method. The
measured output noise power density of the mixer and the
residual noise power density are –160 dBV 2
/Hz and –170
dBV 2 /Hz respectively. The data was obtained by repeating
each step several times with the similar curves.
So far, we have not found reports with measured IP3 result
near 77 GHz range or beyond. The practical problems prohibit
us from building a measurement setup. The mechanical
difficulties encountered during installing the required
equipment and apparatus: two 77 GHz RF sources, a W-band
coupler, a W- band LO source module, and four probes.
Another source (Agilent) using tricky mixing algorithm to
establish two-tone signals works for low frequencies only.
Since all the measured data, including 1 dB compression
point, CG, port matching agree with the simulation data very
well, we can safely use the simulated –2.5 dBm IP3 as
practical metric for mixer. Furthermore, the rule of thumb
states that the real IP3 is around 10 dB larger than the P1dB. That is, the real IP3 can be estimated as -12 dBm + 10 dB = -2
NF
Voltage Power Isolation FOM
(V)
(mW)
(dB)
22 500 -30 >14 -5 300 - -63.77
13.4 100 -12 18.4 4.5 176 >34/
>28
-60.86
1837
4
dBm. This IP3 estimate also well agrees with the simulated
IP3 of -2.5 dBm with only 0.5 dB estimation error. Therefore
we could say that -2.5 dBm IP3 is trustable. Table I shows a
comparison between the so far reported 77 GHz active SiGe
mixer. We choose the new definition of figure-of-merit
(FOM) to have a comprehensive comparison of mixer
performance and show the FOM MIX as an indication.
FOM MIX=(CG-NF)+(MIX LIN-NF)-MIX pwr, where the definitions
for each term can be found in [8]. 60% better linearity and
higher FOM MIX are achieved with 41% less power
consumption.
V. CONCLUSION
A 77 GHz SiGe micromixer with a proposed topology is
presented in 200 GHz SiGe:C technology. 13.4 dB maximum
gain and 18.4 dB NF are achieved with 2 dBm LO power. 1.4
dBm OP 1dB demonstrates the high linearity of the mixer with
176 mW power consumption at 4.5 V. Compared to other
existing structures of micromixers, we demonstrated that our
structure improves the gain and NF without increasing the
circuit complexity. To the authors’ knowledge, this is the first
reported micromixer at 77 GHz.
ACKNOWLEDGEMENT
The authors acknowledge the equipment support from Prof.
A. Thiede University of Paderborn, and Ferdinand-Braun-
Institut (FBI) in Berlin.
REFERENCES
[1] S. K. Reynolds, “A 60-GHz superheterodyne downconversion
mixer in silicon-germanium bipolar technology,” IEEE Journal
Solid-State Circuits, VOL. 39, NO. 11, Nov. 2004, pp. 2065-
2068.
[2] W. Perndl, H. Knapp, M. Wurzer, K. Aufinger, et al., “A lownoise
and high gain double-balanced mixer for 77 GHz
automotive radar front-ends in SiGe:C HBT technology,” IEEE
Radio Frequency Circuits Symposium, 2004, pp. 47-50.
[3] B. Gilbert, “The MICROMIXER: A highly linear variant of the
Gilbert mixer using a bisymmetric class-AB input stage,” IEEE
Journal Solid-State Circuits, VOL. 32, NO. 9, Sep. 1997, pp.
1412-1423.
[4] B. Razavi, “RF microelectronics,” (Prentice Hall. New York.
1998), Chap. 6
[5] C. Meng, T-Han. Wu, T-Hung. Wu, G-W. Huang, “A 5.2 GHz
16 dB CMFB Gilbert downconversion mixer using 0.35 µm
deep trench isolation SiGe BiMCOS technology,” IEEE MTT-S
International Microwave Symposium, 2003, pp.975-978.
[6] C. Y. Wang, S. S. Lu, C. C. Meng, and Y. S. Lin, “A SiGe
micromixer for 2.4/5.2/5.7-GHz multiband WLAN applications,”
IEEE Microwave and Optical Technology Letters Vol. 41, No.
5, Jun. 2004, pp. 343-346.
[7] B. Heinemann, et al.: "Novel collector design for high-speed
SiGe:C HBTs," IEEE IEDM Tech. Dig., 2002, pp. 775-778.
[8] J. P. Comeau, J. D. Cressler, J. Lee, A.J. Joseph,: "An 8.4-12.0
GHz down-conversion mixer implemented in SiGe HBT
technology” IEEE Topical Meeting on Silicon Monolithic
Integrated Circuits in RF systems, 2004, pp.13-16.
A n n u A l R e p o R t 2 0 0 6
97

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
�������������������������������������������������������������������
�����������������
98 A n n u A l R e p o R t 2 0 0 6
proc. european Microwave Integrated Circuits Conference, 198 (2006)
������������������������������������������
����������������������������������������������������������������
������������������������������
�������������������������������������������������������������
��� ������� ������� ������������ ���� ����������� ����� ��� ��� ���
��������������������������������������������������������������
��������� ��� ����� �� ������ ���� �� ��� ���� ����� ���� ���������
�����������������������������������������
������ ������ � �� � ��������� ����������� ��� �����
���������������� � ���������� ����������� ����������� ��������
������������������������
����������������
���� ������ ����������� ����� ������� ������� ��������� ����
������������ ��� ������������������� ��������� ���������������
���� ���������� ������������ ��� ���� �������� ������ ��� ������
����� ������ ������������� ������ ���� �������� ������������ ��� �����
��������������������������������������������������������������
���������������������������������������������������������������
������ ������������� ���� �������� ���� ����� ����������� ��� �����
������������� ������ �� ����� �������� ������������ ��� �����������
���������������������������������������������������������
����� ������������ ������������� ������ �� ������ �������
������������ ������� ������ ����� ���� ����������� ����� �����
����������� ����� � ������ ������� ������� ������������ �� ���
�������������������������������������������������������������
����� ���������� ���������� ���� �������������� ��������������
����� ��� �� ��������� ����������� �� ������ ��� ���� ����������
��������������������������������������������������������
����� ������ ��������� �� ��������� ���������� ��� �� ��������
������� ������� ������������ ��� ��������� ��� ����� �� ��������
�������������������������������������������������������������
��������������������������������������������������������������
���� ��� ����� ��� ������ ���������� ���� �������������������� ����
������ ������� ���� ������� ���� ��� ����� ��������� ��� ������ �����
������������ ���������� ������������ ������������� ����������
���� ����������� ���� ����� ��������� ��� ���� ������������ �������
������ ������������ ����� ���������� �������� �� ������ �������������
���������������������������������������������������������
������������ ������ ���� ��� ����� ��������� ����� ���� ���������
��������������������������������������������������������������������
������ ���� �������� ������ ����� ������� ������� ���������� ��������
��������������������������������������������������������������
���� �� ������������� ���������� ��� ���� ����������������������������
������������������������������������������������������������������
����������������
�
���������������������������
����������������������������������������������������������
���������������������������������������������������������
���������������������������������������������������������������
����� ���� ���� ������������ ���� ���� ��������� ��� ������ ���
�������������������������������������������������������������
���������������������������������������������������������
��������������������������������������������������������������
�������������������������������������������������������������
��� ���������� ����� ���� ������ ���������� ��� ��� ����� ����� ����
����������������������������������������������������������������
�����������������������������������������������������������
������� ���� ������� ������������� ����� ��� �����������
������������ ��� ��� ������ ��� �� �������������� ������������ ��
���������������� ������������� ����� ������ ��� ��� ������������
���������������������������������������������������������������
���������������������������������������������������������������
��� ������ ��� ����� ���� ��������� ����� ������� ��� ����������
����������������������������������������������������������
����������������������������������������������������������
��������������������������������������������������������������
��������������������������
�
����������������������������������������������������������

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
�������
���������������������������������
���������������������������������������������������������������
�������������������������������������������������������������
���������������������������������������������������������������
��������� ����� ���� ���� ���������� �������� ����������� ��� � � ����
����� ������ ��� ���� ������ ������ ��� ��� ����� ������ ����� �����
���������� ���� ����� ���� ������ ��������� ����������� ����
��������������������������������������������������� ���������
���������������������������������������������������������������
����������������� ��������� ���������� ���� ����� ��� ������ ����
������� ��� �������� ���� ���������� ������ ����� ������ ����� ����
�������������������������������������������������������������
����������� ������ ��� ����� ����� ��� ������ ���� ������� ���������
����������� ���� ������ ���� ������� ���� �������� ��� ������
������������� ����������� ���� ���� ������������� ���� ������������
��������� ���� ���������� �������� ���������� ���������� ����� ����
������ ������ ��� ���� ����� ������ ���� �� ����� ������ ������� ���� �����
�����������������������������������������������������������������
������������� ����� ��� �� ���������� ����� ��� ����� ����� ������
�����������������������������������������������������������������
��� ���� ��������� ��� ����� ������������� ������ ���� ������������
������ ��� ����������� ��� ���� ������ ������� ����� ���� �������� ������
������ ��� ��� ���������� ����� ��� ������������� �������� ���� ��� ����
�������������������������������������������������������������
���������� ��� �������� �������� ��� ����� ���� ������������
������������������������������������������������������������
��������� ��� �� ������� ������ ��� ���� ���������� ���� ����
������������� ��� ������ ������ ���� ���� ��� �������������
������������ ������ ������� �������� ����� ������ ���� �������
�����������������������������������������������������������������
�����������������������������������������������������
�
���������������������������������������������������������
�������������������������������������������������������
��� ���� �������� ����� ��� ��� ��� ���� ���� ���������� ����
����������������������������������������������������������
���� �������� ���� ������ ������� ��� ���� ���� ���� ��� ���� ����� ���
�������������������������������������������������������������
���� ���� ������ ��� ��� ����� �� ���� �� �������� ���� �����
������������������������������������������������������������
��������
�
���������
�� �������� ����� ��� ����� ��� ���� ������ ������ ���� ���� ��������
���������������������������������������������������������������
���� ����������� ������ ����������� ���� ��� ���� �� ���� ���
����������� ���� ���� ������ ���� ��� ��������� ��� ����� ������� ����
��� ��������� ��� ���� ����������� ��� ��������� ���� ��� ���� ���
������ ���� �������� ��� ������ ������������� ����������� ��� �����
��������� ���� ��������� ��� ��������� �� ������� �����������������
���������� �������� ���� ��������� ���� ��� �������� ����������
������������������������������������������������������������
���� ��� ��������� ��� ��������� ��� �� ������ �������������� ���
����������� ���� ���� ������������ ���� ��� ��������� �������� ���
���� ��� ����� ��� �� ������������� ���������� ����������� ������ ���
����� ��� ������ ���� ��� ���������� ���������� �� ������� �������
�����������������������������������������������������������������
������� ���� �������� ������� ��� ���� ��������� ���� ��� ����� ���
������������ �������� ��� ���� ���� ������� ��� �������� ��
����������������
��� ���
�����������������������������������������������������
��������������������
��
��
��
���������������������
��������������������
�����������������
����������������
�
�� �� �� �� �� �� �� ��
������������������
����� ��� ��������� ���� ���������� ����������� ����� ����� ��� ���
�����������������������������������������������������������������
�
������� ������ ���� ������������ �������� ����� ���� ���� ������
���� ���� ������������ ��� ���� ���� ������� �� ������ ���
�����������������������������������������������������������
������������������������������������������������������������
�����������������������������������������������������������
��� ���������� ������ ��� ����������� ���� ��������������������
A n n u A l R e p o R t 2 0 0 6
99

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
��������������� ���� ������ ����� ������ �� ��� ���������������
������������������������������������������������������������
������ ���� ����� ������������ �������� ���� ���������� ������
������� ��� ��� ���� ������ ���� ����������� ���� ����������� ������
�����������������������������������������������������������������
���������
�������
�����������������������������������������������������������
������������������������������������������������������������
���� ����� ��������� ���������� ��� ���� ������ ������ ������ ��� ����
��������������������������������������������������������
������ ��� ���������� �������������������������������������������
����������������������������������������������������������������
�������������������
���� ���� ��������� �� ���� ����� �� ������������� �������� ��
��������������������������������������������������������������
������� ���������� ���� �������� ��������� ��� ����� ������������
����������������������������������������������������������������
����� ��� ����� ��� ����� ������������� ����������� ��������
�������������������������������������������������������������
���� ������ ������� ����������� ��� ��� ���������� �������� �������
�������� ���� ���������� ������ ������ ��� ��� ������������� ��������
�������������������������������������������������������
���� ���� ��� ������������ ������ �� ������������� ��������� ���
�����������������������������������������������������������������
��� ���� ���� ����� ������� ��� ������ ��� ���� ������ ������ ������ ���
����������� ������ ���������� �������� �������� ���� ������� ���
������������������������������������������������������������
��������������������������������������������������������������
�����������������������������������������������������������
���������������������������������������������������������������
������������������������������������������������������������
������������������������������������������������������������
����������������������������������������������������������������
����� ���������� ��� ����� �� ������ ������������ ���������
����������������������������������������������������������������
������������������������������������������������������������
������������������������������������������������������������
����� ������������� ������� �� ��������� ������� ���� ���� ����
�����������������������������������������������������������������
������������
�������������������������������������������������������
��������� ���� ���� ����� �� ��� ������� ������� ���� ���� ������
������������������������������������
�����������������������������������
100 A n n u A l R e p o R t 2 0 0 6
�����������������������������������
������������������������������������������������������������
�������� ���� ���� ���� ���� �������� ������� ���� ����� ����� ����
��������� ���� ���� ����������� ���� ������ ���� ��������������
�������������������������������������������������������������
������ ��� ����� �� �������� ��� ����������� ���� ���� �������� ���
����� ���� ���� ������� ����� �������������������������������
������ ���� ��������� ��� �� ��������� ������ ������ ������ ���� ����
���� ��� ��������� ��� �������� ������ ������ ���� ������ ������ ����
����� ��� ������� ���� ������ ��������� �������� ���� �����������
�������������������������������������������������������������
���� ���� ���� ������� ����� ���� ���������� ��� ���� ��� ��������
�����������������������������������������������������������
��� ������ ��� ��������� ���� ������������ ������� ���� ����
������������� ������ �������� ���� ���� ������ ����� ���� �����
���������������������������������������������������������������
�������� �������� �������� ���� ��������� � ������������ �����
��������������������
�������������������������������������������������������������
����������������������������������������������������������
�������������������������������������������������������������
���������� ���������� ��� ���� ���� ���� ���� ��� ����������
�������������������������������������������������������������
�����������������������������������������������������������
�������������������
���������������������
��
��
��
�
�� ���� �� ���� �� ���� ��
������������������
���������������������������������������������
������������
�
���
���
��� ��� ��� ��� ��� ��� �
�����������
����������������������������������
�
����� �� ������ ���� ��������� ������� ������ ��� ��� ���� ���
����������� ���� ��������� ������� ����� ������������ ������ ���
���������������

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
�����������������������������������������������������������������
���������
�
��� �������� ���� ��������� ��� �� ����� ������������� �� ���������
�����������������������������������������������������������
������������������������������������������������������������
��� ������ ��� ���������� ������������ �� �����������
������������� ���� ����� ��� ������������� ����� �� ������ ����
������������������������������������������������������������
������� ���� ���� ���������� ���� ������ ��� ��� ����� ���� ���
�����������������������������������������������������������
����������������������������������������������������������
����������� ���� ��������� ����� ������ ��� ������ ����� ����
������������ ��� ������ ��� ����� �������� ���� ��� ����� ��� ���
������� ���� �������� ������ ���� ������� ���� ����� �������� ����
������������������������������������������������������������
��� ����� ������ ��� ���������� ������ ��� ������� ���� ����������
��������������������������������������������������������
��������� ���� ��� ��� ������� ���� ����� ������ ��� ������ ���
�������������������������� � �����������������������������������
�� � � �������� ����� ������ ����� ��������� ���������� ���� �����
��������� ��������� ����� �� ������������ ��������� ��� ���� �����
�����������������
���������������
�� ������ ������������� ��� ���� ��������� ���������� ����
����������������������������������������������������������������
�� �������� ������ ���� �� ��� ���� ����� ��� ����� ��������� ��
���������� ����������� ����� ��� ��� ���� ���� ��������� �������
����� ������������ ������ ��� ��� ����� ���� ���������� ������
�������������������������������������������������������������
�������������������������������������������������
����������������
�������������������������������������������������������
�������������������������������������������������������
��������������������������������������������������������
���������� ����� ��� ���� �������� ����������� ������ ���� ����
����������������������������
�
�
�
�����������������������������
�
�
�����������
���� ��� ��� ������ ��� ����� ������ �������� ������������ ���������
���������� ��� ��������� ����� ��� ������������ ���������� ����� ����
������������������������
���� ������������������������������������������������������������
�������������������������������������������������������
���� � ��� �������� ��� ����� ���� ���� ������������ ��������� ��� �������
����������������������������������������������������
���� � ��� ���� ��� ����� ��� ������ ����������� ��� ���� ���� ��� �������
������� ������������� ������ ������ ��������� ����� ������ ����
�������
���� � ��� �������� ��� ����� ��� ������ ����������� ������� ���� ���� ���
���� ��������� ��������������� ������ ����� ������ �������� �����
�������������������
���� � ��� �������� ��� ��� ���� ������������������ ����� �����������
�������������������������������������������������
�����������������������������������
���� ��� ������ ��� ���� ���������������� �������� ��� �������
��������������������������������������������������������� �� �
���������������������������������������������������������
�����������
���� ��� ������� ��� ���� ��� ���������� ���� ����� ������ ��������������
��������������������������������������������������������
�������������������������������������������������������
����� ��� ���� ��� ����� ���� ����������� ��� ���� ��������� ���������� ���
������� ��������� �������� �������� ��� �������� �����������
�����������������������������������������������������������
�����������������������������
��������������������������������������������������������������������
����� ��� ������ ��������� ������ ��� ���� �� �� � ��������� ������
��������������������������������������������������������
A n n u A l R e p o R t 2 0 0 6
101

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
A Low-Cost, High-Performance, High-Voltage Complementary BiCMOS Process
102 A n n u A l R e p o R t 2 0 0 6
D. Knoll, B. Heinemann, K. E. Ehwald, A. Fox, H. Rücker, R. Barth, D. Bolze, T. Grabolla,
U. Haak, J. Drews, B. Kuck, S. Marschmeyer, H. H. Richter, M. Chaimanee, O. Fursenko,
P. Schley, B. Tillack, K. Köpke, Y. Yamamoto, H. E. Wulf, and D. Wolansky
Abstract
We demonstrate a low-cost, high-performance, high-voltage
complementary SiGe:C BiCMOS process. This technology
offers three npn SiGe:C devices with fT/ BVCEO values of
40GHz/ 5V, 63GHz/ 3.5V, and 120GHz/ 2.1V together with a
32GHz fT/ 35GHz fmax/ 4.4V pnp SiGe:C HBT by adding only
three bipolar masks to the underlying RF-CMOS process. With
two additional implant masks, a 150GHz, 2.2V npn HBT and
either a 43GHz fT/ 65GHz fmax/ 4.2V pnp or a 38GHz fT/
70GHz fmax, 5.8V pnp device can be fabricated additionally (in
the npn case) or alternatively (pnp case) to the devices of the 3mask
module.
Introduction
It has long been recognized that a Si bipolar or BiCMOS
technology platform containing both npn and pnp devices with
matched performance can offer compelling advantages in many
types of analog circuits (1, 2). An ideal process for such
applications could be a complementary BiCMOS (CBiCMOS)
process which provides, on the bipolar side, both npn and pnp
devices with best RF performance, combined with higher
voltage transistors, but preferably at a process cost not too
much above that of BiCMOS or even RF-CMOS. Recently,
first SiGe CBiCMOS technologies have been reported (3-5),
demonstrating a level of pnp RF performance not seen before
(4, 5). For these technologies, however, performance has
clearly the primacy, while cost is not in the main focus. Here,
we demonstrate for the first time a strictly cost-optimized
SiGe:C CBiCMOS process, which offers, with a minimum of
bipolar mask and processing steps, ample npn and pnp
performance for the majority of applications. The key measures
to get a low-cost, complementary bipolar module are the
adaptation of the process sequence applied in our 1-mask npnonly
module (6) also for pnp fabrication, and the introduction of
a second shallow trench (SSTR) which has a lower depth
compared to the trench of the process core. The SSTR, which is
filled and planarized together with the core trench, separates the
active HBT regions from the collector contact regions and
allows us to reach simultaneously low values of collector
resistance (RC) and base-collector capacitance (CBC) with a
1-4244-0439-8/06/$20.00 © 2006 IEEE
IeDM technical Digest, 607 (2006)
IHP
Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
simple, epi-free collector structure.
Our primary results can be summarized as follows. 1) With a
minimum of only three bipolar mask adders, the new
CBiCMOS process offers 3 types of npn SiGe:C devices
featuring 120GHz fT (at 2.1V BVCEO), 63GHz fT (3.5V BVCEO),
and 40GHz fT (5V BVCEO), together with a 32GHz fT, 35GHz
fmax, 4.2V pnp SiGe:C HBT. 2) With two additional implant
masks, i.e. with only 5 bipolar masks in total, a 150GHz fT,
2.2V npn HBT and either a 43GHz fT, 65GHz fmax, 4.2V pnp or
a 38GHz fT, 70GHz fmax, 5.8V pnp device can be fabricated
additionally (in the npn case) or alternatively (pnp case) to the
devices of the 3-mask module.
A. Process Integration
CBiCMOS Process Flow
Fig. 1 demonstrates the new SiGe:C CBiCMOS process. As
baseline, a 0.25µm RF-CMOS platform is used which is very
similar to that of IHP’s high-performance CBiCMOS process
(4, 5). The baseline offers, with 20 lithographic steps, a triplewell
CMOS core, several types of polysilicon resistors with
sheet resistances ranging from 7Ω to 2kΩ, a MIM capacitor,
and a 5-level Al-BEOL with 2µm and 3µm thick top layers. By
adding the 3-mask or 5-mask complementary HBT modules,
the total CBiCMOS mask count is 23 and 25, respectively.
An essential goal for any bipolar integration in a CMOS
baseline is the reuse of CMOS libraries in the BiCMOS
process. An advantage of the applied HBT integration scheme
in this respect is that the essential bipolar process steps are
carried out already before gate structuring, as can be seen from
Fig. 1. Moreover, the same final RTP step as used in the CMOS
baseline is applied also for the CBiCMOS process. In result, the
bipolar integration is fully modular, i.e. the core CMOS
parameters remain unchanged, compared to the RF-CMOS
baseline.
B. NPN and PNP HBT Fabrication
The complementary SiGe:C HBTs consist of implanted, epi-

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
RF-CMOS Baseline Bipolar Adders
Mask “STR”
Std. depth trench etch
Liner / trench fill / CMP
CMOS well implants
Gate stack deposition
Nitride protection layer
Nitride wet etch
Gate RIE
S/D implants + RTA
Salicide blocker
CoSi formation
5 level AlCu BEOL incl.
MIM module
Mask (A) “SSTR“
Low depth trench etch
Mask (D) “NPN COLL”
NPN collector implant
Mask (E) “PNP COLL”
PNP collector implant
Mask (B) “NEWIN”
NPN module * )
Mask (C) “PEWIN”
PNP module * )
* ) Module main steps
• Nitride / Poly RIE
• Oxide wet etch
• Si / p + or n + SiGe:C / Si
differential epi
• Spacer formation
• n + or p + emitter
deposition
• Poly CMP on Nitride
Fig. 1. CBiCMOS process flow. The 3-mask complementary bipolar
module uses masks (A-C) only, while masks (D) and/or (E), with the
corresponding collector and isolation implants, can be added to get
enhanced performance for both device types.
free collectors, with the second shallow trench (SSTR) located
between the active HBT region and the collector contact region,
as shown in Fig. 2. The 3-mask module uses mainly CMOS
well implants to form the different bipolar collectors including
the vertical isolation of the pnp collector from the p - substrate
(Fig. 3). The higher performance of the 5-mask module stems
from extra collector and isolation implants introduced with the
masks “NPN COLL” and “PNP COLL”, respectively, before
forming the gate stack.
HBT fabrication essentially starts after depositing the MOS
gates and a Si3N4 protection layer. The fabrication steps are
similar to the sequence described previously for a npn-only
module (6), including the removal of the gate material from the
HBT regions, growing the SiGe:C base and a Si cap layer,
forming spacers, and depositing a highly-doped emitter layer.
Collector Emitter
n +
Gate
CoSi
SSTR
W plug
p +
n-SiGe:C base
Collector
Process core
shallow trench
Oxide spacer
SSTR
Fig. 2. SEM X-sections of a pnp SiGe:C HBT illustrating the two trench
types used. Note that same hard mask, trench fill, and CMP processes are
used for both trenches, as can be seen from Fig.1.
Finally, the emitter and base material is removed by CMP from
the Si3N4 layer surface, separating the emitter from the external
base. This sequence is applied first for the npn and then again
for the pnp devices. After wet etching the nitride film from the
gate stack, CMOS device fabrication is completed with the gate
structuring process and the source/drain implantations. These
process steps are also be used for structuring and doping the
HBT external base regions.
Oxide spacer p + Emitter
SSTR
SIC
n-SiGe:C base
Poly SiGe:C/Si
p-Well
Deep n-Well (as used for NMOS isolation)
n + Gate
poly
p + S/D
Fig. 3. Schematic X-section of the PNP-1 SiGe:C HBT which uses only
implants from the CMOS process core for collector formation and vertical
device isolation.
A n n u A l R e p o R t 2 0 0 6
103

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
f T or f max (GHz)
100
90
80
70
60
50
40
30
20
10
0
V CE = 2V
10 -4
f max
104 A n n u A l R e p o R t 2 0 0 6
Device Results
Table 1 summarizes all devices available with the 3-mask and
5-mask complementary bipolar module, respectively.
TABLE I
COMPLEMENTARY SiGe:C HBTS AVAILABLE WITH A 3-MASK OR 5-
MASK BIPOLAR MODULE
HBT Typical parameters (for emitter dimensions, see below)
3-mask, complementary HBT module
NPN-1 fT/ fmax= 40/ 80GHz, BVCEO= 5.0V, β= 220
NPN-2 fT/ fmax= 63/ 95GHz, BVCEO= 3.5V, β= 220
NPN-3 fT/ fmax= 120/ 110GHz, BVCEO= 2.1V, β= 220
PNP-1 fT/ fmax= 32/ 35GHz, BVCEO= 4.4V, β= 25
5-mask, complementary HBT module
(Additional (npn) and alternative (pnp) bipolar devices)
NPN-4 fT/ fmax= 150/ 160GHz, BVCEO= 2.2V, β= 220
PNP-2 or* ) fT/ fmax= 43/ 65GHz, BVCEO= 4.2V, β= 25
PNP-3 fT/ fmax= 38/ 70GHz, BVCEO= 5.8V, β= 25
* ) Choice between low-voltage, high-fT PNP-2 and high-voltage, high-fmax
PNP-3 by using different implants with mask “PNP COLL”; see Fig. 1.
The drawn emitter width and length of all these devices
(defined by masks “NEWIN” or “PEWIN”) is 850nm and
1480nm, respectively. By applying an inside spacer technology,
the effective emitter dimensions are lower, as can be seen from
Fig. 2. For the RF measurements (Figs. 4-7), output
characteristics (Fig. 8), and Gummel plots (Fig. 9), small arrays
with ten of such devices in parallel were used.
Figs. 4 and 5 show fT and fmax vs. collector current for the npn
transistors, respectively. The better performance of the NPN-
4 transistor in comparison to NPN-3 (where the collector is
formed mainly by CMOS well implants), comes from the
higher collector doping introduced with the extra mask “NPN
COLL”. Fig. 6 shows fT and fmax vs. collector current for the
NPN-1
fT NPN-2
10 -3
Collector Current (A)
10 -2
Fig. 4: fT and fmax vs. collector current for high-voltage npn transistors (10
devices in parallel).
f T or f max (GHz)
f T or f max (GHz)
Transit Frequency (GHz)
160
140
120
100
80
60
40
20
0
70
60
50
40
30
20
10
0
10 -4
V CE = -3V
f max
10 -4
f max
10 -3
NPN-4
NPN-3
V CE = 1.5V
10 -2
Collector Current (A)
Fig. 5: fT and fmax vs. collector current for low-voltage npn transistors (10
devices in parallel).
PNP-3
10 -4
f T
10 -3
PNP-1
Collector Current (A)
10 -3
f T
PNP-2
10 -2
Fig. 6: fT and fmax vs. collector current for pnp transistors (10 devices in
parallel).
45
40 PNP-2
-3
35
30
25
-1.5
-1
-2
20
15
10
5
V (V) CE
Collector Current (A)
10 -2
Fig. 7: fT vs. collector current at different collector-emitter voltages for a
pnp transistor.
three pnp devices available. The strong improvement in fmax
of PNP-2 and PNP-3 compared to PNP-1, as demonstrated in
Fig. 6, results primarily from the optimized combination of
collector and isolation implants, applied with the extra mask
“PNP COLL”. Fig. 7 demonstrates the low voltage
dependence of the pnp RF parameters resulting from the high
base doping applied and a careful profile design at the basecollector
junction.

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
Collector Current (mA)
10.0
7.5
5.0
2.5
0.0
-2.5
-5.0
-7.5
-10.0
10 -11
10 -10
10 -9
10 -8
10 -7
10 -6
10 -5
10 -4
10 -3
10 -2
PNP-3
NPN-3
PNP-2
PNP-1
NPN-4
NPN-2
NPN-1
-8 -7 -6 -5 -4 -3 1 2 3 4 5 6 7 8 9
Collector-Emitter Voltage (V)
Fig. 8: pnp and npn SiGe:C HBT open-base output characteristics.
Base or Collector Current (A)
PNP-1
V CB = 0V
NPN-4
-0.8 -0.4 0.4 0.8
Base-Emitter Voltage (V)
Fig. 9: Gummel plots of pnp and npn SiGe:C HBTs.
Figs. 8 and 9 show open-base output characteristics
demonstrating the different BVCEO values, and Gummel plots,
respectively.
Manufacturability of the new HBT module is demonstrated
by low-leakage Gummel plots of 4k pnp HBT arrays (Fig.
10), and by a typical wafer map of the pnp current gain
demonstrating a very low σ (Fig. 11).
Summary and Conclusions
In summary, we have demonstrated a new CBiCMOS SiGe:C
HBT process which provides high-performance and highvoltage
at a very low process complexity, and thus cost. It
offers several complementary bipolar device types, including
a 150GHz fT, 160GHz fmax npn and a 43GHz fT, 65GHz fmax
pnp transistor by adding only 5 mask levels to a RF CMOS
baseline.
Base or Collector Current (A)
10 -10
10 -9
10 -8
10 -7
10 -6
10 -5
10 -4
10 -3
10 -2
10 -1
from 7 wafer sites
@ V CB = 0 and 1V
-0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3
Base-Emitter Voltage (V)
Fig. 10: Gummel plots of 4k pnp transistor arrays.
No. of Devices
10
8
6
4
2
References
Arrays of 4096
pnp transistors
(1) J. D. Cressler et al., “A high-speed complementary silicon bipolar
technology with 12-fJ power-delay product”, IEEE Electron Device
Letters, Vol. 14, pp. 523-526, November 1993.
(2) D. M. Monticelli, “The future of complementary bipolar”, Proceedings of
the 2004 Bipolar/BiCMOS Technology Meeting (BCTM), pp. 21-25
(2004).
(3) B. El-Kareh et al., “A 5V complementary-SiGe BiCMOS technology for
high-speed precision analog circuits”, Proceedings of the 2003
Bipolar/BiCMOS Technology Meeting (BCTM), pp. 211-214 (2003).
(4) B. Heinemann et al., “A complementary BiCMOS technology with high
speed npn and pnp SiGe:C HBTs”, Technical Digest of the 2002
International Devices Meeting (IEDM), pp. 117-120 (2003).
(5) B. Heinemann et al., “Complementary BiCMOS”, Proceedings of the 1 st
Int. Symposium SiGe: Materials, Processing, and Devices, ECS, Vol.
2004-07, pp. 25-31 (2004).
(6) D. Knoll et al., “A flexible, low-cost, high performance SiGe:C BiCMOS
process with a one-mask HBT module, Technical Digest of the 2002
International Devices Meeting (IEDM), pp. 783-786 (2002).
I B
I C
0
21 22 23 24 25 26 27
Beta @ V = -0.7V
BE
Fig. 11: Wafer histogram of pnp transistor current gain, measured on 45
sites of an 8-inch wafer.
A n n u A l R e p o R t 2 0 0 6
105

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
106 A n n u A l R e p o R t 2 0 0 6
ECS Transactions, 3 (7) 1069-1075 (2006)
10.1149/1.2355901, copyright The Electrochemical Society
Dopant Diffusion in SiGeC Alloys
H. Rücker, B. Heinemann, R. Kurps, and Y. Yamamoto
IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
In this paper, we discuss the impact of germanium and carbon on
the diffusion of common dopants in Si-based alloys. We review results
of various diffusion experiments and discuss the basic physical
mechanisms of the observed changes of diffusion coefficients
as a function of alloy composition. Results of boron and phosphorus
marker layer diffusion experiments are presented for binary
Si1-xGex and Si1-yCy and ternary Si1-x-yGexCy alloys.
Introduction
Alloying germanium and/or carbon to the Si lattice can change diffusion coefficients of B,
P, As, and Sb by more than one order of magnitude. These effects have a major impact on
design and fabrication of Si-based heterojunction devices such as high-speed npn and pnp
SiGe HBTs and strained channel FETs. The most prominent example for the exploitation
of suppressed dopant diffusion is the npn SiGe HBT. Reduced diffusion of boron in SiGe
has facilitated the fabrication of extremely sharp base doping profiles resulting in excellent
RF performance. Carbon doping of the SiGe layer has been identified as a means for
further suppression of the diffusion of boron and consequently became an indispensable
feature of state-of-the-art high-performance SiGe HBTs.
This paper is organized as follows. The next section shortly reviews diffusion experiments
in strained and relaxed SiGe alloys. The impact of C on dopant diffusion in
carbon-doped Si is discussed in the following section. In the final section, diffusion of B
and P in ternary SiGe:C alloys is investigated by marker layer experiments.
Strained and relaxed SiGe herterostructures
In epitaxial SiGe layers, alloy composition and strain manipulate dopant diffusion coefficients.
Cowern et al. [1] have demonstrated that the diffusion coefficients of B and Ge
depend exponentially on the Ge content x in compressively strained Si1-xGex layers on Si
(100) substrates. The dependence of the diffusion coefficients on the Ge content x is described
by
~
D( x)
� D0
exp( xQ
/ kT ) , (1)
where D0 is the diffusion coefficient in Ge-free silicon and Q ~ describes a change of
the activation energy with increasing Ge content. According to Ref. [1], the suppressed
diffusion of B in epitaxial Si1-xGex on Si (100) is described by a coefficient Q ~ (B) = -0.71
eV while the enhanced diffusion of Ge is described by a coefficient Q ~ (Ge) = 1.68 eV.
Please note that these activation energy coefficients Q ~ account for contributions due to
strain and due to chemical effects.
1069

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
ECS Transactions, 3 (7) 1069-1075 (2006)
For numerical simulation of dopant diffusion in SiGe layers in various strain states, a
quantitative description of the individual effects of strain and of alloy composition is
needed. Several experiments have been performed over the last 15 years to measure the
diffusion coefficients of common dopants as a function of chemical composition and of
the strain state of epitaxial Si1-xGex layers. These experiments provided a consistent picture
of the qualitative effects of strain and composition. However, numerical values of the
dependencies of diffusion coefficients on strain and alloy composition are still under dispute.
Strain influences the diffusivity of vacancy diffusers and interstitial diffusers in opposite
direction. While compressive biaxial strain suppresses the diffusion of the interstitial
diffuser B [2], it enhances the diffusion of Sb [3] and Ge [4] which diffuse via a vacancy
mechanism. Tensile strain changes diffusivities in the opposite direction. This behavior
can be explained qualitatively by the influence of strain on the formation enthalpies of
interstitial and vacancy-like point defects. In general, compressive strain increases formation
energies of interstitial defects and reduces formation energies of vacancy-like defects.
Consequently, interstitial densities are reduced while vacancy densities are enhanced in
compressively strained layers.
The chemical composition of the alloy acts in a more complex way on binding energies
and mean free paths of the mobile defects of different dopant atoms. In relaxed SiGe,
diffusivities of P [5], As [5], and Sb [4] are enhanced relative to those in Si while the diffusivity
of B [6] is reduced.
Moreover, dopant segregation at Si/SiGe interfaces has to be considered for the interpretation
of diffusion experiments in SiGe heterostructures. Thus, B segregates into layers
of higher Ge content while P segregates into adjacent Ge-free Si layers. This segregation
is controlled by the change of the enthalpy of the substitutional dopant ion with Ge
fraction due to chemical effects as well as due to electric fields caused by free carrier
confinement [7-9].
The impact of carbon
The effect of C on the diffusion of dopants in Si and SiGe is primarily due to changed
densities of the intrinsic point defects (vacancies and self-interstitials) in C-rich regions.
Substitutional C in Si was found to suppress strongly the diffusion of boron during annealing
of implantation damage [10] as well as during annealing steps without excess interstitials
[11]. A reduction of the B diffusivity by a factor of twenty has been reported
for Si:C layers with a C concentration of 1x10 20 cm -3 [11]. Diffusion of phosphorus is
suppressed in a similar way while diffusion of arsenic and antimony is enhanced in Cdoped
Si [12]. Since B and P diffuse via an interstitial mechanism and Sb and As diffuse
via a vacancy mechanism, these observations indicate a suppressed density of self-interstitials
and an enhanced density of vacancies in C-doped Si.
Fast out-diffusion of C from regions of high C concentration has been identified as
the driving force for these non-equilibrium point defect densities [13]. During anneals, C
diffuses out of regions of high C concentration. C diffusion in Si occurs via a substitutional-interstitial
exchange mechanism. Immobile substitutional carbon atoms (Cs) are
1070
A n n u A l R e p o R t 2 0 0 6
107

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
108 A n n u A l R e p o R t 2 0 0 6
transformed into mobile interstitial carbon (Ci) through the kick-out reaction with Si selfinterstitials
(I)
Cs + I � Ci. (2)
In addition, interstitial C can be formed in the dissociative Frank-Turnbull reaction
Cs � Ci +V, (3)
where V is a vacancy. The flux of mobile Ci defects out of C-rich regions has to be
compensated by an opposite flux of Si self-interstitials into the C-rich region, and/or a
flux of vacancies outwards. For C concentrations above ~10 18 cm -3 , the product of the C
concentration and the C diffusion coefficient exceeds the corresponding transport parameters
for the fluxes of self-interstitials and vacancies:
CCDC > CI eq DI and CCDC > CV eq DI . (4)
Under these conditions, diffusion of C becomes limited by the compensating fluxes of
Si point defects, which in turn leads to an undersaturation of self-interstitials and a supersaturation
of vacancies in the C-rich region [12-14]. In addition, C precipitation can cause
a further suppression of the density of self-interstitials for C concentrations of about
10 20 cm -3 and higher [15].
Ternary Si1-x-yGexCy alloys
In ternary Si1-x-yGexCy alloys, the discussed effects of germanium and carbon act simultaneously.
Carbon doping causes an additional reduction of the diffusivity of B in
SiGe [9]. It has been reported that the suppression of B diffusion due to carbon can be
even stronger in SiGe:C than in Si:C [16].
We have studied the combined effects of Ge and C alloying on the diffusion of
dopants by marker layer experiments in binary Si1-xGex and Si1-yCy and ternary
Si1-x-yGexCy layers. Boron and phosphorus diffusion markers were in situ grown by low
pressure CVD in Si, Si0.9Ge0.1, and Si0.8Ge0.2 layers with three different C concentrations
in each case. The SiGe:C layers are pseudomorphically strained on Si (100) substrates.
Diffusion coefficients were extracted from numerical fitting of secondary-ion mass
spectroscopy (SIMS) depth profiles measured before and after annealing. SIMS profiles
were measured using a CAMECA IMS WF with a 0.5 keV O2 ion beam for B and Ge
profiling and a 1 keV Cs ion beam for P and C profiling.
Boron Diffusion
ECS Transactions, 3 (7) 1069-1075 (2006)
Three wafers with boron diffusion markers were grown. Each water contained tree
boron spikes with peak concentrations of about 2x10 18 cm -3 . The boron spikes were centered
in 25nm wide Si1-x-yGexCy layers with different alloy compositions. Typical depth
profiles are shown in Fig. 1 for the wafer with a Ge content of 10% in the alloy layers.
The as-grown C concentrations for the three spikes are 1x10 20 cm -3 , 3x10 19 cm -3 , and below
the detection limit of 1x10 18 cm -3 , respectively. For the other two wafers the Ge content
was changed to 20% and 0% while B and C profiles were similar to the first wafer.
1071

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
B & C Concentration (cm -3 )
10 20
10 19
10 18
10 17
ECS Transactions, 3 (7) 1069-1075 (2006)
10
0 50 100 150 200
16
Depth (nm)
Figure 1. SIMS profiles of B diffusion markers in Si0.9Ge0.1:C layers with three different
C concentrations. The as-grown Ge, C, and B profiles are shown together with the diffused
boron profile after annealing at 900ºC for 1 hour.
Diffused profiles were measured for all samples after annealing at 900ºC for 15 minutes
and for 1 hour. For the chosen low B concentrations, B diffusion is well described by
Fickian diffusion with constant diffusion coefficients. Diffusion coefficients were extracted
by fitting the annealed B profiles with a Fickian diffusion equation using the asgrown
B profile as input. The obtained diffusion coefficients at 900ºC are plotted in Fig.
2 as a function of Ge and C concentrations.
The diffusion coefficients of B in the C-free SiGe samples shown in Fig. 2 confirm
the exponential dependence on Ge content proposed in [1]. For each of the three C concentrations
investigated here, we have applied Eq. (1) to fit the B diffusion coefficients as
a function of the Ge content (lines in Fig. 2). Results of the fit are summarized in Table 1.
TABLE I. Diffusion parameters of B in SiGe:C alloys at 900ºC obtained from fitting the data of Fig. 2
to Eq. (1).
Carbon concentration (cm -3 )
D 0 (cm -2 /s) Q ~ (eV)
< 1E18 9.7 10 -14 -0.58
3E19 2.2 10 -14 -0.81
1E20 5.4 10 -13 -0.65
Carbon doping results in a suppression of B diffusivities by almost the same factor for
the three considered Ge concentrations. C concentrations of 3E19cm -3 were found to suppress
B diffusivities by about a factor of 5 while C concentrations of 1E20cm -3 suppressed
B diffusivities by about a factor of 20. Within the accuracy of the present experiments,
the suppression of boron diffusion in SiGe:C can be described as a product of
a retardation coefficient due to Ge and a retardation coefficient due to C.
1072
14
12
10
8
6
4
2
0
Ge Content (%)
A n n u A l R e p o R t 2 0 0 6
109

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
110 A n n u A l R e p o R t 2 0 0 6
B Diffusion Coefficient (10 -14 cm -2 /s)
10
1
0.1
no C
3x10 19 cm -3 C
1x10 20 cm -3 C
0.0 0.1 0.2
Ge Content
Figure 2. Extracted diffusion coefficients of B in SiGe:C alloys at 900ºC as a function
of Ge and C concentrations. Error bars were estimated from the scattering of the fitted
diffusion coefficients for different annealing times and from uncertainties of the numerical
fits. Lines are fits of the diffusion coefficients as a function of the Ge content according
to Eq. (1).
Phosphorus Diffusion
We have investigated the diffusion of P in Si, Si0.9Ge0.1, Si0.8Ge0.2, and Si0.8Ge0.2:C
doped with 5x10 19 cm -3 carbon.. All layers are grown pseudomorphically on Si (100)
substrates. Two P diffusion profiles in Si and strained Si0.9Ge0.1 are shown in Fig. 3.
P Concentration (cm -3 )
10 18
10 17
(a)
ECS Transactions, 3 (7) 1069-1075 (2006)
20 40 60 80 100
1073
(b)
Depth (nm)
20 40 60 80 100 0
Figure 3. SIMS profiles of P diffusion markers in as-grown samples and after annealing
at 900ºC for 15 min. (a) Si reference sample, (b) Si0.9Ge0.1 sample.
10
8
6
4
2
Ge Content (%)

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
According to the previous discussion, P diffusion in compressively strained SiGe is
expected to be suppressed due to strain and enhanced due to Ge alloying. Fig. 3 indicates
that the combined effect of strain and alloy composition is a slower diffusion of P in
Si0.9Ge0.1 than in Si. Moreover, Fig. 3 indicates a segregation of P from the Si0.9Ge0.1
layer into the adjacent Si region.
This segregation of P is much more pronounced for the Si0.8Ge0.2 sample (Fig.4a).
Comparison of the P diffusion profiles in Figs. 4a and 4b shows that C doping results in a
strong suppression of P diffusion in SiGe. However, more experimental data are needed
for an accurate determination of diffusion and segregation coefficients of P as a function
of Ge and C concentration.
P & C Concentration (cm -3 )
10 20
10 19
10 18
10 17
(a)
10
0 50 100
16
ECS Transactions, 3 (7) 1069-1075 (2006)
Ge
0 50 100 150 0
Depth (nm)
Figure 4. SIMS profiles of P diffusion markers in as-grown samples and after annealing
at 900ºC for 60 min. (a) Si0.8Ge0.2 sample without carbon doping (b) Si0.8Ge0.2 sample
doped with 5x10 19 cm -3 carbon.
1074
(b)
Conclusions
Dopant diffusion coefficients in SiGe:C alloy show changes of more than one order
of magnitude as a function of alloy composition. In SiGe heterostructures, diffusion coefficients
are influenced by Ge content, strain and segregation across Si/SiGe interfaces. C
doping suppresses diffusion coefficients of the interstitial diffusers B and P and enhances
diffusion coefficients of the vacancy diffusers As and Sb. In ternary SiGe:C alloys, the
suppression of the diffusion coefficient of boron can be approximately described as a
product of a retardation coefficient due to Ge and a retardation coefficient due to C.
References
1. N. E. B. Cowern, P. C. Zalm, P. van der Sluis, D. J. Gravensteijn, and W. B. de
Boer, Phys. Rev. Lett. 72, 2585 (1994).
2. N. R. Zangenberg, J. Fage-Pedersen, J. Lundsgaard Hnasen, and A. Nylandsted
Larsen, J. Appl. Phys. 94, 3883 (2003).
C
Ge
20
15
10
5
Ge Content (%)
A n n u A l R e p o R t 2 0 0 6
111

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
112 A n n u A l R e p o R t 2 0 0 6
ECS Transactions, 3 (7) 1069-1075 (2006)
3. P. Kringhoj, A. Nylandsted Larsen, and S. Y. Shirayev, Phys. Rev. Lett. 76, 3372
(1996).
4. G. Xia, O. O. Olubuyide, J. L. Hoyt, and M. Canonico, Appl. Phys. Lett. 88,
013507 (2006).
5. S. Eguchi, J. L. Hoyt, C. W. Leitz, and E. A. Fitzgerald, Appl. Phys. Lett. 80,
1743 (2002).
6. P. Kuo, J. L. Hoyt, J. F. Gibbons, J. E. Turner, and D. Lefforge, Appl. Phys. Lett.
66, 580 (1995).
7. S. M. Hu, D. C. Ahlgren, P. A. Rosenheim, and J. O. Chu, Phys. Rev. Lett. 67,
1450 (1991).
8. R. F. Lever, J. M. Bonar, and A. F. W. Willoughby, J. Appl. Phys. 83 1988
(1998).
9. H. Rücker and B. Heinemann, Solid-State Electronics 44 783 (2000).
10. P. A. Stolk, H.-J. Gossmann, D. J. Eaglesham, D.C. Jacobson, C. S. Rafferty, G.
H. Gilmer, M. Jaraiz, J. M. Poate, H. S. Luftmann, and T. E. Hayes, Appl. Phys.
Lett. 66, 1370 (1995).
11. H. Rücker, B. Heinemann, W. Röpke, R. Kurps, D. Krüger, G. Lippert, and H. J.
Osten, Appl. Phys. Lett. 73, 1682 (1998) and 75, 147 (E) (1999) .
12. H. Rücker, B. Heinemann, D. Bolze, D. Knoll, D. Krüger, R. Kurps, H. J. Osten,
P. Schley, B. Tillack, and P. Zaumseil, Technical Digest, International Electron
Device Meeting, (IEEE, Piscataway, NJ, 1999) p.109.
13. R. Scholz, U. Gösele, J.-Y. Huh, and T. Y. Tan, Appl. Phys. Lett. 72, 200 (1998).
14. R. F. Scholz, P. Werner, U. Gösele, and T. Y. Tan, Appl. Phys. Lett. 74, 392
(1999).
15. H. Rücker, B. Heinemann, and R. Kurps, Phys. Rev. B 64, 073202 (2001).
16. M. S. A. Karunaratne, A. F. W. Willoughby, J. M. Bonar, J. Zhang, and P.
Ashburn, J. Appl. Phys. 97, 113531 (2005).
1075

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 8, AUGUST 2006 1937
Briefs
High-Quality Al2O3/Pr2O3/Al2O3 MIM Capacitors
for RF Applications
Ch. Wenger, G. Lippert, R. Sorge, T. Schroeder, A. U. Mane,
G. Lupina, J. Dabrowski, P. Zaumseil, X. Fan, L. Oberbeck,
U. Schroeder, and H.-J. Müssig
Abstract—The electrical characteristics of layered Al2O3/Pr2O3/
Al2O3 metal–insulator–metal (MIM) capacitors for RF device applications
are presented for the first time. This advanced dielectric layer system
4-nm Al2O3/8-nm Pr2O3/4-nm Al2O3 shows a high capacitance density
of 5.7 fF/µm 2 , a low leakage current density of 5 × 10 −9 A/cm 2 at 1 V,
and an excellent dielectric loss behavior over the studied frequency range.
Index Terms—Capacitor, high-κ, metal–insulator–metal (MIM), thinfilm
devices, voltage linearity.
I. INTRODUCTION
The metal–insulator–metal (MIM) capacitors as passive devices
for RF and mixed-signal IC applications have attracted much attention.
The replacement of conventional SiO2 and Si3N4 by high-k
dielectric materials is essential to reduce the capacitor area. Recently,
several high-k materials such as Al2O3, AlTiOx, AlTaOx,
(HfO2)1−x(Al2O3)x, HfO2, ZrO2, Y2O3, Ta2O5, PrTixOy, and Pr2O3
have been investigated as potential MIM capacitor dielectrics [1]–[10].
Pr2O3 exhibits a promising k-value of 15–30 [7]. However, because
of moderate leakage characteristics [9], MIM capacitors including
pure Pr2O3 dielectrics are not suitable for RF applications. As an
alternative, layered Al2O3/Pr2O3/Al2O3 MIM capacitors are promising
candidates to meet the requirements of the current International
Roadmap for Semiconductors (ITRS). In this brief, we present a
new high-k MIM stack with a high capacitance density as high as
5.7 fF/µm 2 and a low leakage current density. The intrinsic losses
of the dielectrics were extracted by equivalent circuit simulation.
II. EXPERIMENTS
Sputtered TiN films with a thickness of 10 nm were used as bottom
electrodes. Al2O3 and Pr2O3 films with various thicknesses were
deposited by electron beam evaporation, with 4-nm-thick Al2O3 layers
at the bottom and top sides of the dielectric stack. The thickness of
the Pr2O3 layers was varied in the range of 9–77 nm. The Al2O3 and
Pr2O3 layers were deposited at 100 ◦ C. Finally, Au dots with a diameter
of 400 µm were evaporated through a shadow mask. Capacitance
density, leakage current, and dielectric loss were measured to electrically
characterize the MIM capacitors. Physical analysis of the stacked
films was done by cross section transmission electron microscopy
(XTEM), X-ray reflection (XRR), and X-ray diffraction (XRD).
Manuscript received February 7, 2006; revised April 27, 2006. This work
was supported within the scope of technology development by the EFRE fund
of the European Community and by the State Saxony of the Federal Republic
of Germany. The review of this brief was arranged by Editor V. R. Rao.
Ch. Wenger, G. Lippert, R. Sorge, T. Schroeder, A. U. Mane, G. Lupina,
J. Dabrowski, P. Zaumseil, X. Fan, and H.-J. Müssig are with IHP, 15236
Frankfurt (Oder), Germany (e-mail: wenger@ihp-microelectronics.com).
L. Oberbeck and U. Schroeder are with Infineon Technologies SC300 GmbH
and Co. OHG, 01099 Dresden, Germany.
Digital Object Identifier 10.1109/TED.2006.877870
0018-9383/$20.00 © 2006 IEEE
Fig. 1. XTEM picture of the Al2O3/Pr2O3/Al2O3 stack MIM capacitor.
III. RESULTS AND DISCUSSIONS
MIM capacitors with Pr2O3 as the dielectric demonstrated high-k
values (∼ 15), but the leakage current density is not sufficiently low
[9]. For this reason, we use the band-offset engineering approach by
sandwiching the Pr2O3 film between two layers of the wide band gap
insulator Al2O3. Aside from the increase of the electric barrier height,
the top Al2O3 layer also acts as a cap to protect the Pr2O3 film against
humidity. The hygroscopic nature is a well-known characteristic of
Pr2O3 [11]. Positive fixed charges can be created by water absorption
from air, which affect the electrical characteristics in an indefinite
manner.
Due to the moderate k-value of Al2O3 (∼ 8), the resulting capacitance
of the Al2O3/Pr2O3/Al2O3 stacked MIM capacitors will be
reduced. Therefore, the Al2O3 layer thickness must be kept as thin as
possible to obtain high capacitance densities, but its barrier capability
against water diffusion has to be ensured. To meet both requirements,
the thickness of the Al2O3 was set to 4 nm.
The XTEM image of a stacked MIM capacitor with 4-nm
Al2O3/8-nm Pr2O3/4-nm Al2O3 is shown in Fig. 1. The thickness of
the dielectric stack was determined by XTEM and controlled by XRR.
XRD experiments (not shown) indicate that the Al2O3 and the Pr2O3
layers are amorphous. The capacitance density, which is measured at
10 kHz as a function of dielectric thickness, is illustrated in Fig. 2.
The highest capacitance value of 5.7 fF/µm 2 was obtained by a stack
of 4-nm Al2O3/9-nm Pr2O3/4-nm Al2O3. A model of three serial
capacitors was used to calculate the capacitance density. The fitting
parameters of these procedure were the k-values of Al2O3 and Pr2O3,
whereas the thicknesses of the dielectric films were determined by
XRR. The derived k-values are 8 for Al2O3 and 15 for Pr2O3. The
capacitance densities of pure Al2O3 and Pr2O3 capacitors, which are
calculated using these k-values, are shown in Fig. 2 (dotted lines).
The capacitance of thin stacked MIM capacitors is dominated by the
k-value of Al2O3, whereas the effective k-value of thicker MIM stacks
is regulated by Pr2O3. The dissipation factors (tan δ) obtained from
MIM capacitors with different Pr2O3 thicknesses at 0 V bias voltage
are shown in Fig. 3. The stacked capacitor with 5.7 fF/µm 2 exhibits
a small tan δ of 0.02 at a frequency of 10 kHz. With increasing the
Pr2O3 thickness, the dielectric loss increases. To extract the intrinsic
A n n u A l R e p o R t 2 0 0 6
113

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
1938 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 8, AUGUST 2006
Fig. 2. Capacitance density versus thickness of the stacked Al2O3/Pr2O3/
Al2O3 dielectrics. Solid line: serial capacitor model. Dotted line: single-layer
Al2O3 and Pr2O3 capacitors.
Fig. 3. Loss tangent (tan δ) of stacked MIM capacitors with different Pr2O3
thicknesses as a function of frequency at 0 V. Solid line: simulated loss tangents.
Fig. 4. Equivalent circuit for a layered Al2O3/Pr2O3/Al2O3 MIM capacitor.
dissipation losses of the stacked dielectrics, the tan δ of the equivalent
circuit was simulated, as shown in Fig. 4. The required capacitance
values are extracted from capacitance–voltage measurements, and
the conductivities of the Al2O3 and Pr2O3 layers are determined
from leakage current–voltage characteristics. The leakage currents of
single-layer Al2O3 and Pr2O3 MIM capacitors are shown in Fig. 5
and will be discussed later in the text. The simulated loss tangents are
114 A n n u A l R e p o R t 2 0 0 6
Fig. 5. Leakage current density at 1 V of single-layer Pr2O3 and Al2O3 MIM
capacitors as a function of dielectric film thickness. The current measurement
of Al2O3 is limited by the sensitivity of the instrument.
Fig. 6. Extracted access loss tangent as a function of frequency.
represented as solid lines in Fig. 3. The paraboliclike behavior can be
simulated, but it is clearly seen that there is an access loss, which is
not included in the used equivalent circuit. The increase of tan δ in the
high-frequency range above 100 kHz is caused by additional losses
like contact resistances. Interfacial relaxation, which is so-called the
Maxwell–Wagner effect, leads to an increase of tan δ in the frequency
regime below 10 kHz. The excess dielectric loss in the middle of the
frequency regime cannot be explained by the equivalent circuit model.
By subtracting the simulated loss tangent from the measured losses, we
extracted the access tan δ, as shown in Fig. 6. It is clearly seen that the
access dissipation factor rises with increasing Pr2O3-film thickness.
Various microscopic mechanisms can be listed to explain the dielectric
loss in the Pr2O3 layer. For example, free carriers are stored
at the dielectric–electrode interfaces, leading to space charges [12].
By applying an electric field, macroscopic dipoles will be created,

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 8, AUGUST 2006 1939
Fig. 7. Leakage current densities of stacked MIM capacitors as a function of
the applied voltage.
resulting in space charge relaxation processes. The dielectric can also
become a loss by dipolar relaxation of moving oxygen vacancies.
Further work is on the way to determine the microscopic origin of the
observed dielectric loss.
The leakage currents of single-layer Al2O3 and Pr2O3 MIM capacitors
are shown in Fig. 5. Over the studied film thickness range, the
leakage current of Pr2O3 is strongly affected by the film thickness,
whereas the leakage mechanism of Al2O3 is weakly influenced. The
current measurement in this range is limited by the sensitivity of the
instrument. Because of the higher band gap of Al2O3 (∼ 8.8 eV) [13],
the leakage current density is lower than that of Pr2O3. The estimated
band gap of Pr2O3 is around 4.6 eV [14].
The observed leakage current characteristics of the stacked dielectrics
are shown in Fig. 7. The dielectric stack of 4-nm
Al2O3/9-nm Pr2O3/4-nm Al2O3 exhibits the lowest leakage current
density of 5 × 10 −9 A/cm 2 at 1 V. The increment of the Pr2O3
thickness leads to higher leakage current densities, which correspond
to the loss tangent characteristics.
IV. CONCLUSION
The MIM capacitor with a dielectric stack composed of 4-nm
Al2O3/9-nm Pr2O3/4-nm Al2O3 exhibits excellent electrical performances,
such as high capacitance density, low dielectric loss, and
excellent leakage current density. This laminated capacitor meets the
requirements for passive MIM devices in RF applications. However,
by increasing the Pr2O3-film thickness, the loss tangent as well as the
leakage current density rise.
REFERENCES
[1] S. B. Chen, C. H Lai, A. Chin, J. C. Hsieh, and J. Liu, “High-density MIM
capacitors using Al2O3 and AlTiOx dielectrics,” IEEE Electron Device
Lett., vol. 23, no. 4, pp. 185–187, Apr. 2002.
[2] M. Y. Yang, C. H. Huang, A. Chin, C. Zhu, M. F. Li, and D.-L. Kwong,
“High-density MIM capacitors using AlTaOx Dielectrics,” IEEE Electron
Device Lett., vol. 24, no. 5, pp. 306–308, May 2003.
[3] H. Hu, C. Zhu, X. Yu, A. Chin, M. F. Li, B. J. Cho, D.-L. Kwong,
P. D. Foo, M. B. Yu, X. Liu, and J. Winkler, “MIM capacitors using
atomic-layer-deposited high-k (HfO2)1−x(Al2O3)x dielectrics,” IEEE
Electron Device Lett., vol. 24, no. 2, pp. 60–62, Feb. 2003.
0018-9383/$20.00 © 2006 IEEE
[4] X. Yu, C. Zhu, H. Hu, A. Chin, M. F. Li, B. J. Cho, D.-L. Kwong,
P. D. Foo, and M. B. Yu, “A high-density MIM capacitor (13 fF/µm 2 )
using ALD HfO2 dielectrics,” IEEE Electron Device Lett., vol. 24, no. 2,
pp. 63–65, Feb. 2003.
[5] S.-Y. Lee, H. Kim, P. C. McIntyre, K. C. Sarawat, and J.-S. Byun, “Atomic
layer deposition of ZrO2 on W for metal–insulator–metal capacitor application,”
Appl. Phys. Lett., vol. 82, no. 17, pp. 2874–2876, Apr. 2003.
[6] C. Durand, C. Vallée, V. Loup, O. Salicio, C. Dubourdieu, S. Blonkowski,
M. Bonvalot, P. Holliger, and O. Joubert, “Metal–insulator–metal capacitors
using Y2O3 dielectric grown by pulsed-injection plasma enhanced
metal–organic chemical vapor deposition,” J. Vac. Sci. Technol. A, Vac.
Surf. Films, vol. 22, no. 3, pp. 655–660, May 2004.
[7] T. Busani and R. A. B. Devine, “The importance of network structure in
high-k dielectrics: LaAlO3, Pr2O3, and Ta2O5,” J. Appl. Phys., vol. 98,
no. 4, p. 044102, Aug. 2005.
[8] T. Ishikawa, D. Kodama, Y. Matsui, M. Hiratani, T. Furusawa, and
D. Hisamoto, “High-capacitance Cu/Ta2O5/Cu MIM structure for SoC
applications featuring a single-mask add-on process,” in IEDM Tech. Dig,
2002, pp. 940–942.
[9] C. Wenger, J. Dabrowski, P. Zaumseil, R. Sorge, P. Formanek, G. Lippert,
and H.-J. Müssig, “First investigation of metal–insulator–metal (MIM)
capacitor using Pr2O3 dielectrics,” Mater. Sci. Semicond. Process., vol. 7,
no. 4–6, pp. 227–230, 2004.
[10] C. Wenger, R. Sorge, T. Schroeder, A. U. Mane, G. Lippert, G. Lupina,
J. Dabrowski, P. Zaumseil, and H.-J. Muessig, “MIM capacitors using
amorphous high-k PrtixOy dielectrics,” Micrelectron. Eng., vol. 80,
pp. 313–316, Jun. 2005.
[11] S. Jeon and H. Hwang, “Effect of hygroscopic nature on the electrical
characteristics of lanthanide oxides (Pr2O3, Sm2O3, Gd2O3 and
Dy 2 O3),” J. Appl. Phys., vol. 93, no. 10, pp. 6393–6395, May 2003.
[12] R. Coelho, Physics of Dielectrics. Amsterdam, The Netherlands: Elsevier,
1979, ch. 7.
[13] J. Robertson, “Band offets of wide-band-gap oxides and implications for
future electronic devices,” J. Vac. Sci. Technol. B, Miocroelectron, vol. 18,
no. 3, pp. 1785–1789, 2000.
[14] A. V. Prokofiev, A. I. Shelykh, and B. T. Melekh, “Periodicity in the band
gap variation of Ln2X3 (X = O, S, Se) in the lanthanide series,” J. Alloys
Compd., vol. 242, no. 1, pp. 41–44, Sep. 1996.
The Improvement of Polycrystalline Silicon TFTs
Fabricated by Employing Periodic Metal Pads
Hsu-Yu Chang, Chao-Yu Meng, Ming-Wei Tsai,
Bo-Chuan Yang, Tzu-Hung Chuang, and Si-Chen Lee
Abstract—Polysilicon films with regular-sized and large grains were
fabricated by employing periodic metal (Cr–Al) pads as the heat sinks
and with underlying silicon oxynitride (SiON) as the heat absorption
layer. The poly-Si could grow to regular hexagonal grains after excimer
laser annealing (ELA). The thin-film transistors (TFTs) fabricated by
this method show uniform characteristics that are suitable for large-area
applications. The TFT achieves a field-effect mobility of 270 cm 2 /V · s and
an ON–OFF current ratio exceeding 10 8 . It is found that the TFT with the
smaller channel width and length results in a better subthreshold swing
because it contains fewer grain boundaries and, thus, fewer defects. After
comparing the performance of TFTs using either double-metal Cr–Al
or single-metal Al photonic-crystal pads, it is found that the Cr could
efficiently impede the diffusion of Al into Si during ELA.
Index Terms—Photonic crystal, polycrystalline silicon, thin-film
transistor (TFT).
Manuscript received October 13, 2005; revised April 21, 2006. This work
was supported by the National Science Council of Taiwan, R.O.C., under
Contract NSC 93-2215-E-002-046. The review of this brief was arranged by
Editor T. Skotnicki.
The authors are with the Graduate Institute of Electronic Engineering and
Department of Electrical Engineering, National Taiwan University, Taipei
10617, Taiwan, R.O.C.
Digital Object Identifier 10.1109/TED.2006.877873
A n n u A l R e p o R t 2 0 0 6
115

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
Praseodymium silicate films on Si„100… for gate dielectric applications:
Physical and electrical characterization
G. Lupina, a� T. Schroeder, J. Dabrowski, Ch. Wenger, A. U. Mane, and H.-J. Müssig
IHP-Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
P. Hoffmann and D. Schmeisser
Angewandte Physik-Sensorik, BTU Cottbus, Konrad-Wachsmann-Allee 17, 03046 Cottbus, Germany
�Received 9 November 2005; accepted 12 March 2006; published online 12 June 2006�
Praseodymium �Pr� silicate dielectric layers were prepared by oxidation and subsequent N 2
annealing of thin Pr metal layers on SiO 2/Si�100� substrates. Transmission electron microscopy
studies reveal that the resulting dielectric has a bilayer structure. Nondestructive depth profiling by
using synchrotron radiation x-ray photoelectron spectroscopy shows that, starting from the
substrate, the dielectric stack is composed of a SiO 2-rich and a SiO 2-poor Pr silicate phase. Valence
and conduction band offsets of about 2.9 and 1.6 eV, respectively, between the dielectric and the
Si�100� substrate bands were deduced. Pr silicate films with an equivalent oxide thickness of 1.8 nm
show approximately three orders of magnitude lower leakage currents than silicon oxynitride
references. Capacitance versus voltage measurements of the Pr silicate/Si�100� system report a flat
band voltage shift of 0.22 V, an effective dielectric constant of about 11 and a reasonably good
interface quality with an interface state density on the order of 10 11 cm −2 . Experimental results are
supplemented by ab initio considerations which review the most probable mechanisms of fixed
charge formation in the Pr silicate layers. © 2006 American Institute of Physics.
�DOI: 10.1063/1.2202235�
I. INTRODUCTION
The continuous reduction of metal-oxide-semiconductor
field-effect transistor �MOSFET� dimensions was in the past
the major factor contributing to the performance increase of
integrated circuits �IC’s�. 1,2 However, as the MOSFET channel
length is shrinked to the nanometer regime, alternative
device designs, and alternative materials are necessary to
continue scaling at the current rate. 3 One of the key challenges
is the replacement of the traditional silicon dioxide
�SiO 2� gate dielectric which has become thinner than 1.5 nm
in state-of-the-art devices and does not provide sufficient insulation
anymore. 4 Although considerable progress was
achieved in optimizing oxynitride dielectrics to reduce the
gate leakage currents as compared to SiO 2, the introduction
of a material with higher dielectric constant �high k� is very
desirable. 3 Therefore, different high-k dielectrics on silicon
�Si� are currently studied. Many of the metal oxides that
initially appeared attractive due to their high dielectric constants
were eliminated because of either low conduction
band offset with respect to Si �e.g., TiO 2, Ta 2O 5� or thermodynamic
instability in contact with Si �e.g., ZrO 2�. 5,6 In contrast
to these binary compounds, transition and rare-earth
metal silicates satisfy many requirements for gate dielectrics
in advanced MOSFET devices, i.e., silicate-type materials
show reasonable k values and form a high quality interface
on Si comparable with state-of-the-art SiO 2/Si systems. 7
Based on these arguments, it is desirable to engineer a com-
a� Author to whom correspondence should be addressed; electronic mail:
lupina@ihp-microelectronics.com
116 A n n u A l R e p o R t 2 0 0 6
JOURNAL OF APPLIED PHYSICS 99, 114109 �2006�
positionally graded silicate film with a SiO 2-rich interface
layer on Si �high carrier mobility� and a SiO 2-poor top layer
�high dielectric constant�.
In this study, we take advantage of the high tendency of
praseodymium �Pr� to form silicates. 8 As a main result, it is
found that the solid state reaction of Pr with SiO 2/Si�100�
results in a silicate film morphology of the above given bilayer
structure.
II. EXPERIMENT
Phosphorus-doped Si�100� wafers ��=0.3–0.6 � cm�
covered with thin ��1.2 nm� SiO 2 layers formed by a
chemical passivation procedure 9 were used as substrates.
About 2-nm-thick Pr films were deposited on these substrates
by molecular beam epitaxy �MBE� while the wafer
was kept at room temperature �RT�. Base pressure in the
process chamber during deposition was in the 10 −8 mbar
range. Following the deposition, samples were oxidised in
air at RT. Subsequently, a postdeposition annealing step �
1 min at 700 °C� in nitrogen �N 2� with oxygen partial pressure
of 10 −5 mbar was applied. In this way Pr silicate layers
with thickness of about 5 nm were obtained.
Characterization of the film composition after each
preparation step was performed by x-ray photoelectron
spectroscopy �XPS� using nonmonochromatized AlK�
�1486.6 eV� radiation and a PHI 10–360 energy analyzer. Si
2p, O 1s, and Pr 3d core level spectra were collected at a
takeoff angle of 45°. After preparation, the structure and the
chemical composition of the dielectrics was determined.
Transmission electron microscopy �TEM� images were obtained
using a Philips CM 300 microscope with a point-to-
0021-8979/2006/99�11�/114109/8/$23.00 99, 114109-1
© 2006 American Institute of Physics
Downloaded 19 Jun 2006 to 134.105.104.45. Redistribution subject to AIP license or copyright, see http://jap.aip.org/jap/copyright.jsp

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
114109-2 Lupina et al. J. Appl. Phys. 99, 114109 �2006�
point spatial resolution of 1.8 Å. Nondestructive depth profiling
studies by synchrotron radiation XPS �SR-XPS� were
performed at the UPGM 49/2 undulator beamline of BESSY
II. 10 Incident photon energies �E 0� of 350, 600, 850, and
1100 eV were chosen to allow depth profile studies covering
the whole dielectric film thickness. The emitted photoelectrons
were collected with an Omicron EA 125 hemispherical
energy analyzer at a takeoff angle of 85° with respect to the
sample surface. All XPS and SR-XPS spectra were referenced
to the Au 4f 7/2 line �84 eV�. The electron inelastic
mean free path �IMFP� for Si 2p, O 1s, and Pr 3d photoelectrons
was estimated using the NIST Standard Reference Database
71. 11 The corresponding sampling depth was defined
as three times the IMFP.
For electrical characterization, metal-insulator-semiconductor
�MIS� capacitors were formed by in situ evaporation
of gold �Au� electrodes of �200 nm thickness on the Pr
silicate/Si�100� system. The backside of each sample was
coated with a �300-nm-thick Al layer. Finally, a postmetallization
annealing step �15 min at 300 °C� in forming gas
�5% H 2 in N 2� was applied. The capacitance versus voltage
�CV� measurements were performed in serial mode at a frequency
of 10 kHz using an Agilent 4294A impedance analyzer.
Equivalent oxide thickness �EOT� was extracted from
the accumulation capacitance using the QITFIT software
which applies a quantum-mechanical correction for charge
quantization in the Si substrate. 12 Current versus voltage
�JV� characteristics were obtained using an AVT 110 wafer
tester.
Ab initio calculations were done with the ab initio
pseudopotential plane wave code FHI96MD. 13,14 We applied
the local density approximation �LDA� for the exchange and
correlation energy 15,16 and nonlocal pseudopotentials in the
Trouller-Martins scheme 17,18 with 40 Ry cutoff for plane
waves. Since numerous defect structure have been investigated
for the purpose of this work and the typical cells have
no symmetry but many atoms, a low-symmetry special
k-point sampling scheme would require a prohibitively high
numerical effort. The Brillouin zone was thus sampled at the
� k point corresponding to the cell of dimensions as close as
possible to the dimensions of the Pr 2O 3 2�2�1 cell
�orthorombic with dimensions 1.08�1.73�1.30 nm 3 �. Tests
with more converged samplings indicate that although more
exact calculations are needed to confirm the quantitative results,
the qualitative picture presented here is valid.
III. RESULTS AND DISCUSSION
A. XPS study of film formation
The results of the in situ XPS study at the various film
preparation steps are presented in Fig. 1.
The SiO 2/Si�100� substrate exhibits Si 2p emission �Fig.
1�a�� from bulk Si and from SiO 2 located at 99.3 and
103.3 eV, respectively. The corresponding O 1s spectrum
�Fig. 1�b�� shows a single emission peak at 533.3 eV which
is typical for SiO 2. 19
After deposition of about 2 nm metallic Pr, both the Si
bulk and the small oxide related Si 2p peak �Fig. 1�a�� move
towards higher binding energy by nearly the same amount
FIG. 1. XPS Si 2p �a�, O 1s �b�, and Pr 3d �c� spectra during Pr silicate film
preparation. Labels indicate preparation steps.
��0.3 eV�. The direction of this shift is consistent with
downward band bending in the Si substrate and the presence
of a dipole over the dielectric, probably induced by charge
transfer from the Pr layer to the Si substrate in the process of
Downloaded 19 Jun 2006 to 134.105.104.45. Redistribution subject to AIP license or copyright, see http://jap.aip.org/jap/copyright.jsp
A n n u A l R e p o R t 2 0 0 6
117

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
114109-3 Lupina et al. J. Appl. Phys. 99, 114109 �2006�
Fermi level equilibration. 20 Furthermore, an additional component
centered at 98.2 eV appears �arrow�. Its position at
lower binding energy than the Si bulk signal suggests that Pr
silicide is formed. 21 The O 1s emission �Fig. 1�b�� exhibits a
broad feature, resulting from the overlap of Pr 2O 3, Pr silicate
and SiO 2 peaks centered at 530.1, 531.9, and 533.1 eV, respectively.
This broadening proves that the metallic Pr layer
is not stable on SiO 2 at RT. 21 The SiO 2 layer is partially
reduced by Pr and the reaction products are Pr oxide, Pr
silicate and Pr silicide. The Pr 3d spectrum shows a complex
emission pattern characteristic of rare-earth elements. Due to
initial- and final state hybridization effects, it is difficult to
assign chemical states to the features observed in the XPS Pr
3d lines. 22,23 Despite this, some insight can be gained by
comparing the shape of the Pr 3d emission at the various
preparation steps. After Pr deposition, the Pr 3d 5/2 and 3d 3/2
spin-orbit components are located at 932.5 and 952.8 eV,
respectively. These values and the observed spectrum shape
are in good agreement with those reported for pure Pr. 24 The
Pr 3d spectrum reflects only the metallic part of the deposited
Pr layer because the high binding energy of this core
level results in such a low kinetic energy of the emitted photoelectrons
that only the film surface is probed.
After air exposure, there is no evidence of Pr–Si bonds
in the Si 2p emission range anymore �Fig. 1�a��. This proves
the thermodynamic instability of Pr silicides in oxygen-rich
environments. Furthermore, the bulk Si peak shifts to its
original clean substrate position showing that band bending,
introduced in the system by Pr deposition, is reduced during
the oxidation process. Such a reversibility of the Si substrate
core level peak positions was reported before and associated
with the change of the topmost layer of the stack from a
metallic source of electrons to an electrically inactive insulator
as the deposited overlayer is oxidized. 21 The Si oxide
related peak gains intensity and appears at 101.9 eV. This is
an intermediate value with respect to bulk Si �99.3 eV� and
SiO 2 �103.3 eV�, indicating the formation of a Pr silicate
compound. 19 It can therefore be concluded that at least part
of the Pr atoms have intermixed with SiO 2. 22 The O 1s main
peak �Fig. 1�b�� is observed at 531.4 eV, consistent with Pr
silicate being the dominant specie in the dielectric. A shoulder
structure at 530 eV points to the presence of Pr 2O 3. In
the corresponding Pr 3d spectrum �Fig. 1�c�� the Pr 3d 5/2 and
3d 3/2 lines appear at 933.6 and 954.0 eV, respectively. In
addition, satellite structures on the lower binding energy side
of the main peaks show up, producing an emission pattern
typical for Pr oxides. 24 The fact that the surface sensitive Pr
3d spectrum reports only Pr oxide and no Pr silicate formation
shows that the oxide is situated on top of the Pr silicate.
After N 2 annealing, the Si 2p substrate emission peak
�Fig. 1�a�� undergoes a shift by about 0.4 eV towards higher
binding energy �99.7 eV�. This downward bend of the energy
bands in the silicon at the dielectric/Si interface is associated
with an accumulation of negative charge in the silicon
in the interface region. If this charge is compensated by
positive charge in the film, an electrical field must exist in
the dielectric. Such a potential drop over the dielectric is
observed in CV measurements described in one of the following
sections and is at most of the order of 0.2 eV. As the
118 A n n u A l R e p o R t 2 0 0 6
FIG. 2. SR-XPS Si 2p �a� and O 1s �b� photoelectron lines of the Pr silicate
film. Labels indicate incident photon energies.
Si 2p silicate component �Fig. 1�a�� is found to shift during
N 2 annealing by more than 0.2 eV, namely, by about 1 eV
towards higher binding energy �102.9 eV�, it is safe to attribute
this Si 2p silicate line position change mostly to a
modified Pr silicate stoichiometry. 25 In addition, the rather
broad full width at half maximum �FWHM� of the peak
��2.4 eV� suggests contributions from various silicate-type
compounds.
The change in the Pr silicate stoichiometry during N 2
annealing is also reflected in the shape of the O 1s spectrum.
The O 1s spectrum �Fig. 1�b�� is dominated by a Pr silicate
peak at 531.6 eV. 19 The formerly observed Pr 2O 3 peak
�530 eV� has disappeared and a shoulder on the higher binding
energy side of the main peak shows up. The latter feature
at 533 eV indicates the growth of an SiO 2-rich Pr silicate
compound during the thermal N 2 treatment �discussed in
more detail in the nondestructive depth profiling SR-XPS
study below�. The shape of the Pr 3d core level emission
�Fig. 1�c�� does not significantly change after N 2 annealing
but the main peaks shift toward higher binding energy by
�0.9 eV. Again, this shift exceeds the potential in the
dielectric ��0.2 eV� after N 2 annealing. The Pr 3d peak
position change must therefore mainly result from a modified
chemical environment of the Pr atoms on the surface of the
dielectric layer. In fact, the shift direction is consistent with
Pr silicate formation, a conclusion supported by simple
electronegativity arguments. 26 The electronegativities of Pr,
Si, and O on the Pauling scale are 1.1, 1.9, and 3.4,
respectively. 27 Thus, Pr–O–Pr bonds are substantially more
ionic than Si–O–Si bonds. If these two units are intermixed
�Pr–O–Si�, the relative covalency of Si makes Pr in Pr xSi yO z
even more ionic than in bulk Pr mO n. As a result, the XPS
binding energy of Pr in Pr xSi yO z is larger than in Pr mO n. This
trend is consistent with observations of core level shifts in
other silicate alloys. 28
B. SR-XPS depth profiling study
Figure 2 summarizes the SR-XPS data obtained for prepared
Pr silicate dielectrics on Si�100�.
The Si 2p spectrum �Fig. 2�a�� taken at the substrate
sensitive excitation of 1100 eV shows the Si substrate spin-
Downloaded 19 Jun 2006 to 134.105.104.45. Redistribution subject to AIP license or copyright, see http://jap.aip.org/jap/copyright.jsp

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
114109-4 Lupina et al. J. Appl. Phys. 99, 114109 �2006�
orbit doublet with its maximum at 99.4 eV. This signal is
accompanied by the broad Pr silicate feature at 102 eV. The
observed line shape is best fitted by assuming the presence a
SiO 2-rich ��103 eV� and a SiO 2-poor ��102 eV� silicate
phase in the dielectric layer. The peak of the SiO 2-rich Pr
silicate phase is visible as a shoulder structure in the spectrum
excited at E=1100 eV, but its intensity is strongly decreased
in the surface sensitive mode �E=350 eV�. This behavior
clearly demonstrates that the SiO 2-rich Pr silicate
phase is situated close to the Si substrate interface. At
E=350 eV, no Si substrate peak is observed anymore. The
spectrum is dominated by the Si 2p core level at 102.6 eV,
indicative of the SiO 2-poor silicate phase. Furthermore, by
measuring the photoelectron line position as a function of the
excitation energy, SR-XPS allows to study potential gradients
in the dielectric/Si system in more detail. For example,
the Si 2p bulk peak shifts towards higher binding energy
by 0.4 eV, as the excitation energy is varied from
1100 to 600 eV. As already discussed above, this demonstrates
downward band bending in the Si substrate. The resulting
potential difference across the Pr silicate dielectric is
detected in SR-XPS by the gradual shift of the Si 2p silicate
peak towards higher binding energy ��0.4 eV� as a function
of decreasing excitation energy.
It is interesting to note that the potential difference
across the dielectric film is determined below in the CV
study and amounts to at most 0.2 eV. The higher Si 2p silicate
line position variation in SR-XPS results probably from
chemical contributions, i.e., the presence of a compositionally
graded silicate layer.
The corresponding O 1s spectra are displayed in Fig.
2�b�. At E=1100 eV, the main feature is centered at
531.6 eV proving the presence of Pr–O–Si bonds. A shoulder
at the high binding energy side ��533 eV� is also clearly
visible. In accordance with the Si 2p data, we assign it to the
SiO 2-rich silicate at the interface. Changing E 0 from
1100 to 600 eV decreases the intensity of the latter feature
with respect to the main Pr silicate line. However, it is still
present in the most surface sensitive mode. This implies that
the shoulder structure of the O 1s peak is not only caused by
the SiO 2-rich Pr silicate interface layer but also by OH species
at the surface. 24 For completeness, it is noted that both
O 1s lines follow the trend observed for the Si 2p lines and
shift towards higher binding energy by �0.35 eV, when E 0
is varied from 1100 to 600 eV.
C. TEM analysis
The cross-section TEM image �Fig. 3� confirms the bilayer
structure of the dielectric deduced from SR-XPS. Three
regions can be distinguished over the Si�100� substrate. The
1.7-nm-thick bright bottom layer with a smooth interface to
Si is, given the photoemission results, attributed to the
SiO 2-rich Pr silicate compound. The darker film region with
a thickness of about 3.5 nm represents the SiO 2-poor Pr silicate
layer. The bright layer on top is glue used for TEM
sample preparation. Note that no lattice fringes are observed
in the Pr silicate region indicating an amorphous character of
FIG. 3. Cross-section TEM image of a Pr silicate film on Si�100�.
the dielectric. As recently demonstrated by combined x-ray
diffraction �XRD� and XPS studies, Pr silicate films on
Si�100� remain amorphous up to 900 °C. 29
D. Electronic structure
Any dielectric discussed as post-SiO 2 gate oxide must
exhibit valence and conduction band offsets of at least 1 eV
with respect to Si to fulfill the important requirement of low
leakage current. 30
The valence band �VB� offset can be directly derived
from photoemission measurements. 31 Figure 4�a� displays
SR-XPS VB spectra of the hydrogen terminated Si�100� substrate
and of the Pr silicate/Si�100� system measured both
with an excitation energy of 350 eV. The VB spectrum of
pure Si�100�, described in detail elsewhere, 32 acts here as
reference to determine the position of the Si VB maximum.
As indicated in Fig. 4, this value is derived from the measurement
by determining the point where the tangent of the
VB edge crosses the energy axes. In this way, it is found that
the VB maximum of the Pr silicate dielectric is displaced by
about 2.9 eV towards higher binding energy with respect to
Si. This value of the VB offset is reasonable, as it is placed
between the experimentally determined VB offsets of the
Pr 2O 3/Si�100� �1.1 eV� �Ref. 33� and SiO 2/Si�100� �4.4 eV�
�Ref. 34� system. It was recently reported in the literature
that the VB offset of �ZrO 2� x�SiO 2� 1−x silicates with respect
to Si varies as a function of composition �x ranging from 0 to
1� between the limiting values of the components SiO 2 and
ZrO 2. 35 Pr silicate layers probably follow the same trend, an
assumption supported by a previous in situ VB study of the
solid state reaction between Pr and SiO 2/Si�111�. 21 These
authors demonstrate the evolution of the Pr 4f peak structure
as a function of Pr coverage right above the VB maximum of
SiO 2. In this way, the VB offset with respect to Si is reduced.
In the VB spectrum of the Pr silicate film �Fig. 4� emission
from Pr 4f states is responsible for the main peak at 4.7 eV.
Towards lower binding energies, three further shoulders are
Downloaded 19 Jun 2006 to 134.105.104.45. Redistribution subject to AIP license or copyright, see http://jap.aip.org/jap/copyright.jsp
A n n u A l R e p o R t 2 0 0 6
119

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
114109-5 Lupina et al. J. Appl. Phys. 99, 114109 �2006�
FIG. 4. �a� VB spectra of pure Si and the Pr silicate film, �b� O 1s energyloss
feature of the SiO 2 reference sample and the Pr silicate film.
visible at 7.1, 9, and 11.2 eV. The position and shape of the
shoulder at 11.2 eV is very similar to the O 2p–Si 3s, 3p
valence band region of SiO 2, indicating that the character of
Si–O bonds does not substantially change in the Pr-silicate
film. This result is supported by the fact that electropositve
metal atoms in silica are known to create their specific oxygen
coordination polyhedra by strong interaction with the
more delocalized nonbonding O 2p orbitals of the Si–O
bonds. 36 Emission from nonbonding O 2p orbitals results in
VB spectra of clean SiO 2 in a broad unstructured peak in the
binding energy region from about 6 to 10 eV. Clearly, this
featureless VB region of SiO 2 is replaced in the Pr-silicate
film by an emission signal characterized by two shoulders
�7.1 and 9 eV�. It is interesting to note that such a two peak
structure was observed in the VB spectrum of cubic Y 2O 3, a
compound isomorphic with Pr 2O 3. Based on semiempirical
tight binding calculations, the main peak at 7.1 eV was attributed
to O 2p VB orbitals in a pure or distorted tetrahedral
cation environment and the existence of direct hopping terms
between neighboring oxygen atoms was invoked to account
for the weaker shoulder at 9 eV. This similarity suggests that
Pr atoms in Pr-silicate films locally create the same oxygen
coordination polyhedron, as encountered in the bulk oxide
compounds. 37,38 However, this preliminary interpretation of
the Pr-silicate VB spectrum needs further corroboration by
experimental and theoretical studies, as photoemission spectra
of Pr compounds are known to be complicated by hybridization
effects between Pr 4f and O 2p states. 23
The conduction band �CB� offset between Pr silicate and
Si�100� is deduced in the following. Photoelectron scattering
by creation of electron-hole pairs often allows to estimate
indirectly the band gap of insulators by XPS studies. 39,40 In
120 A n n u A l R e p o R t 2 0 0 6
FIG. 5. Schematic illustration of band offset energies of SiO 2 and Pr silicate
with respect to Si.
this procedure, the energy difference between the position of
the photoelectron peak and the onset of the corresponding
loss peak structure on its high binding energy side is taken as
a fingerprint of the insulator band gap. This is illustrated in
Fig. 4�b� using the O 1s loss region of the SiO 2 and the Pr
silicate film. In case of the 2-nm-thick SiO 2/Si�100� reference
sample, a band gap of 8.1 eV is obtained. This result
shows that the method tends to underestimate the real band
gap of about 8.9 eV whenever competing scattering processes
of lower energy occur. The same trend could be responsible
for the fact that the here deduced band gap of
5.6 eV of the Pr silicate film is by about 0.9 eV smaller than
the value recently reported for Pr silicate films on Si�111�. 41
However, this discrepancy of the reported band gap values
could also result from different Pr silicate film stoichiometries.
Hofmann et al. prepared Pr silicate films on Si�111� by
solid state reaction between Pr and SiO 2/Si�100� using a
metal/oxide ratio similar to our study. 21 A Pr silicate band
gap of about 5.5 eV can be deduced from their combined
ultraviolet photoemission spectroscopy �UPS� -inverse photoemission
electron spectroscopy �IPES� study which is close
to the value of our study. This is a reasonable value because
it is intermediate between the band gaps found for Pr 2O 3
�3.9 eV, 33 5.2 eV �Ref. 42�� and SiO 2 �9 eV�. 34 Furthermore,
the reported band gaps of rare-earth silicates generally range
from 4 to 6 eV. 43 Relying that way on the band gap measurement,
we deduce a CB offset of 1.6 eV by subtracting
from the Pr-silicate band gap of 5.6 eV the Si band gap
�1.1 eV� and the value of the above determined VB offset
�2.9 eV�. A scheme of the band discontinuities at the Pr
silicate/Si interface is drawn in Fig. 5 and the band offsets of
the SiO 2/Si system are included for comparison. 34 It is
clearly seen that Pr silicate layers on Si are characterized by
�a� substantially lower band offsets than SiO 2 films and that
�b� the band offsets are quite asymmetric, namely, 1.6 eV for
electrons and 2.9 eV for holes. Both statements are true for
many high-k oxides because �a� the band gap is roughly inversely
proportional to the dielectric constant and �b� the VB
offset is almost uniquely determined by the position of the
oxide O 2p orbitals but the CB offset is a strong function of
the metal wave functions which constitute the CB edge. 44
Downloaded 19 Jun 2006 to 134.105.104.45. Redistribution subject to AIP license or copyright, see http://jap.aip.org/jap/copyright.jsp

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
114109-6 Lupina et al. J. Appl. Phys. 99, 114109 �2006�
FIG. 6. JV characteristics of the SiO xN y reference sample and the Pr silicate
dielectric both with EOT=1.8 nm.
E. Electrical characterization
The photoemission study on the Pr silicate/Si�100� system
gives thus evidence for band discontinuities at the
dielectric/Si interface high enough to act as effective charge
injection barriers. This important insight is corroborated by
JV measurements displayed in Fig. 6. The JV curve for nitrided
SiO 2 serves as reference. The Pr silicate and nitrided
SiO 2 films have the same EOT of about 1.8 nm to allow a
direct comparison. In the depletion region of the MOS capacitor
�negative gate bias�, the JV curves show behavior
typical of a reverse biased p-n junction. 45 Here, the current
flowing through the MOS structure is limited by the reverse
biased p + -n junction induced by the electric field under the
gate oxide. The magnitude of the reverse current is governed
mainly by the minority carrier generation in bulk Si.
In the accumulation regime �positive gate bias�, the JV
curve is determined by various current conduction mechanisms
through the dielectric layer and provides a measure of
the gate dielectric quality. 4 It is seen that the leakage current
across the Pr silicate is significantly lower than that across
the SiO xN y reference layer. For example, the leakage current
measured at +1 V above the flatband voltage �V FB� is of the
order of 5�10 −5 A/cm 2 which is about three orders of magnitude
lower than in case of the high-quality nitrided SiO 2
layer.
Insight into the conduction mechanism involved is
gained from analysis of the JV curve in the accumulation
region. The measured linear relation of the logarithm of the
leakage current density versus the square root of the applied
electric field �inset in Fig. 6� points either to Schottky �S� or
Poole-Frenkel �PF� emission. 45 The current density in the
Schottky model is given by
J = A * T 2 exp� � SE 1/2 − � S
k BT �, �1�
where � S=�e 3 /4�� 0�� 1/2 , A * is the effective Richardson constant,
T is temperature, � S is the potential barrier between the
Si substrate and dielectric layer conduction band, k B is the
FIG. 7. CV curve of the Pr silicate dielectric on Si�100�.
Bolzmann constant, e is the electronic charge, E is the applied
electric field, � 0 is the dielectric constant of free space,
and � is the high frequency dielectric constant.
In the Poole-Frenkel model, the corresponding relationship
is given by
J = J 0 exp� � PFE 1/2 − � PF
k BT �, �2�
where � PF=�e 3 /�� 0�� 1/2 , J 0 is the low-field current density,
and � PF the depth of the trap potential well.
The fact that the quantity � PF is larger than � S by
a factor of two allows to discriminate between S and
PF processes by determining the slope of the ln J−E 1/2
plot. The experimental value of � obtained equals
1.35�10 −4 �cm eV� 1/2 . This is clearly closer to the theoretical
value of � S=1.8�10 −4 �cm eV� 1/2 than to the theoretical
value of � PF=3.6�10 −4 �cm eV� 1/2 pointing to the Schottky
emission as the main conduction mechanism. The potential
barrier height � S is estimated form the ordinate value at
E=0. A height of �1.4 eV is found which is in line with the
CB offset determined above by photoemission.
Figure 7 shows the CV characteristics of the Pr silicate
dielectric on Si�100�. A primary interesting point concerns
the overall shape of the measured CV curve. From the fact
that it is not streched out, a good interface quality between
the Pr silicate dielectric layer and the Si�100� substrate can
be deduced. A quantitative fit by the QITFIT software tool
results in an interface state density �D it� of the order of
10 11 cm −2 . Secondly, interesting insights can be gained from
the measured capacitance in accumulation. From this value,
an EOT of around 1.8 nm is extracted. By using the total
physical thickness of the dielectric stack, the same capacitance
value allows to calculate the effective dielectric constant
which is on the order of 11. Certainly, the effective k
value is strongly limited by the presence of the SiO 2-rich Pr
silicate layer of lower dielectric constant close to the Si substrate.
To extract the dielectric constant of the latter layer, a
simple model of two capacitors in series is assumed. The
interface SiO 2-rich Pr silicate layer and the SiO 2-poor Pr
silicate layer on top of it are modeled by the permittivities k 1
Downloaded 19 Jun 2006 to 134.105.104.45. Redistribution subject to AIP license or copyright, see http://jap.aip.org/jap/copyright.jsp
A n n u A l R e p o R t 2 0 0 6
121

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
114109-7 Lupina et al. J. Appl. Phys. 99, 114109 �2006�
and k 2, respectively. The inset in Fig. 7 shows possible combinations
of k 1 and k 2 to reproduce the measured effective k
value of 11. Using the reported dielectric constant k 2 of
�19.7 for the SiO 2-poor Pr silicate, 41 a k 1 value of �5.7 is
deduced. As this value is higher than the dielectric constant
of SiO 2 �k=3.9�, the electrical measurement is in line with
the SR-XPS study and provides support for the formation of
a SiO 2-rich Pr silicate layer at the interface. Thirdly, the flatband
voltage shift of the measured CV curve corroborates the
presence of a potential difference across the Pr silicate layer
of about 0.2 eV detected above by SR-XPS. For this purpose,
the data of the Au/Pr silicate/Si system is compared
with a simulated CV curve of a Au/SiO 2/Si MOS structure.
In the simulation of the latter, an ideal SiO 2 layer �no fixed
charge, interface dipoles, etc.� and the same Si substrate doping
concentration as in our Pr silicate study was applied.
Under the reasonable assumption that the work function of
the Au top electrode on Pr silicate is the same as on SiO 2, the
measured and simulated CV curves are expected to coincide
for the case of an ideal Pr silcate film. However, Fig. 7
clearly shows that the flatband voltage of the Au/Pr xSi yO z/Si
system is shifted with respect to the Au/SiO 2/Si structure by
�0.22 V towards negative voltage. It is important to note
that magnitude and direction of this flatband voltage shift
correlate well with the potential gradient across the Pr silicate
dielectric layer detected by SR-XPS. Clearly, a possible
microscopic origin of these experimental findings is the presence
of positive fixed charge in the Pr silicate layer. However,
as pointed out in more detail in the next section, the
physics of electrically active defect sites in the Pr silicate/Si
system is more complicated and further contributing factors
can not be ruled out at present.
F. Ab initio calculations
In order to understand the origin of the positive charge in
the silicate films, we have analyzed the formation and the
electrical properties of various point defects in Pr silicates.
The details of this calculations will be given elsewhere; 46
here we summarize the main ideas and results sketching the
most probable scenarios of fixed charge formation.
Pr silicate can be regarded as a mixture
n�Pr 2O 3�m�SiO 2� with Si–O–Si, Pr–O–Si, and Pr–O–Pr
bonds. To describe theoretically point defect formation in
these bonding configurations, we use SiO 2 �n=0�, G-type
Pr 2Si 2O 7 �m=2n� �Ref. 47�, and cubic Pr 2O 3 �m=0� as
model substances, respectively. The current discussion of
nonstoichiometric silicate is based solely on the dependence
of point defect formation energies on the chemical potential
of oxygen, ��O�. The coexistence of various stoichiometries
of the Pr silicate in our system indicates that during the silicate
formation at high temperature the chemical potential
��O� is situated between the equilibrium of stoichiometric
Pr 2Si 2O 7 and SiO 2 and the equilibrium of stoichiometric
Pr 2Si 2O 7 and Pr 2O 3. We assume that this range of ��O�
roughly reflects the change of ��O� over the composition of
our Pr silicate system.
122 A n n u A l R e p o R t 2 0 0 6
In most of this range, it is found that the formation en-
3+
ergy of Pr interstitial PrI is negative: it varies from about
−1.5 eV at the Pr oxide end to about +0.5 eV at the Si oxide
3+
end. A negative PrI formation energy means that it is energetically
more favorable to dissolve some Pr atoms as triple
positively charged interstitials in the silicate. In other words,
the silicate may be enriched in SiO2 by the oxidation of Si
whereby the required oxygen not only stems from the ambient
but to certain extent also from the reduction of Pr2O3 moieties in the Pr silicate. This is described by the following
relationship
2Pr 2Si 2O 7 + 3Si → 2Pr I 3+ + Pr2Si 2O 7:SiO 2, �3�
where Pr2Si2O7:SiO2 stands for Pr2Si2O7 slightly enriched
in SiO2. As the silicate composition changes towards the
SiO2 end, the energy gain from Pr2O3 reduction decreases
and eventually changes sign to become a loss of 0.5 eV at
the SiO2 limit. Over the same range of ��O�, the formation
2+
energies of oxygen vacancies OV and valence alternated �un-
+
deroxidized� Pr atoms PrVA are small �around +0.5 eV� in
Pr2O3. The latter defect corresponds formally to a half oxygen
vacancy. One would expect a comparable energy cost
when an oxygen deficiency defect is created at a Pr-rich site
in the network of the silicate, that is, at a site where the
removal of the oxygen atom does not break any covalent
bonds with Si.
3+ 2+ +
Can some of these defects �PrI , OV , PrVA�
be responsible
for the positive fixed charge detected by photoemission
3+
and CV studies in our Pr silicate film? The energy of PrI decreases �by approximately 0.2 eV� when the defect moves
from Pr2Si2O7 to Pr2O3. Therefore, one expects that Pr interstitials
created during mixing diffuse away across the Pr oxide
to the surface of the film, where they are oxidized by
oxygen from the ambient. The oxygen vacancies are expected
to become eventually filled by oxygen as the ultrathin
film interacts with oxygen from the ambient. But underoxi-
+
dized praseodymium, PrVA, may survive because in order to
become oxidized, such defects would need to pair into oxy-
+
gen vacancies. Therefore, we suspect that PrVA in
Pr2O3—rich Pr silicates may be responsible for the positive
charge observed in the films. Another possibility that is
pointed to by the results of our calculations is that the positive
charge is trapped in the Si-rich region of the Pr silicate
in form of over-coordinated oxygen atoms. This model will
be discussed in detail in a separate publication. 46
IV. CONCLUSIONS
We demonstrated that the solid state reaction of Pr with
native SiO 2 layers on Si�100� can be tailored to prepare compositionally
graded Pr silicate dielectrics with good interface
properties, low leakage currents, and appropriate k values.
These results along with the reported good thermal stability
against crystallization and phase separation make Pr silicate
films attractive for high-k applications. 29 Further work is under
way to optimize the system �i.e., achieve EOT values
below 1 nm �Ref. 48�� and integrate the alternative high-k
dielectric in conventional complementary metal-oxide semiconductor
�CMOS� process technology. 49,50
Downloaded 19 Jun 2006 to 134.105.104.45. Redistribution subject to AIP license or copyright, see http://jap.aip.org/jap/copyright.jsp

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
114109-8 Lupina et al. J. Appl. Phys. 99, 114109 �2006�
1
E. J. Nowak, IBM J. Res. Dev. 46, 169 �2002�.
2
Y. Taur, IBM J. Res. Dev. 46, 213 �2002�.
3
International Technology Roadmap for Semiconductors, 2004 Update,
http://public.itrs.net.
4
H. R. Huff and D. C. Gilmer, High Dielectric Constant Materials
�Springer, New York, 2005�.
5
E. P. Gusev, E. Cartier, D. A. Buchanan, M. Gribelyuk, M. Copel, H.
Okorn-Schmidt, and C. D’Emic, Microelectron. Eng. 59, 341 �2001�.
6
C. C. Fulton, T. E. Cook, Jr., G. Lucovsky, and R. J. Nemanich, J. Appl.
Phys. 96, 2665 �2004�.
7
G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys. 87, 484
�2000�.
8
H. Ono, Appl. Phys. Lett. 78, 1832 �2001�.
9
Handbook of Semiconductor Cleaning Technology, edited by W. Kern
�Noyes, Park Ridge, New York, 1993�.
10
D. Schmeisser, P. Hoffmann, and G. Beuckert, in Materials for Information
Technology, Devices, Interconnects and Packaging, Engineering Materials
and Processes, edited by E. Zschech, C. Whelan, and T. Mikolajick
�Springer, New York, 2005�.
11
NIST Electron Inelastic-Mean-Free-Path Database, http://www.nist.gov/
srd/nist71.htm, and references therein.
12
G. Apostolopoulos, G. Vellianitis, A. Dimoulas, J. C. Hooker, and T. Conrad,
Appl. Phys. Lett. 84, 260 �2004�.
13
M. Bockstedte, A. Kley, J. Neugebauer, and M. Scheffer, Comput. Phys.
Commun. 107, 187 �1997�.
14
A. Fissel, J. Dabrowski, and H. J. Osten, J. Appl. Phys. 91, 8986 �2002�.
15
D. M. Ceperley and B. J. Alder, Phys. Rev. Lett. 45, 567 �1980�.
16
J. P. Perdew and A. Zunger, Phys. Rev. B 23, 5048 �1981�.
17
D. R. Haman, Phys. Rev. B 40, 2980 �1989�.
18
G. B. Bachelet, D. R. Hamann, and M. A. Schlüter, Phys. Rev. B 26, 4199
�1982�.
19
J. F. Moulder, W. F. Stickle, P. E. Sobol, and K. D. Bomben, Handbook of
X-ray Photoelectron Spectroscopy �Perkin Elmer, Eden Prairie, 1992�.
20
H. Lüth, Surfaces and Interfaces of Solids �Springer-Verlag, Berlin, 1993�.
21
R. Hofmann, W. A. Henle, H. Öfner, M. G. Ramsey, F. P. Netzer, W.
Braun, and K. Horn, Phys. Rev. B 47, 10407 �1993�.
22
D. Schmeisser, Mater. Sci. Semicond. Process. 6, 59 �2003�.
23
A. Kotani and H. Ogasawara, J. Electron Spectrosc. Relat. Phenom. 60,
257 �1992�.
24
S. Lütkehoff, M. Neumann, and A. Slebarski, Phys. Rev. B 52, 13 808
�1995�.
25
G. B. Rayner, D. Kang, Y. Zhang, and G. Lucovsky, J. Vac. Sci. Technol.
B 20, 1748 �2002�.
26
T. L. Barr, J. Vac. Sci. Technol. A 9, 1793 �1991�.
27
L. Pauling, The Nature of the Chemical Bond and the Structure of Molecules
and Crystals �Cornell University Press, Ithaca, NY, 1960�, p. 93.
28
T. Gougousi, M. J. Kelly, D. B. Terry, and G. N. Parsons, J. Appl. Phys.
93, 1691 �2003�.
29
G. Lupina, T. Schroeder, J. Dabrowski, Ch. Wenger, A. Mane, G. Lippert,
H.-J. Müssig, P. Hoffmann, and D. Schmeisser, Appl. Phys. Lett. 87,
092901 �2005�.
30
J. Robertson, J. Vac. Sci. Technol. B 18, 1785 �2000�.
31
S. Hüfner, Photoelectron Spectroscopy �Springer-Verlag, Berlin, 2003�.
32
L. Ley, S. Kowalczyk, R. Pollak, and D. A. Shirley, Phys. Rev. Lett. 29,
1088 �1972�.
33
H. J. Osten, J. P. Liu, and H. J. Müssig, Appl. Phys. Lett. 80, 297 �2002�.
34
G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys. 89, 5243
�2001�.
35
G. Lucovsky, G. B. Rayner, Y. Zhang, C. C. Fulton, and R. J. Nemanich,
Appl. Surf. Sci. 212–213, 563 �2003�.
36
N. F. Mott, Adv. Phys. 26, 363 �1977�.
37
B. F. Hoskins and R. L. Martin, J. Chem. Soc. Dalton Trans. 1975, 576.
38
R. L. Martin, J. Chem. Soc. Dalton Trans. 1974, 1335.
39
F. G. Bell and L. Ley, Phys. Rev. B 37, 8383 �1988�.
40
S. Miyazaki, J. Vac. Sci. Technol. B 19, 2212 �2001�.
41
A. Sakai, S. Sakashita, S. Zaima, and S. Miyazaki, Appl. Phys. Lett. 85,
5322 �2004�.
42
S. Kimura, F. Arai, and M. Ikezawa, J. Electron Spectrosc. Relat. Phenom.
78, 135 �1996�.
43
F. P. Netzer, J. Phys.: Condens. Matter 7, 991 �1995�.
44
J. Robertson, Appl. Surf. Sci. 190, 2 �2002�.
45
S. M. Sze, Physics of Semiconductor Devices �Wiley, New York, 1981�.
46
J. Dabrowski, A. Fleszar, G. Lippert, G. Lupina, A. Mane, and Ch.
Wenger, in Topics in Applied Physics: Rare earth oxide thin films: growth,
characterization, and applications, edited by M. Fanciulli and G. Scarel
�Springer, Berlin, 2006�.
47
Y. I. Smolin and Y. F. Shepelev, Acta Crystallogr., Sect. B: Struct. Crystallogr.
Cryst. Chem. 26, 484 �1970�.
48
T. Schroeder, G. Lupina, J. Dabrowski, Ch. Wenger, A. Mane, G. Lippert,
and H.-J. Müssig, Appl. Phys. Lett. 87, 022902 �2005�.
49
A. U. Mane, Ch. Wenger, G. Lupina, T. Schroeder, P. Zaumseil, G. Lippert,
G. Weidner, and H.-J. Müssig, Microelectron. Eng. 82, 148 �2005�.
50
A. U. Mane, T. Schroeder, Ch. Wenger, P. Zaumseil, G. Lippert, G.
Weidner, and H.-J. Müssig, J. Electrochem. Soc. 152, C399 �2005�.
Downloaded 19 Jun 2006 to 134.105.104.45. Redistribution subject to AIP license or copyright, see http://jap.aip.org/jap/copyright.jsp
A n n u A l R e p o R t 2 0 0 6
123

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
Residual stress in Si nanocrystals embedded in a SiO 2 matrix
T. Arguirov, a� T. Mchedlidze, and M. Kittler
IHP, Im Technologiepark 25, D-15236 Frankfurt (Oder), Germany and IHP/BTU Joint Lab,
Konrad Wachsmann Allee 1, D-03046 Cottbus, Germany
R. Rölver, B. Berghoff, M. Först, and B. Spangenberg
Institute of Semiconductor Electronics, RWTH Aachen University, D-52074 Aachen, Germany
�Received 23 March 2006; accepted 13 June 2006; published online 2 August 2006�
Multiple quantum wells consisting of alternating Si and SiO 2 layers were studied by means of
Raman scattering. The structures were fabricated by the remote plasma enhanced chemical vapor
deposition of amorphous Si and SiO 2 layers on quartz substrate. The structures were subjected to a
rapid thermal annealing procedure for Si crystallization. The obtained results suggest that the Si
layers consist of nanocrystals embedded in an amorphous Si phase. It was found that the silicon
nanocrystals inside 2 nm thin layers are under high residual compressive stress. Moreover, the
metastable Si III phase was detected in these samples supporting the presence of large compressive
stresses in the structures. The compressive stress could be relaxed upon local laser annealing.
© 2006 American Institute of Physics. �DOI: 10.1063/1.2260825�
Multiple quantum wells �MQWs� consisting of alternating
Si and SiO 2 layers attract considerable interest due to
their luminescent properties and possibilities of band gap
adjustment, related mainly to carrier confinement effects. 1
The MQW structures are fabricated by deposition of alternating
amorphous silicon �a-Si� and silicon dioxide �SiO 2� layers.
An appropriate heat treatment is applied after deposition
for recrystallization of a-Si. The amorphous-to-crystalline
phase transition in MQWs occurs through random nucleation
of crystalline Si �c-Si� clusters surrounded by a-Si and is
influenced by stress fields existing in the system. It was reported
that nucleation of c-Si is suppressed near the Si/SiO 2
interface in the adjacent 0.5–1.0 nm of the Si layer. 2 A careful
analysis of the crystallization process was presented in
Ref. 3, where the authors showed that the major factor restricting
the crystallization of the nanolayers is the strain
exerted by the SiO 2 to the Si layers due to the lattice mismatch
of the materials. The screening distance after which
the c-Si nucleation centers in the a-Si phase are not influenced
by the Si/SiO 2 interface was estimated to be about
2.5 nm. Consequently, an equilibriumlike furnace annealing
will not allow a complete crystallization of Si nanolayers
with thicknesses less than 5 nm due to the influence of the
interfaces. The rapid thermal annealing �RTA� procedure
should allow heating of the a-Si nanolayers directly. Therefore,
proper adjustment of the RTA procedure may minimize
influence of interfaces. However, compressive stress during
RTA can be generated in the layers due to difference in the
expansion coefficients of Si and SiO 2, and this stress may
influence the crystallization. The aim of the present work
was an investigation of stresses in the MQW samples during
RTA procedure.
Stacks consisting of ten periods of Si/SiO 2 layers were
deposited on quartz substrates by remote plasma enhanced
chemical vapor deposition. 4 The thickness of a-Si layers was
varied in the range from 2 to 5 nm, and the thickness of
SiO 2 layers was kept at 3 nm for all MQW samples. The
RTA procedure was carried out at 1100 °C for 30 s. For
a� Electronic mail: arguirov@tu-cottbus.de
124 A n n u A l R e p o R t 2 0 0 6
APPLIED PHYSICS LETTERS 89, 053111 �2006�
better heat absorption, the side of the samples with deposited
layers was brought in thermal contact with a silicon wafer
during the RTA process. The heating of the structures is then
caused by light directly absorbed in the layers and by the
heat exchange between the silicon wafer and the sample. An
additional annealing step at 400 °C in forming gas was conducted
to further improve the interface quality and for hydrogen
passivation of the defects. The MQW samples were
analyzed by micro-Raman measurements on a Dilor XY
triple spectrometer equipped with frequency doubled
Nd:YVO 4 laser �Coherent Verdi� at a wavelength of
532 nm. The illuminated spot was 1 �m in diameter, and the
power of the laser during the measurements was kept below
4 mW to avoid unintentional heating of the structures. The
absolute positions of the Raman peaks were determined by
comparison with the spectrum of a Hg calibration lamp. To
investigate an influence of local annealing by laser beam,
single spot on the sample surface with 2 nm thick a-Si layers
was subjected to illumination by the probe beam using high
laser powers.
All MQW samples showed blueshifted band edge photoluminescence,
which can be attributed to quantum confinement
of charge carriers in nanocrystalline Si �nc-Si�. 4 The
Raman spectra in Fig. 1 show that all measured samples
contain a-Si and nc-Si fractions. The scattering from amorphous
material has a maximum at about 480 cm −1 and can be
deconvoluted in three broad peaks 5 �Fig. 1, inset�. The sharp,
asymmetric peak at higher wavenumbers is associated with
nc-Si. Changes in the shape of the spectra with the changes
in the Si layer thickness are mainly related to the contribution
of nc-Si phase. It is not possible to determine exactly a
value of crystallinity, i.e., the absolute volume fraction of
nc-Si and a-Si in the layers, because the Raman scattering
cross section for nc-Si is strongly dependent on the size of
the nanocrystals. 6 As a rough estimate for this value, one can
use a ratio of integrated intensities for signals related to nc-Si
and a-Si. We obtained crystallinity of �5% for the 2 nm
thick layers and �25% for the 5 nm thick layers. A comparison
between the volume fraction estimated from transmission
electron microscopy images and that obtained from the
0003-6951/2006/89�5�/053111/3/$23.00 89, 053111-1
© 2006 American Institute of Physics
Downloaded 01 Sep 2006 to 141.43.75.152. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
053111-2 Arguirov et al. Appl. Phys. Lett. 89, 053111 �2006�
FIG. 1. Raman spectra from MQW samples, thickness of Si layers is indicated
on the related curves. The position of Raman peak in bulk Si is
indicated by a doted line c-Si. The inset shows fitting of the experimental
spectra with three peaks related to the amorphous material and the residual
peak related to nc-Si.
Raman results on similar samples showed that latter gives an
overestimation of the volume fraction within �10%.
Figure 2 compares the dependencies of positions and of
widths of nc-Si Raman peaks on the layer thickness with the
results of the calculations. 7,8 The peak width �full width at
half maximum �FWHM�� follows the theoretical predictions
quite well. The asymmetry of the nc-Si peak �Fig. 1, inset�
can originate from scatter in the sizes of the nanocrystals
and/or from the variation of their residual stress. Since the
dependence of the FWHM corresponds well to that predicted
theoretically, we suppose that the main source of asymmetry
is homogeneous broadening. Contrary to the theoretical
predictions, 7,8 a shift to higher Raman frequencies in the
peak position was observed upon decreasing the layer thickness.
Similar results were reported previously. 9 It was
shown 10 that the width of the Si Raman peak is barely influenced
by compressive stress, although the position of the
FIG. 2. Symbols represent the experimental data for the position shift �a�
and FWHM �b� of the nc-Si related peak. The peak shift is given relative to
the position of the crystalline bulk Si material. The model calculations are
presented by dashed �Ref. 7� and dotted �Ref. 8� lines.
FIG. 3. Change of the gap between Raman peak positions �Pos�c-Si�
−Pos�nc-Si�� detected in the sample with 2 nm layers with the increase of
power of the probe beam; the line serves as a guide for the eye. Inset: Si III
peak detected before �solid line� and after �dotted line� laser annealing.
peak maximum is strongly shifted. Therefore we attributed
the observed anomalous behavior to a residual hydrostatic
stress exerted from the a-Si phase on the nc-Si grains during
RTA.
We investigated response of the system to the laser annealing.
For this, the power of the probing laser was increased
stepwise at one spot from 4 to 120 mW. The exposure
time was varied in order to keep the exposition constant
for various laser powers. It should be noted that in contrast to
the RTA, the laser annealing is a steady state process where
the steady state conditions are reached within several
microseconds. 11 Thus the crystallization conditions are determined
mainly by the acting laser power and not by the exposure
time.
Figure 3 shows change of a gap between Raman peak
positions �Pos�c-Si�−Pos�nc-Si�� with the increase in the applied
laser power. The position of the nc-Si peak in the spectra
was determined by subtracting the reference spectrum,
i.e., the spectrum measured at 120 mW from all other spectra.
This procedure highlighted the nc-Si peak, because the
a-Si related scattering was not shifted and does not contribute
to the resulting curve. As seen in Fig. 3, a shift in the
Raman peak position to lower wavenumbers was observed
upon increasing the laser power. After the peak reached a
value of �10 cm−1 below the position for bulk c-Si, the shift
leveled off. To exclude possible influence of local temperature
change on the Raman shift and the peak width, 10,12,13 we
measured the Raman spectrum at the low laser power at the
same spot after the laser annealing. The spectral shapes at the
high and the low power measurements were identical within
the experimental error. This fact suggests that the change in
the nc-Si peak position in our experiment is related to the
stress relaxation caused by annealing and not to changes in
experimental conditions.
The final position for the nc-Si peak roughly corresponds
to that expected for �2 nm size crystallites of relaxed
nc-Si. 7,8 Then from the obtained change in the peak position
caused by laser annealing ��10 cm−1� and by applying the
approximation for influence of stress in c-Si, 14 the compressive
stress in the initial state of nc-Si after RTA was estimated
as �5 GPa.
Downloaded 01 Sep 2006 to 141.43.75.152. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp
A n n u A l R e p o R t 2 0 0 6
125

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
053111-3 Arguirov et al. Appl. Phys. Lett. 89, 053111 �2006�
As an additional confirmation for the presence of high
compressive stresses in the system, a peak at about 180 cm −1
was observed in the low energetic part of the Raman spectrum
in the samples before laser annealing �Fig. 3, inset�.
This peak can be related to the metastable Si III phase. 5,15
The Si III phase is formed by expansion and cooling of the
high-temperature, high-pressure stable metallic silicon
phase—Si II �Refs. 15 and 16�—and requires compressive
stresses of about 10 GPa at elevated temperatures. 16 Therefore,
the presence of Si III phase confirms that the silicon
was exposed to high compressive stresses during RTA. Si III
is a metastable phase and transforms to Si I by relaxation of
the compressive stress during annealing. Such relaxation of
the Si III related peak was indeed observed in the Raman
spectra upon the laser treatment. The inset in Fig. 3 shows
that the peak related to the Si III phase is strongly reduced
after the laser annealing. The dependence of the Raman peak
position on the Si layer thickness �Fig. 2�a�� probably should
be attributed to a screening of the compressive stress by
a-Si material in thicker Si layers.
In summary, RTA annealed MQWs showed an anomalous
blueshift of nc-Si related Raman peak on decreasing of
Si layer thickness. Such behavior could be ascribed to residual
compressive stresses in the layers. This supposition
was supported by presence of high-pressure Si III phase in
the samples after RTA. Laser annealing led to redshift of
126 A n n u A l R e p o R t 2 0 0 6
nc-Si Raman peak and suppression of Si III related peak.
This indicates relaxation of stress by local laser annealing.
This work has been partly funded by the European Commission
under the frame of SINANO �IST-506844� and by
the BMBF, Germany �Contract 03SF0308�.
1
Y. Rui, D. Chen, J. Xu, Y. Zhang, L. Yang, J. Mei, Z. Ma, Z. Cen, W. Li,
L. Xu, X. Huang, and K. Chen, J. Appl. Phys. 98, 033532 �2005�, and
references therein.
2
J. Gonzalez-Hernandez and R. Tsu, Appl. Phys. Lett. 42, 90 �1983�.
3
M. Zacharias and P. Streitenberger, Phys. Rev. B 62, 8391 �2000�.
4
R. Rölver, M. Först, O. Winkler, B. Spangenberg, and H. Kurz, J. Vac. Sci.
Technol. A 24, 141 �2006�.
5
V. Domnich, Yu. Gogotsi, and S. Dub, Appl. Phys. Lett. 76, 2214 �2000�.
6
R. Tsu, J. Gonzalez-Hernandez, S. S. Chao, S. C. Lee, and K. Tanaka,
Appl. Phys. Lett. 40, 534 �1982�.
7
Ch. Ossadnik, S. Veprek, and I. Gregora, Thin Solid Films 337, 148
�1999�.
8
W. Cheng and S. Ren, Phys. Rev. B 65, 205305 �2002�.
9
L. Khriachtchev, O. Kilpelä, S. Karirinne, J. Keränen, and T. Lepistö,
Appl. Phys. Lett. 78, 323 �2001�.
10
S. Kouteva-Arguirova, Tz. Arguirov, D. Wolfframm, and J. Reif, J. Appl.
Phys. 94, 4946 �2003�.
11
M. Lax, J. Appl. Phys. 48, 3919 �1977�.
12
H. W. Lo and A. Compaan, J. Appl. Phys. 51, 1565 �1980�.
13
M. Balkanski, R. F. Wallis, and E. Haro, Phys. Rev. B 28, 1928 �1983�.
14
I. De Wolf, Semicond. Sci. Technol. 11, 139 �1996�.
15
A. Kailer, Yu. Gogotsi, and K. Nickel, J. Appl. Phys. 81, 3057 �1997�.
16
J. Hu, L. Merkle, C. Menomi, and I. Spain, Phys. Rev. B 34, 4679 �1986�.
Downloaded 01 Sep 2006 to 141.43.75.152. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
1.5 µm Emission from a Silicon MOS-LED Based on a Dislocation Network
M. Kittler 1,2 , M. Reiche 3 , X. Yu 1,2 , T. Arguirov 1,2 , O.F. Vyvenko 2,4 , W. Seifert 1,2 ,
T. Mchedlidze 2 , G. Jia 2 and T. Wilhelm 3
Abstract
A novel Si MOS-LED is demonstrated, which is fully
compatible with Si technology. It is based on a dislocation
network fabricated by wafer direct bonding. Light emission
at 1.5 µm was observed when the network was near the
Si/SiO 2 interface close to/inside the accumulation layer
induced by the gate voltage.
Introduction
On-chip optical interconnects will be essential for future
integrated circuits. Many key components that can be
integrated on the chip have already been demonstrated by Si
technology. A CMOS-compatible electrically pumped Sibased
light emitter is still lacking. Different approaches for
light emitters have been studied, e.g. (1-6). The desired light
emitter should not only exhibit a high luminescence
efficiency at room temperature (RT), but also be spatially
confined and emit at about 1.5 or 1.3 µm.
LEDs based on Er-doped layers consisting of Si nanoparticles
embedded in Si oxide (7) or Si nitride (4), respectively, are
known to emit at 1.55 µm. However, a rather high bias
voltage is needed to cause efficient electroluminescence
(EL). Another LED exhibiting 1.5 µm light emission with a
RT efficiency > 0.1% (8) makes use of the luminescent
properties of dislocations introduced by plastic deformation.
Furthermore, also Si nanowires containing crystal
defects/dislocations were observed to produce a dominating
1.5 µm light emission at RT (9). In order to utilize
dislocations as active elements in devices, their wellcontrolled,
reproducible formation is an essential
prerequisite.
Recently, it has been demonstrated that Si wafer bonding
allows the reproducible formation of dislocation networks
that exhibit a dominating light emission at the desired
wavelength of about 1.5 µm (6). EL at about 1.5 µm from a
p-n junction formed by direct bonding of p- and n-type
wafers was already observed a few years ago (10). The
present paper reports an efficient light emission at 1.5 µm
from a MOS-LED containing a regular dislocation network.
1-4244-0439-8/06/$20.00 © 2006 IEEE
IeDM technical Digest, 845 (2006)
1
IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
2
IHP/BTU Joint Lab, Konrad-Wachsmann-Allee 1, 03046 Cottbus, Germany
3
MPI für Mikrostrukturphysik, Weinberg 2, 06120 Halle, Germany
4 St. Petersburg State University, Uljanovskaja 1, 198904 St. Petersburg, Russia
The light emission was observed when the dislocation
network was within/close to the accumulation layer formed
by the gate bias.
Dislocation-related luminescence in silicon
A typical luminescence spectrum for dislocated Si with the
quartet of defect-related D1-D4 lines (11) is shown in the
insert of Fig. 1. The D1 and D3 lines appear at about 1.5 or
1.3 µm, respectively, i.e. at the required wavelengths.
For application of dislocations as active parts of LEDs their
formation must be reproducible regarding both structure and
location. Si wafer direct bonding using hydrophobic surfaces
is a promising technique to form a regular dislocation
network. Details of the bonding procedure used are described
in (12). An example TEM micrograph of a periodic
dislocation network consisting of closely spaced screw and
edge dislocations is represented in Fig. 2. The structure of a
dislocation network, i.e., density and type of the dislocations
Fig. 1: Example of impact of misorientation/structure on the luminescence
spectra of dislocation networks.
(A) Twist angle of α = 9°, dominating D1 line; (B) twist angle of α = 8.2°,
dominating D3 line. Same tilt angle of β = 0.2° in both cases. (C)
Appearance of D1 line for the network shown in Fig. 2. The insert shows a
typical spectrum of dislocated Si, exhibiting the D1-D4 lines formed by
dislocations and the BB line.
A n n u A l R e p o R t 2 0 0 6
127

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
Fig. 2: TEM plan view of a periodic dislocation network fabricated by direct
bonding of (100) Si wafers. The directions of screw and edge dislocations
are indicated. Note, for this network only the D1-line was detected (see
spectrum C in Fig. 1).
formed, depends on the misorientation angles for twist, α,
and tilt, β, during wafer bonding. The dislocation network
can be well reproduced by appropriately adjusting the angles.
Fig. 1 demonstrates that the luminescence spectra strongly
correlate with the structure of the dislocation network. Hence,
the luminescence spectrum can be tailored by the
misorientation angles in a controlled manner and dominance
of either D1 or D3 radiation can be attained.
A layer transfer treatment allows positioning the dislocation
network close to the wafer surface, e.g. (13). The network
can be placed at depths ranging from less than 50 nm (see
Fig. 6) to micrometers below the surface.
Fig. 3: EL of a MOS tunnel diode on p-Si exhibiting BB luminescence at
300 K with an efficiency > 0.1 %. The insert shows the dependence of the
EL signal on the current level.
128 A n n u A l R e p o R t 2 0 0 6
Silicon MOS-LED
EL with emission of the band-to-band (BB) line at about
1.1 µm has been reported from a MOS tunnel diode
prepared on n-type Si (14). Under positive gate bias electrons
EL intensity (a.u.)
300 K
EL intensity (a.u.)
900 1000 1100 1200 1300 1400
Wavelength (nm)
1000 1200 1400 1600
Wavelength (nm)
5
60 mA
20
10
(a) (b)
Fig. 4: Scheme of MOS-LED, (a) p-type material with dislocation network,
capable of yielding both dislocation and BB luminescence, (b) n-type Si
without network yielding BB luminescence only.
are attracted, building an accumulation layer close to the
Si/oxide interface, and a hole current is formed by tunneling
through the oxide layer.
Also MOS tunnel diodes on p-type Si yield comparable
results. Fig. 3 shows the EL spectrum observed at RT
exhibiting the BB line with an efficiency > 0.1%. As shown
in the insert the EL intensity increases sub-linearly with
increasing tunneling current. The basic processes in MOS-
LEDs on n-type and p-type Si, respectively, are schematically
represented in Fig. 4.
Dislocation-based MOS-LED
When a dislocation network with appropriate structure is
positioned near the Si/oxide interface, close to/within the
accumulation layer, the radiative recombination is dominated
by the D1 line at about 1.5 µm instead of the BB line.
280000
260000
EL intensity (a.u.)
240000
220000
200000
180000
160000
140000
Current (A)
0,01
1E-3
1E-4
1E-5
1E-6
1E-7
1.1
Energy (eV)
1.0 0.9
0 1
Voltage (V)
2 3
120000
1000 1100 1200 1300 1400 1500 1600 1700
Wavelength (nm)
Fig. 5: Electroluminescence at 80 K of a MOS-LED (gate area of about
7.9 x 10 -3
cm 2
) under negative gate bias with 1.5 µm radiation caused by the
dislocation network near the Si/oxide interface. The intensity is found to
increase sub-linearly with increasing tunneling current as seen from the
spectra measured at 2, 5 and 8 mA, respectively. The insert represents the
I-V characteristic of the LED at 300K.
0.8
8 mA
5
2

Fig. 6: XTEM of the MOS-LED consiting of a 134 nm Ti layer on 1.8 nm Si
oxide. The dislocation network is positioned in a depth of about 45 nm and
was fabricated by direct bonding of p-type Si wafers, ρ ~ 10 Ωcm, with
(100) orientation.
This is clearly seen from the EL spectra shown in Fig. 5. The
MOS-LED on p-type Si, with the dislocation network at a
depth of about 45 nm, consisted of a 134 nm thick Ti gate
(7.9 x 10 -3 cm 2 ) deposited on 1.8 nm thick Si oxide, see TEM
micrographs shown in Fig. 6. The I-V characteristic is given
in the insert of Fig. 5. The tunneling current increases with
increasing gate voltage, leading to an enhancement of the EL
intensity.
To estimate the efficiency, we compared the EL of a Si p-n
diode under forward bias with that of the MOS-LED (Fig. 7),
obtaining a value of about 0.1% for the 1.5 µm emission
generated by the MOS-LED at 80 K. Fig. 8 shows that
increasing the temperature (T) from 80 to 210 K causes a
red-shift of the D1 line and a reduction of the EL intensity /
EL power intensity (pW nm -1
)
N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
12
10
8
6
4
2
1.6 1.4
Wavelength (µm)
1.2 1
MOS-LED
p-n diode
0.6 µW /A 1.35 µW/A
0
0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
Energy (eV)
Fig. 7: Comparison of the EL internal quantum efficiencies of a Si p-n diode
and the MOS-LED. The p-n diode was measured at RT under forward bias,
yielding an efficiency of 0.15%. For the MOS-LED, the estimated efficiency
at 80K was about 0.1%.
EL intensity (a.u.)
W a ve le ng th (µm )
1 .7 1.6 1 .5 1.4 1 .3 1.2 1 .1
T = 21 0 K
T = 8 0 K
0.7 0.8 0.9 1.0 1.1 1.2
Energy (eV )
Fig. 8: Comparison of EL of the MOS-LED at 80 and 210 K. The EL data
are normalized on tunneling current values.
efficiency by a factor of about 2. Increase of temperature to
300 K was found to further reduce the EL efficiency.
Nevertheless, we suppose that sufficient 1.5 µm
luminescence at 300 K is achievable with dislocation
networks, since clearly detectable D1 emission at 300 K
(efficiency > 0.1%) was demonstrated already for a p-n LED
containing a dislocation network.
Prospects for future improvements
We suppose that elimination of non-radiative recombination
channels, such as states at the Si/oxide interface, will
significantly improve the efficiency. The reported upper limit
of efficiency of radiative recombination in Si at RT is about
20% (15).
Utilization of gate dielectrics with smaller band-gap, e.g. Hf
oxide, and stacks of multiple parallel networks could enhance
efficiency further.
Moreover, a bias voltage applied to the network significantly
enhances the D-line emission in the cathodoluminescence
mode (Fig. 9a), probably due to modification of the
occupancy of the dislocation defect levels (16,17).
Accordingly, a combination of a MOS diode or a p-n junction
under forward bias, for injection of excess carriers with
additional bias voltage applied to the network could be an
alternative LED design (Fig. 9b). This might even allow
modulation of the LED via the bias voltage.
We also observed that, for the same structure of the
dislocation network, the intensity of the D1 luminescence is
significantly enhanced (about three times) by a trace of
oxygen accommodated at the bonded interface (18). Oxygen
exhibits this positive influence when its content is just above
the SIMS detection limit and when no Si oxide precipitates
are observed at the bonded interface. Hence, controlled
placement of a trace of oxygen (Si oxide) before wafer direct
bonding may help to increase the efficiency of a dislocationbased
light emitter.
A n n u A l R e p o R t 2 0 0 6
129

N A C H D R U C K E A U S G E W Ä H L T E R P U b L i K A T i o N E N – R E P R i N T S o F S E L E C T E D P U b L i C A T i o N S
Fig. 9: Influence of a bias voltage: (a) Enhancement of D-line CL emission
caused by a bias applied to the dislocation network. The maximum intensity
appears at about 2.5 V. The insert represents the sample configuration. (b)
Suggested LED design to exploit this effect.
130 A n n u A l R e p o R t 2 0 0 6
Summary
A novel Si LED for IR emission has been demonstrated,
which does not require additional Er doping and is fully
compatible with Si technology. According to our estimates
and the supposed improvements it offers the capability for an
efficiency around 1% at RT. We consider the proposed
network-based MOS-LED a promising concept for the
realization of a Si-based on-chip light emitter.
Acknowledgements
(a)
(b)
The authors would like to thank G. Weidner for X-TEM.
Parts of this work have been supported by the
Volkswagenstiftung Hannover, Germany.
References
(1) W.L. Ng, M.A. Lourenco, R.M. Gwilliam, S. Ledain, G. Shao, K.P.
Homewood, Nature 410, 192 (2001).
(2) L. Pavesi, J. Phys.: Condens. Matter 15, R1169 (2003).
(3) G.Z. Pan, R.P. Ostroumov, Y.G. Lian, K.N. Tu, K.L. Wang, IEDM
Tech. Digest (2004) pp. 343-346.
(4) L. Dal Negro, J.H. Yi, M. Stolfi, J. Michel, J. LeBlanc, J. Haavisto,
L.C. Kimerling, IEDM Tech. Digest (2005) pp. 1019-1022.
(5) M.H. Liao, C.-Y. Yu, C.-F. Huang, C.-H. Lin, C.-J. Lee, M.-H. Yu,
S.T. Chang, C.-Y. Liang, C.-Y. Lee, T.-H. Guo, C.-C. Chang, C.W.
Liu, IEDM Tech. Digest (2005) pp. 1023-1026
(6) M. Kittler, M. Reiche, T. Arguirov, W. Seifert, X. Yu, IEDM Tech.
Digest (2005) pp. 1027-1030.
(7) F. Iacona, D. Pacifici, A. Irrera, M. Miritello, G. Franzo, F. Priolo,
D. Sanfilippo, G. Di Stefano, P.G. Fallica, Appl. Phys. Lett. 81, 3242
(2002)
(8) V. Kveder, M. Badylevich, E. Steinman, A. Izotov, M. Seibt, W.
Schröter, Appl. Phys. Lett. 84, 2106 (2004).
(9) G. Jia, M. Kittler, Z. Su. D. Yang, J. Sha, phys. stat. sol. (a) 203, R55
(2006).
(10) E.Ö. Sveinbjörnsson, S. Bengtsson, J. Weber, N. Keskitalo, ECS Proc.
Vol. 97-36 (1998) pp. 264-271.
(11) N.A. Drozdov, A.A. Patrin, V.D. Tkachev, JETP Lett. 23, 597 (1976).
(12) M. Reiche, K. Scheerschmidt, D. Conrad, R. Scholz, A. Plößl, U.
Gösele, K.N. Tu, Inst. Phys. Conf. Ser. 157, 447 (1997).
(13) B. Aspar, M. Bruel, Moriceau, C. Maleville, T. Poumerol, A.M.
Papon, A. Claverie et al., Microeletr. Eng. 36, 233 (1997).
(14) C.W. Liu, M.H. Lee, M.-J. Chen, I.C. Lin, C.-F. Lin, Appl. Phys. Lett.
76, 1516 (2000).
(15) M. Trupke, J. Zhao, J. Zhao, A. Wang, R. Corkish, M.A. Green, Appl.
Phys. Lett. 82, 2996 (2003).
(16) A. Broniatowski, Phys. Rev. B 36, 589 (1987).
(17) X. Yu, O.F. Vyvenko, M. Kittler, W. Seifert, T. Mchedlidze,
T. Arguirov, M. Reiche, “Combined CL/EBIC/DLTS Investigation of a
Regular Dislocation Network Formed by Silicon Wafer Direct
Bonding”, “Beam Injection Assessment of Microstructures in
Semiconductors - BIAMS 2006”, St. Petersburg, June 2006, BIAMS
Proceedings in press.
(18) M. Kittler, M. Reiche, W. Seifert, X. Yu, T. Arguirov, O.F. Vyvenko,
T. Mchedlidze, T. Wilhelm, "Regular Dislocation Networks in Silicon
as a Tool for Novel Device Application", "High Purity Silicon 9” ,
ECS Transactions - Cancun, Volume 3 (2006), in press.

Erschienene Publikationen
Published Papers
E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
(1) Determination of Low Concentrations of
N and C in CZ-Si by Precise FTiR
Spectroscopy
V.D. Akhmetov, H. Richter, n. Inoue
Materials Science and engineering B 134(2-3),
207 (2006)
Adding of relatively small amounts of n and C, on
the order of 1 × 10 14 cm -3 in the growing crystals of
Czochralski Si (CZ-Si) is considered now as a tool for
the control of the internal gettering processes based
on the precipitation of oxygen. the sensitivity of the
conventional procedure of measurements by Fourier
transform infrared (Ft-IR) spectroscopy measurements
is not sufficient to determine, in a reliable
manner, such concentrations of n and C. this report
contains results of the implementation of the modified
method of Ft-IR measurements, which allows
one to improve the sensitivity for more than one order
of magnitude. the new method is based mainly
on (1) the modified Ft-IR system with enhanced photometric
accuracy achieved by a suppression of the
influence of the instabilities, and (2) using Brewster
geometry to suppress the interference effects. the
method contains built-in checking of the achieved
accuracy of the recorded spectrum. the examples of
the determination of [n] and [C] on the 10 14 cm -3 -level
in 2 mm thick samples as well as in industrial wafers
are presented.
(2) FTiR Spectroscopic System with improved
Sensitivity
V.D. Akhmetov, H. Richter
Materials Science in Semiconductor
processing 9(1-3), 92 (2006)
the problem of the determination of the intensity of
weak infrared (IR) absorption bands by differential
IR spectroscopy is considered for the case of a noise-limited
sensitivity. A spectroscopic system based
on a Fourier transform IR (FtIR) spectrometer which
improves the sensitivity of the IR method by at least
30 times, is described. In the conventional differen-
tial FtIR measurements, only a single pair of spectra
(from the analyzed sample and from the reference) is
taken during the whole acquisition time. In contrast,
in our system, we take the data interchangeably from
the analyzed pair of sample and reference during the
same acquisition time. this “modulation” of samples
suppresses the contribution of the low-frequency
noise as well as long-term instabilities in the differential
spectrum. the described system consists of an
FtIR spectrometer, a computer-controlled optimized
sample changer, and software for fully automated
multiple measurements. the main steps of data processing
as well as an example of application of multiple
measurements for a diagnostics of thin wafers
are presented.
(3) Pressure-induced Transformations of
Nitrogen implanted into Silicon
V.D. Akhmetov, A. Misiuk, A. Barcz, H. Richter
physica Status Solidi A 203(4), 781 (2006)
Czochralski (CZ) Si samples implanted with nitrogen,
with doses 10 17 ion / cm 2 and 10 18 ion / cm 2 , at 140
keV, were studied by means of Fourier transform infrared
spectroscopy after annealing at 1130 °C / 5 h
under different hydrostatic pressures, from 1 bar
to 10.7 kbar. It has been found for each pressure
applied, that the increased nitrogen dose leads to
transformation of the broadband spectra to the fine
structure ones, corresponding to crystalline silicon
nitride. the spectral position of observed sharp peaks
in the investigated pressure region is red shifted in
comparison to that for the peaks of crystalline silicon
oxynitride found recently by other investigators
in nitrogen-containing poly-Si as well as in a residual
melt of nitrogen-doped CZ-Si. the application of the
pressure during annealing results in further red shift
of the nitrogen-related bands. the observed decrease
of frequency of vibrational bands is explained in
terms of the pressure induced lowered incorporation
of oxygen into growing oxynitride phase. Secondary
ion mass spectrometry data reveal the decrease of
oxygen content in implanted layer with increasing
pressure during annealing.
A n n u A l R e p o R t 2 0 0 6
131

132 A n n u A l R e p o R t 2 0 0 6
E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
(4) Pressure-assisted Lateral Nanostructuring
of the Epitaxial Silicon Layers with SiGe
Quantum Wells
I.V. Antonova, M.B. Gulyaev, V.A. Skuratov,
R.A. Soots, V.I. obodnikov, A. Misiuk,
p. Zaumseil
Solid State phenomena 114, 291 (2006)
transformations of the SiGe / Si superlattice structures,
either annealed at high pressure, or irradiated
by high energy ions and subjected to post-implantation
annealing, were studied and compared. Both
types of treatments were found to lead to the formation
of recharged defects clusters, resulting in the
appearance of peaks on C-V characteristics, shrinkage
of Ge profiles registered by SIMS technique after annealing,
and disappearance of peaks in the free carrier
profiles. the effects were more pronounced in the
case of high energy ion implantation. the results are
explained by the vacancy-assisted precipitation of Ge
in SiGe layers.
(5) Residual Stress in Si Nanocrystals
Embedded in a Sio 2 Matrix
t. Arguirov, t. Mchedlidze, M. Kittler, R. Rölver,
B. Berghoff, M. Först, B. Spangenberg
Applied physics letters 89, 053111 (2006)
Multiple quantum wells consisting of alternating
Si and Sio 2 layers were studied by means of Raman
scattering. the structures were fabricated by the remote
plasma enhanced chemical vapor deposition of
amorphous Si and Sio 2 layers on quartz substrate. the
structures were subjected to a rapid thermal annealing
procedure for Si crystallization. the obtained
results suggest that the Si layers consist of nanocrystals
embedded in an amorphous Si phase. It was
found that the silicon nanocrystals inside 2 nm thin
layers are under high residual compressive stress. Moreover,
the metastable Si III phase was detected in
these samples supporting the presence of large compressive
stresses in the structures. the compressive
stress could be relaxed upon local laser annealing.
(6) Towards Silicon based Light Emitters
Utilising the Radiation from Dislocation
Networks
t. Arguirov, M. Kittler, W. Seifert, X. Yu
Materials Science and engineering B 134,
109 (2006)
on-chip optical interconnects require a CMoS-compatible
electrically pumped Si-based light emitter
at about 1.5 µm. Dislocations in silicon offer a recombination
centre for light emission at the desired
energy. Here we report on the radiative properties of
dislocation networks, created in a well controllable
manner at a certain depth of silicon wafers. Dislocation
networks, created by ion implantation and annealing,
misfit dislocation in SiGe buffers and a novel
concept of dislocations created by misoriented direct
bonded Si wafers are discussed. We demonstrate that
under a specific misorientation a dislocation network
with efficient room temperature D1 (1.55 µm) emission
might be generated.
(7) Structure of biomembrane-on-Silicon
Hybrids Derived from X-Ray Reflectometry
M. Birkholz, p. Zaumseil, M. Kittler, I. Wallat,
M. Heyn
Materials Science and engineering B 134,
125 (2006)
the organic–inorganic interface and its proper structural
adjustment are of central importance for the
fabrication of hybrid material systems from biomolecules
and semiconductors. Such material hybrids are
currently under development for several advanced
applications, in particular for biomolecular sensing.
An investigation of biomolecular immobilization on
semiconductor surfaces by X-ray reflectometry (XRR)
will be presented. Complete biomembrane patches
of purple membrane (pM) from Halobacterium salinarum
were immobilized on oxidized and nitrided
silicon wafers. A covalent immobilization protocol
based on 3-aminopropyltriethoxysilane (AptS) and
glutaric dialdehyde (GD) was applied for cross-linking
the biomolecules to the semiconductor surface. XRR
could be shown to yield the relevant morphological
parameters of biomolecular monolayers such as layer

E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
thickness, interface roughness and coverage. Synchrotron
radiation was not required, but a laboratory
rotating anode set-up was sufficient to study the prepared
stacking of organic monolayers. According to
the measurement and analysis of XRR patterns both
cross-linking layers AptS and GD are required for bonding
purple membrane patches to Sio 2 / Si, whereas
GD alone suffices for cross-linking to Si 3 n 4 / Si. this
distinct behavior offers a pathway for nanopatterning
of biomolecules on Si surfaces by selective passivation.
(8) A 20 GSample/s, 40 mW SiGe HbT
Comparator for Ultra-High-Speed ADC
Y. Borokhovych, H. Gustat
eCS transactions 3(7), 937 (2006)
this paper presents a high-speed master-slave comparator
in an eCl configuration. Implemented in 190 GHz
SiGe HBt technology, the comparator occupies
0.7 x 0.7 mm 2 , including bondpads. the comparator
can operate at a speed up to 20 GSample / s with a resolution
of 7.2 bits per 1.2 Vp-p input. the low power
consumption of the comparator itself (40 mW) and
its small corearea of 190 x 35 µm 2 make it suitable
for mediumresolution full-flash A / D converters and
other low-power comparator applications.
(9) Ab initio Study of Point Defects in
Dielectrics based on Pr oxides
J. Dabrowski, A. Fleszar, G. lupina, Ch. Wenger
Materials Science in Semiconductor
processing 9, 897 (2006)
We discuss the influence of band structures and point
defects (oxygen vacancies and interstitials, and praseodymium
vacancies) in pr 2 o 3 , pro 2 , and prSio 3.5 on
the electrical properties of high-K gate dielectrics for
the application in CMoS technology. In particular,
we consider the origin of fixed charges and leakage
currents. We address these issues mostly from the
perspective of ab initio calculations for formation
energies, electronic structures, and band alignment
between the film and the silicon substrate.
(10) High Spatial Resolution Mapping of
Partially Strain-Compensated SiGe:C Films
in the Presence of Postannealed Defects
A.V. Darahanau, A. Benci, A.Y nikulin,
J. etheridge, J. Hester, p. Zaumseil
Journal of Applied physics 99, 113531 (2006)
An experimental-analytical technique for the model-independent
nondestructive characterization of singlecrystal
alloys is applied to partially strain-compensated
SiGe:C / Si single layer structures with high concentrations
of Ge. the studies were performed on pre- and postannealed
SiGe:C / Si samples. X-ray Bragg diffraction
profiles were collected at a synchrotron radiation source
near the absorption edge of Ge. the studies have allowed
the reconstruction of the complex crystal structure
factor as a function of crystal depth, permitting direct
observation of the effect of the thermal annealing on
lattice strain and structural composition in the SiGe:C
layer. the technique was shown to be applicable to the
analysis of both perfect crystals and crystal structures
containing a low defect concentration.
(11) An integrated 3.1-5.1 GHz Pulse Generator
for Ultra-Wideband Wireless Localization
Systems
X. Fan, G. Fischer, B. Dietrich
Advances in Radio Science 4, 247 (2006)
this paper presents an implementation of an integrated
ultra-wideband (uWB), Binary-phase Shift
Keying (BpSK) Gaussian modulated pulse generator.
VCo, multiplier and passive Gaussian filter are the key
components. the VCo provides the carrier frequency
of 4.1 GHz, the lC Gaussian filter is responsible for the
pulse shaping in the baseband. Multiplying the baseband
pulse and the VCo frequency shifts the pulse to
the desired center frequency. the generated Gaussian
pulse ocuppies the frequency range from 3.1 to 5.1 GHz
with the center frequency at 4.1 GHz. Simulations
and measured results show that this spectrum fulfills
the mask for indoor communication systems given by
the FCC (Federal Communications Commission, 2002).
the total power consumption is 55 mW using a supply
voltage of 2.5 V. Circuits are realized using the IHp
0.25 µm SiGe:C BiCMoS technology.
A n n u A l R e p o R t 2 0 0 6
133

134 A n n u A l R e p o R t 2 0 0 6
E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
(12) Cost-Effective integration of an FNprogrammed
Embedded Flash Memory into
a 0.25 µm SiGe:C RF-biCMoS Technology
A. Fox, K.e. ehwald, p. Schley, R. Barth,
S. Marschmeyer, C. Wolf, V.e. Stikanov,
A. Gromovyy and A. Hudyryev
Microelectronics Journal 37(11), 1194 (2006)
this paper presents a process technology for costeffective
integration of low-power flash memories
into a 0.25 µm, high performance SiGe:C RF-BiCMoS
process. only four additional lithographic steps are
used on top of the baseline BiCMoS process, leading
to in total 23 mask levels for the BiCMoS / embedded
flash process. uniform-channel Fowler-nordheim programmable
and erasable stacked-gate cells, suitable
for medium density (Mbit) memories, are demonstrated.
peripheral high-voltage transistors, with >10 V
breakdown voltage, are integrated without additional
mask steps on top of the flash cell integration. the
flash memory integration is modular and has negligible
impact on the original CMoS and HBt device
parameters.
(13) infrared Absorption Measurement of
Carbon Concentration in Silicon Crystals
n. Inoue, M. nakatsu, V. Akhmetov
eCS transactions 2(2), 461 (2006)
Sensitivity and accuracy of carbon concentration
measurement by infrared (IR) absorption spectroscopy
are improved. We cut unnecessary high energy
light input by a low pass filter. Measurement condition
of sample and reference is kept as equal as possible
by using the sample changer and measure them
alternately for many times. It is possible to improve
the accuracy by keeping the temperature of sample
and reference as close as possible. In the analytical
procedure, we use a reduced phonon spectrum fitting
instead of straight baseline. Standard carbon spectrum
fitting to a small carbon peak make it possible
to determine the carbon concentration accurately. As
a result, we can measure differential carbon concentration
down to about 1x10 14 atoms / cm 3 .
(14) 1.5 µm Luminescence of Silicon Nanowires
Fabricated by Thermal Evaporation of Sio
G. Jia, M. Kittler, Z. Su, D. Yang, and J. Sha
physica Status Solidi A 203, R55 (2006).
Silicon nanowires (nWs) fabricated by thermal evaporation
of Sio were studied by cathodoluminescence.
A band around 1550 nm (0.8 eV) was observed. It
appears above 225 K and its intensity increases with
increasing temperature. the broad band consists of
the defect-related D1 and D2 lines and is supposed to
be formed by extended defects within the nWs that
are decorated with oxygen. Moreover, luminescence
bands are found that are related to Si oxide and / or
the interface between Si and Si oxide. In addition, the
Si band-to-band line and the G center are observed.
(15) A Contribution to oxide Precipitate
Nucleation in Nitrogen Doped Silicon
G. Kissinger, u. lambert, M. Weber,
F. Bittersberger, t. Müller, H. Richter,
W. von Ammon
physica Status Solidi A 203(4), 677 (2006)
Based on Fourier transform infrared (FtIR) spectroscopy
and bulk micro-defect investigations, in relation
to earlier results of other groups, we suggest
the following model for oxide precipitate nucleation
in n-doped silicon. Around 600 °C a nucleation maximum
exists where oxide precipitates are formed via
oxygen attachment to both noo and nno complexes.
these complexes are formed by the reaction of nn
with interstitial oxygen. Vacancy supersaturation enhances
this type of precipitate nucleation. A second
nucleation maximum exists around 900 °C. this is
assumed to be due to a vacancy assisted oxynitride
Sio x n y based nucleation process. the higher density
of the oxynitride phase compared to silicon oxide and
a higher residual vacancy concentration would explain
the observed shift of the maximum nucleation
rate to higher temperatures around 900 °C.

E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
(16) Analytical Modeling of the interaction of
Vacancies and oxygen for oxide Precipitation
in RTA Treated Silicon Wafers
G. Kissinger, J. Dabrowski, A. Sattler,
C. Seuring, t. Müller, H. Richter, W. von Ammon
eCS transactions 2(2), 247 (2006)
We have investigated the impact of RtA induced vacancy
supersaturation on oxide precipitation based
on as much as possible experimental and theoretical
values. oxygen precipitation after RtA processing was
found to be controlled by the initial concentration of
interstitial oxygen in a sixth power dependency and
frozen vacancies just in a cubic dependency. the formation
of tensile strained nVo 2 clusters seems to be
the favored process for coherent nucleation of oxide
precipitates. the reduction of interstitial oxygen
can be accurately modeled for the temperature range
from 1150 °C to 1250 °C using Ham‘s theory for
precipitate growth and an empirical relation based
on nucleation of oxide precipitates by agglomeration
of Vo 2 complexes. During RtA treatments at temperatures
greater than or equal to 1300 °C vacancies seem
to be consumed by other processes. Below RtA temperatures
of 1150 °C, oxide precipitation is dominated
by shrunken as-grown precipitate nuclei because
as-grown nuclei can be dissolved only at RtA temperatures
greater than or equal to 1150 °C.
(17) Combination of optical Measurement and
Precipitation Theory to overcome the
obstacles of Detection Limits
G. Kissinger, t. Müller, A. Sattler, W. Häckl,
p. Krottenthaler, t. Grabolla, H. Richter,
W. von Ammon
Materials Science in Semiconductor
processing 9, 236 (2006)
Ham‘s theory was applied in order to become independent
of detection limits for oxide precipitates and
to quantify the phenomenon of oxygen loss to invisible
BMDs during thermal treatments. the density
of detectable bulk micro-defects (BMDs) depends on
the size distribution of grown-in nuclei and the ramp
rate, temperature, and duration of the thermal treatment
applied. there is no correlation to the invisible
BMDs. During conventional annealing, the density of
the invisible BMDs decreases exponentially with increasing
radius of precipitates at a nearly constant
loss of interstitial oxygen. only if the calculated radius
exceeds 70 nm, a 100 % loss of interstitial oxygen
to BMDs detectable by scanning infrared microscopy
(SIRM) seems to be possible. After RtA processing at
1230 °C, a period of 1 h at 1000 °C would be necessary
for the growing oxide precipitates to reach a saturated
density detectable by SIRM, but there remains a
very high density of invisible BMDs consuming interstitial
oxygen. In n-doped silicon, the vast majority
of BMDs is detectable by SIRM, cleave and etch, and
infrared light scattering tomography after thermal
processing.
(18) oxide Precipitation via Coherent
“Seed”-oxide Phases
G. Kissinger, J. Dabrowski
eCS transactions 3(4), 97 (2006)
until now, oxide precipitation is treated in theoretical
models as homogeneous nucleation of incoherent
Sio x precipitates. In reality, this type of nucleation is
very seldom because it is hindered by a high energy
barrier which results from the incoherent interface.
the key role of Vo 2 complexes for nucleation of oxide
precipitates was already demonstrated on a broad experimental
basis. Ab initio calculations have shown
that the agglomeration of Vo 2 is energetically favorable.
In this contribution, the bulk modulus and molecular
volume of nVo 2 clusters, so-called seed-Sio 2 ,
are determined and an analytical nucleation model is
developed. In a second step, a more advanced model
was developed which is based on a mono-layered agglomeration
of Vo 2 complexes on 100 planes, so called
seed-Sio and the heterogeneous nucleation of amorphous
Sio 2 (a-Sio 2 ) at these plates. From energetic
reasons, the advanced model is regarded as the most
plausible nucleation path.
A n n u A l R e p o R t 2 0 0 6
135

136 A n n u A l R e p o R t 2 0 0 6
E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
(19) Regular Dislocation Networks in Silicon
as a Tool for Novel Device Application
M. Kittler, M. Reiche, W. Seifert, X. Yu,
t. Arguirov, o.F. Vyvenko, t. Mchedlidze,
t. Wilhelm
eCS transactions 3(4), 429 (2006)
the paper deals with possibilities of utilizing dislocation
structures as active components of devices. the
suggested means for controlled formation of dislocations
is direct wafer bonding, giving rise to well defined
dislocation networks with adjustable properties.
It is shown that the networks allow building light
emitting diodes based on the D line luminescence
of the dislocations. A light emitter at about 1.5 µm
wavelength is demonstrated, with an efficiency potential
estimated at 1 %. Immobilization of biomolecules
on Si surfaces by Coulomb interaction with the
dislocations in the network is another application
discussed. Finally, the potential use of dislocation
networks as insulating layers permeable to impurities
to be gettered and as three-dimensional buried conductive
channels in the Si wafer is addressed.
(20) Self-organized Pattern Formation of
biomolecules at Si Surfaces: intended
Application of a Dislocation Network
M. Kittler, X. Yu, o.F. Vyvenko, M. Birkholz,
W. Seifert, M. Reiche, t. Wilhelm, t. Arguirov,
A. Wolff, W. Fritzsche, M. Seibt
Materials Science and engineering C 26,
902 (2006)
Defined placement of biomolecules at Si surfaces is a
precondition for a successful combination of Si electronics
with biological applications. We aim to realize
this by Coulomb interaction of biomolecules with dislocations
in Si. the dislocations form charged lines
and they will be surrounded with a space charge region
being connected with an electric field. the electric
stray field in a solution of biomolecules, caused
by dislocations located close to the Si surface, was
estimated to yield values up to few kVcm -1 . A regular
dislocation network can be formed by wafer direct
bonding at the interface between the bonded wafers
in case of misorientation. the adjustment of misori-
entation allows the variation of the distance between
dislocations in a range from 10 nm to a few µm. this is
appropriate for nanobiotechnology dealing with protein
or DnA molecules with sizes in the nm and lower
µm range. Actually, we achieved a distance between
the dislocations of 10–20 nm. Also the existence of a
distinct electric field formed by the dislocation network
was demonstrated by the technique of the electron-beam-induced
current (eBIC). Because of the
relatively short range of the field, the dislocations
have to be placed close to the surface. We positioned
the dislocation network in an interface being 200 nm
parallel to the Si surface by layer transfer techniques
using hydrogen implantation and bonding. Based on
eBIC and luminescence data we postulate a barrier of
the dislocations at the as bonded interface < 100 meV.
We plan to dope the dislocations with metal atoms
to increase the electric field. We demonstrated that
regular periodic dislocation networks close to the Si
surface formed by bonding are realistic candidates for
self-organized placing of biomolecules. experiments
are underway to test whether biomolecules decorate
the pattern of the dislocation lines.
(21) Silicon-based Light Emitters
M. Kittler, M. Reiche, t. Arguirov,
W. Seifert, X. Yu
physica Status Solidi A 203(4), 802 (2006)
A new concept for a Si light emitting diode (leD) capable
of emitting efficiently at 1.55 µm or at 1.3 µm,
respectively, is proposed. It utilizes radiation from a
well-defined dislocation network created in a reproducible
manner by direct Si wafer bonding. the wavelength
of the light emitted from the network can be
tailored by adjusting the misorientation between the
Si wafers. that way dominance of radiation at 1.55 µm
(D1 line) or at 1.3 µm (D3 line) was achieved. there
are hints that decoration of the dislocations by
oxygen enhances the intensity of the D1 radiation.
A critical analysis of the light emitter proposed by W.
l. ng et al. [nature 410, 192 (2001)] using band-toband
emission is given. Its application at the above
wavelengths would require a few microns thick SiGe
layer on top of the Si substrate.

E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
(22) System integration by Request-driven
GALS Design
M. Krstic, e. Grass, C. Stahl, M. piz
Iee proceedings - Computers and Digital
techniques 153(5), 362 (2006)
A novel request-driven globally asynchronous locally
synchronous (GAlS) technique for the system integration
of complex digital blocks is proposed. For this new
GAlS technique, an asynchronous wrapper compliant
is developed and evaluated. this proposed GAlS technique
is applied to a baseband processor compatible
with the wireless lAn standard Ieee 802.11a. the developed
GAlS baseband processor chip is fabricated
and measured. Besides improvements of the system
integration process, a 5 dB reduction in electromagnetic
interference, 30 % reduction in instantaneous
supply current variation, and similar dynamic power
consumption as in the synchronous baseband processor
is achieved.
(23) A Low-Power, X-band SiGe HbT Low-Noise
Amplifier for Near-Space Radar Applications
W.-M. l. Kuo, R. Krithivasan, X. li, Y. lu,
J. D. Cressler, H. Gustat, B. Heinemann
Ieee Microwave and Wireless Components
letters 16(9), 520 (2006)
A low-power, X-band low-noise amplifier (lnA) is presented.
Implemented with 180 GHz silicon-germanium
(SiGe) heterojunction bipolar transistors (HBts),
the circuit occupies 780 x 660 µm 2 . the lnA exhibits
a gain of 11.0 dB at 9.5 GHz, a mean noise figure of
2.78 dB across X-band, and an input third-order intercept
point of -9.1 dBm near 9.5 GHz, while dissipating
only 2.5 mW. the low-power performance of this lnA,
together with its natural total-dose radiation immunity,
demonstrates the potential of SiGe HBt technology
for near-space radar applications.
(24) A Distributed Privacy Enforcement
Architecture based on Kerberos
p. langendörfer, K. piotrowski, M. Maaser
WSeAS transactions on Communications 5,
2 (2006)
In this paper we propose a distributed privacy enforcement
architecture. each mobile client runs its own
privacy negotiation unit as well as its own Kerberos
ticket granting server. the privacy negotiation units
are compatible with the p3p standard, but allow mutual
exchange of privacy policies and enforce that these
are digitally signed in case of an agreement. each of
the individual tGS may provide tickets only for data
that is owned by the mobile (user) on behalf of which
it is executed. In addition the initial authentication
phase can be done by the standard Kerberos approach
as well as based on pKI using certificate chains. So
our architecture gives the user back control over her
personal data and it provides better scalability to the
context aware platform. It also opens up the Kerberos
approach for environments in which the mobile client
discovers new services, which are not registered at its
platform, i.e., at the Kerberos server. our measurements
indicate that running our privacy enforcement
architecture on the mobile device does not inhibit a
real burden. Successful negotiations are completed
within 2 seconds including message exchange and
compiling a ticket is done in about 100 ms at 238 MHz
and the client application size of our Java tGS implementation
is less than 50 kByte.
(25) Praseodymium Silicate Films on Si(100)
for Gate Dielectric Applications: Physical
and Electric Characterization
G. lupina, t. Schroeder, J. Dabrowski,
Ch. Wenger, A.u. Mane, H.-J. Müssig,
p. Hoffmann, D. Schmeißer
Journal of Applied physics 99, 114109 (2006)
praseodymium (pr) silicate dielectric layers were
prepared by oxidation and subsequent n 2 annealing
of thin pr metal layers on Sio 2 / Si(100) substrates.
transmission electron microscopy studies reveal
that the resulting dielectric has a bilayer structure.
nondestructive depth profiling by using synchrotron
radiation x-ray photoelectron spectroscopy shows
that, starting from the substrate, the dielectric stack
is composed of a Sio 2 -rich and a Sio 2 -poor pr silicate
phase. Valence and conduction band offsets of about
2.9 and 1.6 eV, respectively, between the dielectric
and the Si(100) substrate bands were deduced. pr
A n n u A l R e p o R t 2 0 0 6
137

138 A n n u A l R e p o R t 2 0 0 6
E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
silicate films with an equivalent oxide thickness of
1.8 nm show approximately three orders of magnitude
lower leakage currents than silicon oxynitride references.
Capacitance versus voltage measurements
of the pr silicate / Si(100) system report a flat band
voltage shift of 0.22 V, an effective dielectric constant
of about 11 and a reasonably good interface
quality with an interface state density on the order of
10 11 cm –2 . experimental results are supplemented by
ab initio considerations which review the most probable
mechanisms of fixed charge formation in the pr
silicate layers.
(26) Thermal Stability of Pr Silicate High-k-
Layers on Si(100)
G. lupina, t. Schroeder, Ch. Wenger,
J. Dabrowski, H.-J. Müssig
Applied physics letters 89, 222909 (2006)
thermal stability of amorphous pr silicate high-k
layers on Si(001) was evaluated in view of complementary
metal-oxide-semiconductor transistor processing
requirements. Materials science techniques
prove that no crystallization, no phase separation
into Sio 2 and pr 2 o 3 , and no pr silicide formation at the
interface occur after 1 min rapid thermal annealing
treatment in n 2 over the temperature range from 600
to 900 °C. electrical measurements confirm within
this thermal budget well-behaved characteristics
with k values between 11 and 13 and leakage currents
about three orders of magnitude lower than in case of
Sion reference layers.
(27) involvement of iron-Phosphorus
Complexes in iron Gettering for N-Type
Silicon
t. Mchedlidze, M. Kittler
physica Status Solidi A 203(4), 786 (2006)
Mechanisms for phosphorus (p) diffusion gettering
(pDG) for iron are supplemented by possible formation
of iron-phosphorus complexes in heavy p-doped
region. existence of such complexes was recently
reported based on the results of electron-spin resonance
investigations. DltS measurements suggest a
high probability for the formation of iron-phosphorus
complexes in n-type silicon in the presence of vacancies
and / or vacancy-phosphorus pairs. on the other
hand, recent theoretical calculations predict formation
of negatively charged vacancy-phosphorus pairs
in the heavily p-doped region of silicon during pDG.
these facts indicate on possibility to explain the high
efficiency of the pDG process for iron by assuming
formation of iron-phosphorus complexes in the heavy
p-doped region of silicon. possible advantages of
application of hydrogen or nitrogen assisted pDG are
considered.
(28) Structural and optical Properties of
Si / Sio 2 Multi-Quantum Wells
t. Mchedlidze, t. Arguirov, M. Kittler,
R. Roelver, B. Berghoff, M. Foerst and
B. Spangenberg
physica e available online (2006)
Structural and optical properties of Si / Sio 2 multiquantum
wells (MQW) were investigated by means
of Raman scattering and photoluminescence (pl)
spectroscopy. the MQW structures were fabricated
on a quartz substrate by remote plasma enhanced
chemical vapour deposition (RpeCVD) of alternating
amorphous Si and Sio 2 layers. After layer deposition
the samples were subjected to heat treatments, i.e.
rapid thermal annealing (RtA) and furnace annealing.
Distinct pl signatures of confined carriers evidenced
formation of Si-nanocrystals (nc-Si) in annealed samples.
Analyses of Raman spectra also show presence
of nc-Si phase along with amorphous-Si (a-Si) phase
in the samples. the strong influence of the annealing
parameters on the formation of nc-Si phase suggests
broad possibilities in engineering MQW with various
optical properties. Interestingly, conversion of the
a-Si phase to the nc-Si phase saturates after certain
time of furnace annealing. on the other hand, thinner
Si layers showed a disproportionately lower crystalline
volume fraction. From the obtained results we could
assume that an interface strain prevents full crystallization
of the Si layers and that the strain is larger for
thinner Si layers. the anomalous dependence of nc-
Si Raman scattering peak position on deposited layer
thickness observed in our experiments also supports
the above assumption.

E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
(29) Atomically Controlled Processing for
Group iV Semiconductors by Chemical
Vapor Deposition
J. Murota, M. Sakuraba, B. tillack
Japanese Journal of Applied physics pt. 1
45(9a), 6767 (2006)
one of the main requirements for Si-based ultrasmall
devices is atomic-order control of process technology.
Here we show the concept of atomically controlled
processing for group IV semiconductors based on
atomic-order surface reaction control. By ultraclean
low-pressure chemical vapor deposition using SiH 4
and GeH 4 gases, high-quality low-temperature epitaxial
growth of Si, Ge, and Si 1-x Ge x with atomically flat
surfaces and interfaces on Si(100) is achieved, and
atomic-order surface reaction processes on group
IV semiconductor surface are formulated based on
a langmuir-type surface adsorption and reaction
scheme. In in-situ doped Si 1-x Ge x epitaxial growth
on the (100) surface in a SiH 4 –GeH 4 –dopant (pH 3 , or
B 2 H 6 or SiH 3 CH 3 )–H 2 gas mixture, the deposition rate,
the Ge fraction and the dopant concentration are
explained quantitatively assuming that the reactant
gas adsorption / reaction depends on the surface site
material and that the dopant incorporation in the
grown film is determined by Henry‘s law. Self-limiting
formation of 1–3 atomic layers of group IV or related
atoms in the thermal adsorption and reaction of
hydride gases on Si(100) and Ge(100) is generalized
based on the langmuir-type model. Si or SiGe epitaxial
growth over n, p or B layer already-formed on
Si(100) or SiGe(100) surface is achieved. Furthermore,
the capability of atomically controlled processing
for advanced devices is demonstrated. these results
open the way to atomically controlled technology for
ultralarge-scale integrations.
(30) Effect of Fluorine on the Activation and
Diffusion behaviour of boron implanted
Preamorphized Silicon
S. paul, W. lerch, B. Colombeau, n.e.B Covern,
F. Christiano, S. Bonelli, D. Bolze
Journal of Vacuum Science and technology B
24(1), 437 (2006)
In this study we investigated the effect of position
and dose of a separate fluorine coimplant on the
activation and diffusion behavior of germanium
preamorphized boron implants. Germanium preamorphized
silicon was implanted with boron, and fluorine
was subsequently implanted with different energies
and doses to place it either at the projected range
of the boron implant, or between the boron profile
and the amorphous-crystalline interface, or at this
interface. the wafers were spike annealed at temperatures
ranging from 950 to 1050 °C. In terms of
sheet resistance it was found that the superposition
of B and F profiles leads to decreased activation compared
to the wafers without any F implant. Increased
boron activation is seen for all the other cases with
the biggest effects for the highest fluorine dose. the
positioning of F either between the boron projected
range and the end of range (eoR) or at the eoR leads
to more box-shaped boron profiles with shallower
junction depth than the reference wafer.
(31) Protecting Privacy in E-Cash Schemes by
Securing Hidden identity Approaches
against Stochastic Attacks
K. piotrowski, p. langendörfer, o. Maye,
Z. Dyka
Internet Research emerald 16(2), 159 (2006)
to enhance security and privacy of e-cash systems
that apply revocable anonymity by presenting a statistical
attack that reveals the hidden ID and suitable
protection means against this kind of attack.
(32) Quantum Theory for ac-Admittance
p.n. Racec, u. Wulf
Materials Science and engineering C 26,
876-880 (2006)
Starting from a mean field calculation for the static
capacitance of a MIS-nanostructure with a near back
gate [p.n. Racec, e.R. Racec and u. Wulf, phys. Rev. B
65, 193314, (2002)] we develop an approach to determine
its ac-admittance. Mainly because of the interaction
with the near back gate the inversion electron
layer which forms in the considered MIS-nanostructure
assumes on open character which is taken into
A n n u A l R e p o R t 2 0 0 6
139

140 A n n u A l R e p o R t 2 0 0 6
E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
account in the landauer–Büttiker formalism. For the
Coulomb interaction the Hartree approximation is
applied. In quantitative agreement with experiments
a characteristic step in the static C–V trace results
when the inversion layer is populated from the back
gate. We found that this characteristic step is dominated
by a particular resonance which we call intermediate
resonance. Consistent with our static calculations
we determine the density–density correlation
function in the random phase approximation to find
the ac-admittance. As an example we demonstrate
that the lifetime of the static resonance induces a
characteristic turnover frequency for the ac-admittance.
An equivalent small-signal circuit is proposed
and the dependence of its elements (capacitance and
resistance) on the working point for low and high frequencies
are presented.
(33) Small-Signal Circuit Elements of MiS-Type
Nanostructures
p.n. Racec, u. Wulf
Solid State phenomena 121-123, 549 (2006)
Starting from a mean field calculation for the static
capacitance of a MIS-nanostructure with a near
back gate [p.n. Racec, e.R. Racec and u. Wulf, phys.
Rev. B 65, 193314, (2002)] we develop an approach
to determine the equivalent small-signal circuit. the
analyzed system has an open character, taken into account
in the landauer-Büttiker formalism. the Coulomb
interaction is treated in Hartree approximation.
Consistent with our static calculation we determine
the charge-charge correlation function in the random
phase approximation to find the ac-admittances.
the small-signal circuit consists of a voltage-dependent
capacitance and a resistance in series. Beyond
a characteristic frequency V c they become frequency
dependent. the characteristic frequency is given by
the life time of specific resonance which develops in
the system.
(34) Dislocation-induced Light Emission
M. Reiche, M. Kittler, t. Wilhelm, t. Arguirov,
W. Seifert, X. Yu, t. Mchedlidze
eCS transactions 3(7), 311 (2006)
Hydrophobic wafer bonding causes the formation of
dislocation networks in the bonded interface. the
structure of the dislocation network depends on
the misorientation between both wafers during the
bonding. the characterization of the dislocation networks
proved that the luminescence depends only on
the structure of the dislocation network. Different
degrees of misorientation cause that different lines
in the pl- and Cl-spectra appear. this makes it possible
to construct monochromatic light sources.
(35) Dopant Diffusion in SiGe:C Alloys
H. Rücker, B. Heinemann, R. Kurps, Y. Yamamoto
eCS transactions 3(7), 1069 (2006)
In this paper, we discuss the impact of germanium
and carbon on the diffusion of common dopants in
Si-based alloys. We review results of various diffusion
experiments and discuss the basic physical mechanisms
of the observed changes of diffusion coefficients
as a function of alloy composition. Results of
boron and phosphorus marker layer diffusion experiments
are presented for binary Si 1-x Ge x and Si 1-y C y and
ternary Si 1-x-y Ge x C y alloys.
(36) on the Epitaxy of Twin-Free Cubic (111)
Praseodymium Sesquioxide Films on Si (111)
t. Schroeder, p. Zaumseil, G. Weidner,
Ch. Wenger, J. Dabrowski, H.-J. Müssig,
p. Storck
Journal of Applied physics 99, 014101 (2006)
twin-free epitaxial cubic (111) praseodymium sesquioxide
films were prepared on Si(111) by hexagonalto-cubic
phase transition. Synchrotron radiation
grazing incidence x-ray diffraction and transmission
electron microscopy were applied to characterize the
phase transition and the film structure. As-deposited
films grow single crystalline in the (0001)-oriented
hexagonal high-temperature phase of praseodymium
sesquioxide. In situ x-ray diffraction studies deduce
an activation energy of 2.2 eV for the hexagonal-to-cubic
phase transition. transmission electron
microscopy shows that the phase transition is accompanied
by an interface reaction at the oxide / Si(111)
boundary. the resulting cubic (111) low-temperature

E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
praseodymium sesquioxide film is single crystalline
and exclusively shows B-type stacking. the 180° rotation
of the cubic oxide lattice with respect to the
Si substrate results from a stacking fault at the substrate
/ oxide boundary.
(37) Standardization of Test Methods of bulk
Microdefects and Denuded Zone in
Annealed CZ Si
R. takada, n. Inoue , K. Moriya, K. Kashima,
K. nakashima, M. Kato, S. Kitagawa, t. ono,
H. uzushido, n. nango and V. Akhmetov
eCS transactions 2(2), 471 (2006)
the requirement to standardize measurement methods
for BMD (Bulk Micro Defect) density and DZ
(Denuded Zone) CZ silicon has lead to the establishment
of a SeMI standard for annealed CZ silicon wafers.
therefore, it was decided that we should aim at
standardizing the preferential-etching and 90 degrees
laser-scattering tomography techniques as a
collaborative work between JeItA (Japan electronics
and Information technology Industries Association)
and JSpS (Japan Society of promotion of Science)
145 th Committee. In this work, we carried out a set
of round robin tests and examined whether we could
jointly standardize both the preferential-etching and
the 90 degrees laser-scattering methods. this resulted
in a standardized measurement protocol for BMD
density and DZ width, which has become known as the
JeItA standard eM 3508 [1].
(38) Atomic Layer Processing for Doping of SiGe
B. tillack, Y. Yamamoto, D. Bolze,
B. Heinemann, H. Rücker, D. Knoll, J. Murota,
W. Mehr
thin Solid Films 508(1-2), 279 (2006)
Atomic layer processing has been demonstrated for
doping of SiGe during Reduced pressure Chemical Vapour
Deposition (RpCVD) in a commercial single wafer
reactor. Atomic level control of dose and location has
been obtained for B doping using B 2 H 6 and for p doping
using pH 3 . the main idea of atomic layer processing
is the separation of adsorption of the reactant
gases from the deposition process. By this way, self-
limitation has been shown for p doping. By lowering
the temperature for B 2 H 6 exposure (100 °C), the nonself-limiting
character of the B doping process can
be changed to self-limitation. By this manner, very
shallow doping profiles with low sheet resistance
have been obtained, capable for future ultra-shallow
junction applications. p atomic layer doping is shown
to be suitable for the creation of steep and narrow
doping profiles suitable for high-performance pnp
Heterojunction Bipolar transistors (HBts). this result,
together with the already demonstrated usage of B
atomic layer doping for npn HBts, demonstrates the
capability of the atomic layer processing approach for
future devices with critical requirements for dopant
dose and location control.
(39) High Quality Al 2 o 3 / Pr 2 o 3 / Al 2 o 3 MiM
Capacitors for RF Applications
Ch. Wenger, G. lippert, R. Sorge, t. Schroeder,
A.u. Mane, G. lupina, J. Dabrowski,
p. Zaumseil, X. Fan, l. oberbeck,
u. Schröder, H.-J. Müssig
Ieee transactions on electron Devices 53(8),
1937 (2006)
the electrical characteristics of layered
Al 2 o 3 / pr 2 o 3 / Al 2 o 3 metal–insulator–metal (MIM) capacitors
for RF device applications are presented for
the first time. this advanced dielectric layer system
4-nm Al 2 Ho 3 / 8-nm pr 2 o 3 / 4-nm Al 2 o 3 shows a high
capacitance density of 5.7 fF / µm 2 , a low leakage current
density of 5 x 10 -9 A / cm 2 at 1 V, and an excellent
dielectric loss behavior over the studied frequency
range.
(40) Chemical Vapor Phase Etching of Polycrystalline
Selective to Epitaxial SiGe
Y. Yamamoto, B. tillack, K. Köpke, o. Fursenko
thin Solid Films 508(1-2), 297 (2006)
Combination of nonselective Si / SiGe growth with selective
chemical vapor phase etching of poly-Si / SiGe
was investigated with the aim to create epitaxial
Si / SiGe in a selective manner. Directly after the nonselective
deposition, an HCl vapor phase etching was
performed within the same reactor (RpCVD) at diffe-
A n n u A l R e p o R t 2 0 0 6
141

142 A n n u A l R e p o R t 2 0 0 6
E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
rent process conditions (HCl partial pressure, etching
temperature) to remove the polycrystalline Si / SiGe
selectively to the epitaxial material. Microloading
effect of nonselective SiGe process was ignorable to
that of selective SiGe process. etching rate of poly-
Si / SiGe was higher than that of epitaxial Si / SiGe. We
found that there is a pattern size dependence of the
etching process which becomes smaller by increasing
HCl flow, indicating that high HCl flow condition is
required for uniform epitaxial Si / SiGe thickness. Selectivity
of polycrystalline to epitaxial Si / SiGe becomes
higher with increasing etching temperature. the
selectivity of polycrystalline to epitaxial etching for
SiGe can be improved by adding a thin Si cap layer
which will be partly removed during the etching process.
(41) P Doping Control During SiGe:C Epitaxy
Y. Yamamoto, B. tillack, K. Köpke, R. Kurps
thin Solid Films 508 (1-2), 288 (2006)
phosphorus (p) doping during SiGe:C epitaxy by using
reduced pressure chemical vapor deposition (RpCVD)
was investigated with the aim to prevent non-intended
doping and to create steep doping profiles. We
found that p diffusion during cap SiGe:C growth is
not a major cause for p autodoping. the source of p
autodoping is not the reactor but the wafer itself. By
unloading the wafer at < 200 °C in H 2 HF dip treatment
after p-doped SiGe:C layer deposition, p autodoping
was drastically suppressed. this means that the
source layer for p autodoping was partly removed by
the HF treatment. We also found that this layer could
not be removed by in-situ HCl dry etching after p-doped
SiGe:C layer deposition. lowering growth rate of
nondoped cap SiGe:C layer without changing temperature
improves the p autodoping at high p concentration.
By reducing growth temperature from 600 to
550 °C for nondoped SiGe:C cap layer keeping same
growth rate, steepness of p autodoping was improved
from 20.9 nm / dec to 8.7 nm / dec. By reducing
growth temperature further to 500 °C, steepness of
p autodoping is drastically improved to 3.4 nm / dec.
the impact of the growth temperature is indicating
segregation as the main factor for autodoping and
profile steepness. therefore, by reducing growth temperature
for SiGe cap layer deposition, non-intended
p doping could be suppressed resulting in very steep
p profiles applicable for devices with critical doping
profile requirements.
(42) Properties of Dislocation Networks Formed
by Si Wafer Direct bonding
X. Yu, t. Arguirov, M. Kittler, W. Seifert,
M. Ratzke, M. Reiche
Materials Science in Semiconductor
processing 9, 96 (2006)
Reproducible formation of well-controlled dislocation
structures is a prerequisite to use dislocations
as an active part of devices. Regular dislocation networks
have been formed at the interface by Si wafer
direct bonding. the barriers of interface were generally
smaller than 100 meV. the temperature dependence
of the electron-beam-induced current (eBIC)
contrast of the interface indicates a deep state density
of a few 10e5 per cm along the dislocation lines
in the network. It is also found that the dislocation
networks in Si can act as effective channel for carrier
transport. photoluminescence (pl) reveals that the
D line spectrum related to the dislocation networks
can be tailored by the bonding misorientation. So,
the D1 line can be made the dominating feature in
the pl spectrum. It is suggested that regular dislocation
networks represent an interesting new nanosystem
for future applications, such as accommodation
biomolecules onto silicon, dislocation-based leD or
buried nanowires.
(43) optimization of Anti-reflective Coatings
for High NA Lithography
J. Bauer, o. Fursenko, S. Virko, B. Kuck,
t. Grabolla, V. Melnik, W. Mehr
proc. 4 th Workshop ellipsometry, 94 (2006)
(44) Swing Curve Measurement and Simulation
for High NA Lithography
J. Bauer, u. Haak, K. Schulz, G. old, A. Kraft
proc. Microlithography 2006, SpIe, Metrology,
Inspection, and process Control for
Microlithography XX, 6152, 1209 (2006)

E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
(45) An Ultra-Wideband Low Power Consumption
Differential Low Noise Amplifier in
SiGe:C biCMoS Technology
p.K. Datta, G. Fischer
proc. Ieee Radio and Wireless Symposium,
RWS ‘06, 107 (2006)
(46) An Ultra-Wideband Transceiver Front-End
in SiGe:C biCMoS Technology
p.K. Datta, X. Fan, G. Fischer
proc. 2006 Ieee International Conference
on ultra-Wideband, 167 (2006)
(47) A Wireless Communication Platform
for Long-Term Health Monitoring
D. Dietterle, J.-p. ebert, G. Wagenknecht,
R. Kraemer
proc. of the 1 st Ieee International Workshop
on pervasive and ubiquitous Health Care
(ubiCare ‘06), Ieee Computer Society,
474 (2006)
(48) bASUMA - Ein körpernahes Funknetzwerk
für Telemonitoring
J.-p. ebert, t. Falck, J. espina
proc. 7. Würzburger Medizintechnik-Kongress
für medizinische Anwendungen im Krankenhaus,technologien-partnerschaftenpraktische
lösungen, abstract (2006)
(49) Leakage Current and Dopant Activation in
Ultra-Shallow Junctions Following Millisecond
Anneals Measured by Non-Contact
Junction Photo-Voltage Methods
V.n. Faifer, t.M.H. Wong, M.I.Curent,
D.K. Schroder, p.J. timans, S. McCoy, J. Gelpey,
W. lerch, S. paul, D. Bolze, t. Claryssee,
t. Zangerle, A. Moussa, W. Vandervorst
proc. American Vacuum Society 53rd International Symposium (2006)
(50) bASUMA - The Sixth Sense for Chronically
iii Patients
t. Falck, J. espina, J.-p. ebert, D. Dietterle
proc. Body Sensor networks (2006)
(51) An integrated Gaussian Modulated Pulse
Generator for Ultra-Wideband Wireless
Localization System
X. Fan, p.K. Datta, G. Fischer
proc. Joint China Japan Microwave Conference,
2, 566 (2006)
(52) SiGe:C biCMoS Technologie für 77 GHz
Radaranwendungen
G.G. Fischer
proc. ItG / BMBF Statusseminar “Automobile
Radarsensorik für Fahrerassistenzsysteme”,
VDe Kongress, 1, 349 (2006)
(53) Stability Constraints in SiGe Epitaxy
A. Fischer
the Silicon Heterostructure Handbook:
Materials, Fabrication, Devices, Circuits, and
Applications of SiGe and Si Strained layer
epitaxy / ed. J. Cressler, Boca Raton,
CRC press, 127 (2006)
(54) Combination of Spectroscopic Ellipsometry
and Reflectometry for Characterization
of Ni Silicide Process
o. Fursenko, D. Bolze, I. Costina, p. Zaumseil,
t. Huelsmann, W. lerch
proc. 4 th Workshop ellipsometry, 133 (2006)
(55) A broadband Low Spur Fully integrated
biCMoS PLL for 60 GHz Wireless Applications
S. Glisic, W. Winkler
proc. Ieee Radio and Wireless Symposium -
RWS ‘06, 451 (2006)
(56) A 10 GS / s 2 V pp Emitter Follower only
Track and Hold Amplifier in SiGe biCMoS
Technology
S. Halder, S.A. osmany, H. Gustat, B. Heinemann
proc. Ieee International Symposium on
Circuits and Systems (ISCAS ‘06), 4775 (2006)
(57) An 8 bit 10 GS / s 2 V pp Track and Hold
Amplifier in SiGe biCMoS Technology
S. Halder, H. Gustat, J.C. Scheytt
proc. eSSCIRC, 416 (2006)
A n n u A l R e p o R t 2 0 0 6
143

144 A n n u A l R e p o R t 2 0 0 6
E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
(58) High-Performance biCMoS Technologies
without Epitaxially-buried Subcollectors
and Deep Trenches
B. Heinemann, R. Barth, D. Knoll, H. Rücker,
B. tillack, W. Winkler
Conference Digest of 2006 3 rd International
SiGe technology and Device Meeting,
IStDM ‘06, 230 (2006)
(59) Creation of SiGe Radhard Library
H.-V. Heyer, u. Jagdhold
proc. 1 st International Workshop on Analog
and Mixed Signal Integrated Circuits for
Space Applications, AMICSA (2006)
(60) 1.5 µm Emission from a Silicon MoS-LED
based on a Dislocation Network
M. Kittler, M. Reiche, X. Yu, t. Arguirov,
o. Vyvenko, W. Seifert, t. Mchedlidze, G. Jia,
t. Wilhelm
IeDM technical Digest, 845 (2006)
(61) A Low-Cost, High-Performance, High-
Voltage Complementary biCMoS Process
D. Knoll, B. Heinemann, K.e. ehwald, A. Fox,
H. Rücker, R. Barth, D. Bolze, t. Grabolla,
u. Haak, J. Drews, B. Kuck, S. Marschmeyer,
H.H. Richter, M. Chaimanee, o. Fursenko,
p. Schley, B. tillack, K. Köpke, Y. Yamamoto,
H.e. Wulf, D. Wolansky
IeDM technical Digest, 607 (2006)
(62) industry Examples at State-of-the-Art: iHP
D. Knoll
the Silicon Heterostructure Handbook:
Materials, Fabrication, Devices, Circuits, and
Applications of SiGe and Si Strained layer
epitaxy / ed. J. Cressler, Boca Raton,
CRC press, 321 (2006)
(63) Siliziumbasierte Mikroelektronik für die
drahtlose Hochleistungskommunikation
R. Kraemer
proc. Fachtagung Mikroelektronik
“Microelectronics on the Move!” im Rahmen
des VDe-Kongresses, 1, 481 (2006)
(64) The institute of High Performance
Microelectronics: Excellent Research
Environment for PhD. Students and Post Doc
R. Kraemer
Digest of the 4 th Joint Symposium on optoand
Microelectronic Devices and Circuits
(SoDC ‘06), 109 (2006)
(65) A Graphical Tool for Specification, Rapid
Prototyping and implementation of
Location based Services
p. langendörfer, S. Adam
proc. Innovations for europe Mobility,
ItG-Fachtagung im Rahmen des
VDe-Kongresses, 1, 53 (2006)
(66) Efficient Protection of Mobile Devices by
Cross Layer interaction of Firewall
Approaches
p. langendörfer, M. lehmann, K. piotrowski
proc. 4 th International Conference on Wired /
Wireless Internet Communications
(WWIC 2006), Springer, lnCS 3970, 155 (2006)
(67) on the implementation of a Low-Power
iEEE 802.11a Compliant Viterbi Decoder
K. Maharatna, A. troya, M. Krstic, e. Grass
proc. VlSI Design Conference, 613 (2006)
(68) An optical indoor Positioning System for
the Mass Market
o. Maye, J. Schäffner, M. Maaser
proc. of 3 rd Workshop on positioning,
navigation and Communication –
WpnC ‘06, 111 (2006)
(69) Nanoelectronics – a Major Driver for Ultra-high
integration and Ulta-high Speed innovations
W. Mehr
proc. of nnFC International Symposium on
nanotechnology, 42 (2006)
(70) A Complementary RF-LDMoS Architecture
Compatible with 0.13 µm CMoS Technology
n. Mohapatra, H. Rücker, K.e. ehwald, R. Sorge,
R. Barth, p. Schley, D. Schmidt, H.e. Wulf

E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
proc. of the 18 th International Symposium on
power Semiconductor Devices and ICs
(ISpSD ‘06), 37 (2006)
(71) Atomically Controlled CVD Technology for
Group iV Semiconductors
J. Murota, M. Sakuraba, B. tillack
2006 8 th International Conference on Solid-
State and Integrated Circuit technology
proceedings, 440 (2006)
(72) Spike and Flash Annealing of Shallow
Arsenic and Phosphorus implants in
Different Gaseous Ambient
S. paul, W. lerch, S. McCoy, J. Gelpey, D. Bolze
proc. 16 th International Conference in Ion
Implantation technology (IIt ‘06), 109 (2006)
(73) How Public Key Cryptography influences
Wireless Sensor Node Lifetime
K. piotrowski, p. langendörfer, S. peter
proc. 4 th ACM Workshop on Security of Ad Hoc
and Sensor networks (SASn ‘06), 169 (2006)
(74) A Simple oFDM Physical Layer for Short-
Range High Data Rate Transmission at 60 GHz
M. piz, e. Grass
proc. 11 th International oFDM Workshop
(InoWo ‘06), 303 (2006)
(75) Carbon Plasma Etching in Advanced
Semiconductor Technologies
H.H. Richter, K.A. pears, M. Markert,
S. Marschmeyer, S. Günther,
G. Weidner, H. Silz
Verhandlungen der Deutschen physikalischen
Gesellschaft 5, 33 (2006)
(76) Single Crystalline Semiconductorinsulator-Semiconductor
Systems by oxide
Engineering and Lattice Matching
Approaches
t. Schroeder, I. Costina, p. Zaumseil, G. lupina,
Ch. Wenger, J. Dabrowski, H.-J. Müssig
proc. 13 th Workshop on oxide electronics,
abstracts book (2006)
(77) The iEEE 802.15.3 MAC Protocol Accelerator
for a body Area Sensor Network
H. Shah, D. Dietterle, J.-p. ebert, R. Kraemer
proc. of the 9 th International Symposium on
Wireless personal Communication (WpMC ‘06),
(2006)
(78) An implementation Study on Fault-Tolerant
LEoN-3 Processor System
Z. Stamenkovic, C. Wolf, G. Schoof, J. Gaisler
proc. Ip-Based SoC Design Conference, 23
(2006)
(79) LEoN-2: General Purpose Processor for a
Wireless Engine
Z. Stamenkovic, C. Wolf, G. Schoof, J. Gaisler
proc. of the 2006 Ieee Workshop on Design
and Diagnostics of electronic Circuits and
Systems, 50 (2006)
(80) SoC Design: Engineering or Art
Z. Stamenkovic
proc. 25 th Ieee International Conference on
Microelectronics, 401 (2006)
(81) A Fully Differential 60 GHz Receiver Front-
End with integrated PLL in SiGe:C biCMoS
Y Sun, S. Glisic, F. Herzel
proc. european Microwave Integrated Circuits
Conference, 198 (2006)
(82) An integrated 60 GHz Receiver Front-End in
SiGe:C biCMoS
Y. Sun, l. Wang, J. Borngräber, F. Herzel,
W. Winkler, R. Kraemer
proc. of the 6 th topical Meeting on Silicon
Monolithic Integrated Circuits in RF Systems
(SiRFIC ‘06), 269 (2006)
(83) An integrated 60 GHz Transceiver Front-
End for oFDM in SiGe biCMoS
Y. Sun, S. Glisic, M. piz, F. Herzel, K. Schmalz,
e. Grass, W. Winkler, J.C. Scheytt, R. Kraemer
Digest of the 4 th Joint Symposium on optoand
Microelectronic Devices and Circuits
(SoDC ‘06), 93 (2006)
A n n u A l R e p o R t 2 0 0 6
145

146 A n n u A l R e p o R t 2 0 0 6
E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
(84) Atomic Layer Processing for Future Micro-
and Nanotechnology
B. tillack
proc. of the International Symposium on
System Construction of Global-networkoriented
Information electronics, 11 (2006)
(85) SiGe:C biCMoS Technologies for High
Frequency Applications
B. tillack, B. Heinemann, D. Knoll, H. Rücker,
G.G. Fischer, W. Winkler, W. Mehr
proc. 2 nd International Workshop on new
Group IV Semiconductor nanoelectronics,
program and abstracts, 1 (2006)
(86) Strained SiGe and Si Epitaxy
B. tillack, p. Zaumseil
the Silicon Heterostructure Handbook:
Materials, Fabrication, Devices, Circuits, and
Applications of SiGe and Si Strained layer
epitaxy / ed. J. Cressler, Boca Raton, CRC press,
33 (2006)
(87) Transforming Protocol Specifications for
Wireless Sensor Networks into Efficient
Embedded System implementations
G. Wagenknecht, D. Dietterle, J.-p. ebert,
R. Kraemer
proc. 3 rd european Workshop on Wireless
Sensor networks (eWSn), Berlin, Springer,
lnCS 3868, 228 (2006)
(88) 77 GHz Automotive Radar Receiver Front-
end in SiGe:C biCMoS Technology
l. Wang, J. Borngräber, W. Winkler
proc. eSSCIRC, 388 (2006)
(89) A 0.7-1.4 GHz Variable band Low Noise
Amplifier for Multi-band Applications
l. Wang, W. Winkler, G. Wang, J. Borngräber
proc. 8 th International Conference on Solid-
State and Integrated Circuit technology
proceedings, 1547 (2006)
(90) Low Power Frequency Dividers in SiGe:C
biCMoS Technology
l. Wang, Y. Sun, J. Borngräber, A. thiede,
R. Kraemer
proc. of Ieee Mtt-S 6 th topical Meeting on
Silicon Monolithic Integrated Circuits in
RF Systems, 357 (2006)
(91) An improved Highly-Linear Low-Power
Down-Conversion Micromixer for 77 GHz
Automotive Radar in SiGe Technology
l. Wang, R. Kraemer, J. Borngräber
proc. Internat. Microwave Symposium (2006)
(92) High Quality Layered Pr 2 Ti 2 o 7 / Sio 2 MiM
Capacitor for Mixed-Signal Applications
Ch. Wenger, R. Sorge, t. Schroeder, A.u. Mane,
D. Knoll, J. Dabrowski, H.-J. Müssig
proc. of the 6 th topical Meeting on Silicon
Monolithic Integrated Circuits in RF Systems
(SiRFIC ‚06), 241 (2006)
(93) An indoor Localization System based on
DTDoA for Different Wireless LAN
F. Winkler, e. Fischer, e. Grass, p. langendörfer
proc. of 3 rd Workshop on positioning, navigation
and Communication - WpnC ‘06, 117 (2006)
(94) Front-End MMiC for Low-Cost 24 GHz Radar
Systems
W. Winkler, J. Borngräber
proc. International Radar Symposium
(IRS ‘06), 145 (2006)
(95) A Novel Approach to Self-organized Pattern
Formation of biomelcules at Silicon
Surfaces
A. Wolff, W. Fritzsche, M. Kittler, X. Yu,
M. Reiche, t. Wilhelm, M. Seibt, o. Voß
proc. International Symposium on DnA-Based
nanoscale Integration, 31 (2006)
(96) Phosphorus Segregation Control for SiGe:C
Epitaxy
Y. Yamamoto
Conference Digest of 2006 3 rd International

E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
SiGe technology and Device Meeting,
IStDM ‘06, 282 (2006)
(97) optical Properties, Elasto-optical Effects,
and Critical-Point Parameters of biaxially
Stressed Si 1-y C y Alloys on Si (001)
St. Zollner, V. Vartanian, J.p. lui, p. Zaumseil,
H.-J. osten, A.A. Demkov, B-Y nguyen
Conference Digest of 2006 3 rd International
SiGe technology and Device Meeting,
IStDM ‘06, 90 (2006)
(98) Design of a Wireless Communication
Platform for body Area Networks
D. Dietterle, G. Wang, J.-p. ebert, R. Kraemer
proc. of WWRF 16 (2006)
(99) High Performance SiGe biCMoS Technology
for High Frequency Applications
G.G. Fischer
proc. 36 th european Microwave Conference
(2006)
(100) SiGe:C biCMoS Technologien für 77/79 GHz
Automobilradar
G.G. Fischer
GMM-Workshop „Hochfrequenz-Halbleitertechnologien
für Automobilanwendungen“
(2006)
(101) SiGe:C biCMoS-Technologien für Mikroelek-
tronik-Anwendungen über 60 GHz
G.G. Fischer
GMM-Workshop Mikroelektronik-Anwendungen
(2006)
(102) UWb Transceiver for Data Communication
and indoor Localization
G. Fischer
proc. 36 th european Microwave Conference
(2006)
(103) SiGe iCs for the 77 GHz Automotive Radar
S. Glisic, l. Wang
proc. eeefCoM Workshop Hochfrequenztechnik,
Komponenten, Module und eMV (2006)
(104) Scalable Low-Power High-Speed biCMoS
ECL Library
H. Gustat
proc. 36 th european Microwave Conference
(2006)
(105) Ultra-High Speed A /D and D /A Converters
H. Gustat
proc. 36 th european Microwave Conference
(2006)
(106) 60 GHz RF-Frontend for 1 Gbit /s WLAN
Transceiver
F. Herzel
proc. 36 th european Microwave Conference
(2006)
(107) impact of Ni Layer Thickness and Anneal
Time on Nickel Silicide Formation by Rapid
Thermal Processing
t. Huelsmann, J. niess, W. lerch, o. Fursenko,
D. Bolze
proc. 14 th Ieee International Conference on
Advanced thermal processing of
Semiconductors (2006)
(108) 60 GHz SiGe Transceiver Frontend-iCs für
die drahtlose Nahfeldkommunikation
J.C. Scheytt, Y. Sun, S. Glisic, F. Herzel,
K. Schmalz, e. Grass, W. Winkler, R. Kraemer
proc. eeefCoM Workshop Hochfrequenztechnik,
Komponenten, Module und eMV
(2006)
(109) Frequenzagiler Synthesizer und effizienter
Leistungsverstärker für Multi-Standard
basisstationen
J.C. Scheytt
proc. BMBF Statusseminar (2006)
(110) High-Performance Mixed-Signal iCs in SiGe
biCMoS Technology
J.C. Scheytt, R. Kraemer
proc. european Microwave Week (2006)
A n n u A l R e p o R t 2 0 0 6
147

148 A n n u A l R e p o R t 2 0 0 6
E R S C H i E N E N E P U b L i K A T i o N E N – P U b L i S H E D P A P E R S
(111) An integrated 5 GHz Wideband Quadrature
Modem in SiGe:C biCMoS Technology
K. Schmalz, F. Herzel, M. piz
proc. of the 36 th european Microwave
Conference, 1656 (2006)
(112) Radar Circuits and Components
W. Winkler
proc. 36 th european Microwave Conference (2006)
(113) A 70 MHz – 4.1 GHz 5 th -order Elliptic gm-C
Low-Pass Filter in Complementary SiGe
Technology
l. Yuan, R. Krithivasan, W.-M.l. Kuo,
l. Xiangtao, J.D. Cressler, H. Gustat,
B. Heinemann
proc. of the Ieee Bipolar / BiCMoS Circuits
and technology Meeting, BCtM ‘06, 4.3.1.
(2006)
(114) 60 GHz Demonstrator in 0.25 µm SiGe:C
biCMoS Technology
e. Grass, M. piz, F. Herzel, K. Schmalz, Y. Sun,
S. Glisic, K. tittelbach-Helmrich
proc. Ieee 802.15 Meeting, Document
number: Ieee 802.15-06 / 0320r0 (2006)
(115) Protocol integration of 60 GHz PHY
e. Grass, K. tittelbach-Helmrich, D. Dietterle,
J.-p. ebert, R. Kraemer
proc. Ieee 802.15 Meeting, Doc.no:
Ieee 802.12-06 / 0127r0 (2006)
(116) NEPP: Negotiation Enhancements for
Privacy Policies
M. Maaser, S. ortmann, p. langendörfer
proc. W3C Workshop on languages for privacy
policy negotiation and Semantics-Driven
enforcement (2006)
(117) 60 GHz Channel Measurements for “Video
Supply in Trains, busses and Aircraft”
Scenario
M. peter, W. Keusgen, e. Grass
proc. Ieee 802.15 Meeting, Document
number: Ieee 802.15-06 / 0476r0 (2006)
Eingeladene Vorträge
invited Presentations
(1) biomolecular Sensing - and Potential
Contributions from Microelectronics
M. Birkholz
technische Fachhochschule Wildau,
January 26, 2006, Germany
(2) Körpernahe Funknetze zur Fernüberwachung
des Gesundheitszustandes von
Patienten
D. Dietterle
Gauss-Woche, Frankfurt (oder),
April 07, 2006, Germany
(3) bASUMA - body Area System for Ubiquitous
Multimedia Applications
J.-p. ebert
5. Schloß Steinhöfel Seminar of GI RGB and
German Chapter of ACM, Fürstenwalde,
April, 2006, Germany
(4) bASUMA - Ein körpernahes Funknetzwerk
für Telemonitoring
J.-p. ebert, t. Falck, J. espina
7. Würzburger Medizintechnik-Kongress für
medizinische Anwendungen im Krankenhaus,
technologien-partnerschaften-praktische
lösungen, Würzburg,
Mai 14-17, 2006, Germany
(5) Drahtlose Kommunikation in eingebetteten
Automobilsystemen - Stand und Vision der
Funktechnik für den Einsatz in Fahrzeugen
J.-p. ebert
Die Zuliefermesse: 7. Internationale Fachmesse
für teile, Module, Komponenten und
technologien, leipzig, June, 2006, Germany
(6) SiGe:C biCMoS Technologien für 77/79 GHz
Automobilradar
G.G. Fischer
GMM-Workshop „Hochfrequenz-Halbleitertechnologien
für Automobilanwendungen“,
München, June 22, 2006, Germany

E i N G E L A D E N E V o R T R Ä G E – i N V i T E D P R E S E N T A T i o N S
(7) UWb Transceiver Architecture for Robust
Location Determination
G. Fischer, J.C. Scheytt, R. Kraemer
Ieee International Microwave Symposium
Ieee-Mtt-S, Workshop WMA, San Francisco,
June 11-16, 2006, uSA
(8) Ultra-Wide band Transceiver für indoor
Lokalisierung und Datenkommunikation
G. Fischer
Workshop Analog Integrated Circuits,
tu Kaiserslautern, March 13, 2006, Germany
(9) broadband Wireless Communication at
60 GHz: Systems, Circuits and Technologies
e. Grass, M. piz, F. Herzel, K. Schmalz, Y. Sun,
S. Glisic, M. Krstic, K. tittelbach-Helmrich,
M. ehrig, W. Winkler, R, Kramer, J.C. Scheytt
Workshop “From Research to Innovation”,
Szczecin, May 17-19, 2006, poland
(10) High-Performance biCMoS Technologies
without Epitaxially-buried Subcollectors
and Deep Trenches
B. Heinemann, R. Barth, D. Knoll, H. Rücker,
B. tillack, W. Winkler
2006 3 rd International SiGe technology and
Device Meeting, IStDM 2006, princeton,
May 15-17, 2006, uSA
(11) Analytical Modeling of the interaction of
Vacancies and oxygen for oxide Precipita-
tion in RTA Treated Silicon Wafers
G. Kissinger, J. Dabrowski, A. Sattler,
C. Seuring, t. Müller, H. Richter, W. von Ammon
10 th International Symposium on Silicon
Materials, Science, and technology
(Semiconductor Silicon 2006), Denver,
May 07-12, 2006, uSA
(12) Dislocations in Solar Silicon:
Electrical Activity
M. Kittler
nordic Workshop on Crystalline Si Solar Cells,
oslo, January 23-24, 2006, norway
(13) iR-Emitter auf Si-basis
M. Kittler
ISF Hameln, Institutsseminar, Hameln,
november 21, 2006, Germany
(14) Regular Dislocation Networks in Silicon
M. Kittler
SoIteC, Bernin, June 26, 2006, France
(15) Regular Dislocation Networks in Silicon as
a Tool for Novel Device Application
M. Kittler, M. Reiche, W. Seifert, X. Yu,
t. Arguirov, o.F. Vyvenko, t. Mchedlidze,
t. Wilhelm
210 th eCS Meeting, Symposium ‚High purity
Silicon 9‘, Cancun,
october 29 - november 03, 2006, Mexico
(16) Silicon Nanostructures for iR Light
Emitters
M. Kittler, t. Arguirov, W. Seifert, X. Yu, G. Jia,
o.F. Vyvenko, t. Mchedlidze, M. Reiche,
t. Wilhelm, J. Sha, D. Yang
e-MRS Spring Meeting 2006, Symposium A:
Current trends in nanoscience, nice,
May 29 - June 02, 2006, France
(17) Automatisierungstechnik
R. Kraemer
BMBF-Workshop „Kommunikationstechnolo-
gien für das Internet der Dinge“, Köln,
September 22, 2006, Germany
(18) Car-to-Car-Kommunikation
R. Kraemer
technologietag Mitteldeutschland, Dresden,
november 08, 2006, Germany
(19) Gigabit Wireless Communication based on
integrated 60 GHz biCMoS Frontend
R. Kraemer
1. Informatik-Kooperationsworkshop,
Btu Cottbus, october 20, 2006, Germany
A n n u A l R e p o R t 2 0 0 6
149

150 A n n u A l R e p o R t 2 0 0 6
E i N G E L A D E N E V o R T R Ä G E – i N V i T E D P R E S E N T A T i o N S
(20) Kommunikations- und Sicherungsverfahren
für eingebettete Systeme
R. Kraemer
Symposium „Moderne Ausbildungsmethoden
und Simulation“, Dresden,
March 21 - 22, 2006, Germany
(21) Sensornetze im medizinischen Umfeld
R. Kraemer
3 rd leibniz Conference of Advanced Science,
lichtenwalde, october 12 - 14, 2006, Germany
(22) Siliziumbasierte Mikroelektronik für die
drahtlose Hochleistungskommunikation
R. Kraemer
Fachtagung Mikroelektronik „Microelectronics
on the Move!“ im Rahmen des VDe-Kongresses
2006, Aachen, october 24 - 25, 2006, Germany
(23) System and Circuit Research in iHP
R. Kraemer
4 th Joint Symposium on opto- and Microelectronic
Devices and Circuits (SoDC 2006),
Duisburg, September 03 - 08, 2006, Germany
(24) Verfahren zur ultraschnellen drahtlosen
Übertragung von Daten und deren
Anwendungen
R. Kraemer
Ringvorlesung „Das Internet und seine Anwendungen
(IV)“, Btu Cottbus,
May 09, 2006, Germany
(25) Advanced dielectrics for highly scaled
DRAM applications: The example of
( Pr 2 o 3 ) 1-x (Al 2 o 3 ) x mixed oxide systems
on TiN
G. lippert, H.-J. Müssig
Infineon Workshop on Dielectric Materials for
DRAM applications, Dresden,
March 16, 2006, Germany
(26) PrAlo 3 -based M-i-M Structures for
Advanced DRAM Applications
G. lippert
external Collaboration Workshop, Qimonda,
Dresden, September 07, 2006, Germany
(27) Development of 0.13 µm Shallow Trench
Etch Process
S. Marschmeyer
AMAt Workshop etch Customer Workshop,
Dresden, May 10, 2006, Germany
(28) Rod-like Defects in Silicon: Signatures of
Distinct RLD Structures Detected by
Various Measurement Methods
t. Mchedlidze, t. Arguirov, G. Jia, M. Kittler
International Conference on extended Defects
in Semiconductors, eDS 2006, Halle,
September 17-22, 2006, Germany
(29) Nanoelectronics – a Major Driver for Ultra-high
integration and Ulta-high Speed innovations
W. Mehr
nnFC International Symposium on
nanotechnology, Daejeon City,
March 2006, Republic of Korea
(30) Science to the Market – SiGe:C Technology
and RF Circuits and Systems for Mobile
Communication
W. Mehr
Workshop From Research to Innovation,
Szczecin, May 17-19, 2006, poland
(31) SiGe biCMoS Technologies for RF Mixed
Signal Circuits-Technology, Design Kit and
Circuit iPs
W. Mehr
Mentor Workshop, Frankfurt / Main,
oktober, 2006, Germany
(32) SiGe RF Mixed Signal Circuits and Technologies
– New Developments and Perspectives
(1 Gbit / s, LP Sensor Networks and Fiber
optics)
W. Mehr
tFH Wildau, December, 2006, Germany

E i N G E L A D E N E V o R T R Ä G E – i N V i T E D P R E S E N T A T i o N S
(33) Atomically Controlled Processing for Future
Si-based Devices
J. Murota, M. Sakuraba, B. tillack
2006 Advanced Research Workshop Future
trends in Microelectronics: up the nano Creek,
Crete, June 26-30, 2006, Greece
(34) Welche Rolle spielen neue dielektrische
Materialien in der Mikroelektronik?
H.-J. Müssig
Akademisches Festkolloquium der Btu
Cottbus, December 12, 2006, Germany
(35) Dopant Diffusion in SiGeC Alloys
H. Rücker, B. Heinemann, R. Kurps,
Y. Yamamoto
2 nd International SiGe & Ge: Materials,
processing, and Device Symposium, 210 th eCS
Meeting, Cancun,
october 29 - november 03, 2006, Mexico
(36) High-Performance Mixed-Signal iCs in SiGe
biCMoS Technology
J.C. Scheytt, R. Kraemer
european Microwave Week 2006, Manchester,
September 10, 2006, uK
(37) iHP - Technologien und elektrische
Möglichkeiten – Lösungen mit Analog
office
R.F. Scholz
3. AWR Anwendertreffen, München,
october 04, 2006, Germany
(38) Advanced Dielectrics for Highly Performing
and Functionalized Silicon based iCs
t. Schroeder
MInAteC Winter School electrochemistry for
the Semiconductor Industry, Grenoble,
December 11, 2006, France
(39) Global and Local Heteroepitaxy Approaches
in Si-based Microelectronics: Motivation,
Methods and Materials
t. Schroeder
Surface Science Seminar of the physics
Department of the university of osnabrück,
August, 18, 2006, Germany
(40) Materials for Si-based Nanoelectronics –
Discoveries and Challenges in Nanospace
t. Schroeder
Hanse-Wissenschafts-Kolloquium,
Delmenhorst, August 16, 2006, Germany
(41) Single Crystalline Heteroepitaxial
Semiconductor-insulator-Semiconductor
Systems on Si(111)
t. Schroeder
eSRF experimental Division Meeting, Grenoble,
May 23, 2006, France
(42) Ultra-Thin Dielectric Films for Si based
Nanoelectronic Device Technology
t. Schroeder
5 th International Workshop on Surfaces and
Interfaces, university of Marseille,
February 01-03, 2006, France
(43) SoC Design: Engineering or Art
Z. Stamenkovic
25 th Ieee International Conference on
Microelectronics, nis, May 14-17, 2006, Serbia
(44) Atomic Layer Processing for Future
Micro- and Nanotechnology
B. tillack
System Construction of Global-networkoriented
Information electronics, Sendai,
January 31 - February 01, 2006, Japan
(45) SiGe:C biCMoS Technologies for High
Frequency Applications
B. tillack, B. Heinemann, D. Knoll, H. Rücker,
G.G. Fischer, W. Winkler, W. Mehr
2 nd International Workshop on new Group IV
Semiconductor nanoelectronics, Sendai,
october 02, 2006, Japan
A n n u A l R e p o R t 2 0 0 6
151

152 A n n u A l R e p o R t 2 0 0 6
E i N G E L A D E N E V o R T R Ä G E – i N V i T E D P R E S E N T A T i o N S
(46) SiGe:C biCMoS Technologies for High Speed
Applications
B. tillack
etRI, Daejeon,
March 16, 2006, Republic of Korea
(47) SiGe:C biCMoS Technologies for High Speed
Applications
B. tillack
ntu – national taiwan university,
March 21, 2006, taiwan
(48) SiGe:C biCMoS Technologies for High Speed
Applications
B. tillack
nagoya university, nagoya,
December 16, 2006, Japan
(49) The Running 0.25 µm Technology as the
0.13 µm biCMoS, which is under
Development
B. tillack
CIC – Chip implementation Center taiwan,
March 20, 2006, taiwan
(50) Millimeter-wave integrated Cicruits in
SiGe:C biCMoS Technology
W. Winkler
uMC taiwan, March 21, 2006, Hsinchu, taiwan
(51) Millimeter-wave integrated Cicruits in
SiGe:C biCMoS Technology
W. Winkler
tSMC, Hsinchu, March 20, 2006, taiwan
(52) Millimeter-wave integrated Cicruits in
SiGe:C biCMoS Technology
W. Winkler
national taiwan university, taipei,
March 21, 2006, taiwan
(53) Millimeter-wave integrated Cicruits in
SiGe:C biCMoS Technology
W. Winkler
Chip Implementation Center taipei,
March 20, 2006, taiwan
Vorträge
Presentations
(1) Determination of Low Concentrations of N
and C in CZ-Si by Precise FTiR Spectroscopy
V.D. Akhmetov, H. Richter, n. Inoue
e-MRS 2006 Spring Meeting, nice,
May 29 - June 02, 2006, France
(2) Determination of Nitrogen in Thin CZ-Si
Wafers by Means of High Sensitive FTiR
Spectroscopy
V.D. Akhmetov, H. Richter
All-Russian Meeting „Silicon 2006“,
Krasnojarsk, July 04-06, 2006, Russia
(3) FTiR-Messungen an MQW
V.D. Akhmetov
BMBF-projekt-treffen „Bandstrukturdesign:
ladungsträgertransport in Si-basierten
Quantenstrukturen für zukünftige
Höchsteffizienz-Solarzellen“, Cottbus,
october 18- 20, 2006, Germany
(4) iR Spectroscopy of Carbon and boron States
in Highly Doped SiGe:C(b) Layers
V.D. Akhmetov, H. Richter
All-Russian Meeting „Silicon 2006“,
Krasnojarsk, July 04-06, 2006, Russia
(5) Nitrogen in Thin Silicon Wafers Determined
by Vibrational FTiR Spectroscopy with
Enhanced Sensitivity
V.D. Akhmetov, H. Richter
44. Arbeitskreis „punktdefekte“ Combined
with CADReS expert Group Meeting, Dresden,
March 23-25, 2006, Germany
(6) Precise FTiR Spectroscopy of Carbon and
boron in Thin SiGe:C(b) Layers
V.D. Akhmetov, H. Richter
44. Arbeitskreis „punktdefekte“ Combined
with CADReS expert Group Meeting, Dresden,
March 23-25, 2006, Germany

(7) Practical Scalable and Statistical Modeling
of SiGe HbT‘s
B. Ardouin, R.F. Scholz, G.G. Fischer, D. Knoll
HICuM Workshop 2006, Heilbronn,
June 12, 2006, Germany
(8) Effect of Mechanical Stress in Nanocrystalline
Si / Sio 2 Multiple Quantum Wells
t. Arguirov, t. Mchedlidze, M. Kittler, R. Rölver,
M. Först, o. Winkler, B. Spangenberg
International Conference on extended Defects
in Semiconductors, eDS 2006, Halle,
September 17-22, 2006, Germany
(9) Photoluminescence Study on Defects in
Multicrystalline Silicon
t. Arguirov, G. Jia, W. Seifert, M. Kittler
International Conference on Beam Injection
Assessment of Microstructures in Semiconductors
(BIAMS 2006), St. petersburg,
June 11-15, 2006, Russia
(10) Raman-Untersuchungen von mechanischen
Spannungen in MQW
t. Arguirov, t. Mchedlidze, M. Kittler
BMBF-projekt-treffen „Bandstrukturdesign:
ladungsträgertransport in Si-basierten
Quantenstrukturen für zukünftige Höchsteffizienz-Solarzellen“,
Cottbus,
october 18- 20, 2006, Germany
(11) Towards Silicon based Light Emitters
Utilising the Radiation from Dislocation
Networks
t. Arguirov, M. Kittler, W. Seifert, X. Yu
e-MRS Spring Meeting 2006, nice,
May 29 - June 02, 2006, France
(12) ARC and Swing optimization for High-NA
Photolithography
J. Bauer
4 th IISB lithography Simulation Workshop,
Hersbruck, September 29, 2006, Germany
V o R T R Ä G E – P R E S E N T A T i o N S
(13) optimization of Anti-reflective Coatings
for High NA Lithography
J. Bauer, o. Fursenko, S. Virko, B. Kuck,
t. Grabolla, V. Melnik, W. Mehr
4 th Workshop ellipsometry, Berlin,
February 20-22, 2006, Germany
(14) Swing Curve Measurement and Simulation
for High NA Lithography
J. Bauer, u. Haak, K. Schulz, G. old, A. Kraft
SpIe International Symposium on Microlithography
2006, San Jose,
February 19-24 2006, uSA
(15) beiträge der Materialforschung für die
Entwicklung der Fotovoltaik
M. Birkholz
lehrprobevortrag im Habilitationsverfahren
an der Btu Cottbus, June 28, 2006, Germany
(16) GiD and GiSAXS Characterization of biomolecules
on Semiconductors
M. Birkholz, I. Zizak, n. Darowski, I. Wallat,
p. Zaumseil, M. Kittler, M. p. Heyn
Bessy nutzertreffen, Berlin,
December 07-08, 2006, Germany
(17) Small-Angle X-Ray Reciprocal Space
Mapping of Surface Relief Gratings
M. Birkholz, p. Zaumseil, J. Bauer, D. Bolze,
G. Weidner
e-MRS Spring Meeting, nice,
May 29 - June 02, 2006, France
(18) Structure of biomembrane-on-Silicon
Hybrids Derived From X-Ray Reflectometry
M. Birkholz, p. Zaumseil, M. Kittler, I. Wallat,
M. Heyn
e-MRS 2006 Spring Meeting, nice,
May 29 - June 02, 2006, France
(19) The Evolution of Structural Properties
During the Growth of Thin Films
M. Birkholz
A n n u A l R e p o R t 2 0 0 6
153

Wissenschaftlicher Vortrag im Habilitationsverfahren
an der Btu Cottbus,
november 24, 2006, Germany
(20) A 20 GSample /s, 40 mW SiGe HbT
Comparator for Ultra-High-Speed ADC
Y. Borokhovych, H. Gustat
2 nd International SiGe & Ge: Materials,
processing, and Device Symposium, 210 th eCS
Meeting, Cancun,
october 29 - november 03, 2006, Mexico
(21) Ab initio Atomistic Calculations for CMoS
Technology Development
J. Dabrowski
5 th International Summerschool at IHp,
Frankfurt (oder),
August 28 - September 02, 2006, Germany
(22) Ab initio Calculations for CMoS Technology
Developments
J. Dabrowski
Workshop From Research to Innovation,
Szczecin, May 17-19, 2006, poland
(23) Charge States of Native Point Defects in
Pr-based High-k Dielectrics
J. Dabrowski, A. Fleszar, G. lupina, G. lippert,
A.u. Mane, Ch. Wenger
DpG Frühjahrstagung Dresden,
March 27-31, 2006, Germany
(24) Ti at interfaces between Si and High-k Films
J. Dabrowski
DpG Frühjahrstagung Dresden,
March 27-31, 2006, Germany
(25) An Ultra-Wideband Low Power Consumption
Differential Low Noise Amplifier in
SiGe:C biCMoS Technology
p.K. Datta, G. Fischer
Ieee Radio and Wireless Symposium, RWS 2006,
San Diego, January 17-19, 2006, uSA
154 A n n u A l R e p o R t 2 0 0 6
V o R T R Ä G E – P R E S E N T A T i o N S
(26) An Ultra-Wideband Transceiver Front-End
in SiGe:C biCMoS Technology
p.K. Datta, X. Fan, G. Fischer
2006 International Conference on ultra-
Wideband, Waltham,
September 24-27, 2006, uSA
(27) A Wireless Communication Platform for
Long-Term Health Monitoring
D. Dietterle, G. Wagenknecht, J.-p. ebert,
R. Kraemer
1 st Ieee International Workshop on pervasive
and ubiquitous Health Care (ubiCare 2006),
pisa, March 13, 2006, Italy
(28) Design of a Wireless Communication
Platform for body Area Networks
D. Dietterle, G. Wang, J.-p. ebert, R. Kraemer
WWRF 16, Shanghai, April 26-28, 2006, China
(29) bASUMA - A body Sensor System for
Telemedicine
J.-p. ebert, t. Falck
3 rd european Workshop on Wireless Sensor
networks (eWSn), Zurich,
February 13-15, 2006, Switzerland
(30) Leakage Current and Dopant Activation in
Ultra-Shallow Junctions Following Millisecond
Anneals Measured by Non-Contact
Junction Photo-Voltage Methods
V.n. Faifer, t.M.H. Wong, M.I. Curent,
D.K. Schroder, p.J. timans, S. McCoy,
J. Gelpey, W. lerch, S. paul, D. Bolze,
t. Claryssee, t. Zangerle, A. Moussa,
W. Vandervorst
American Vacuum Society 53 rd International
Symposium, San Francisco,
november 12-17, 2006, uSA
(31) bASUMA - The Sixth Sense for Chronically
iii Patients
t. Falck, J. espina, J.-p. ebert, D. Dietterle
Body Sensor networks, Cambridge,
April 03-05, 2006, uSA

(32) An integrated Gaussian Modulated Pulse
Generator for Ultra-Wideband Wireless
Localization System
X. Fan .
Joint China Japan Microwave Conference 2006,
Chengdu, August 24, 2006, China
(33) Contamination during High Temperature
Treatments in SiC Reactor Tubes
A. Fischer, V. Akhmetov, G. Kissinger,
M. Kittler
SIWeDS Fall Meeting, Cancun,
november 02-03, 2006, Mexico
(34) High Performance SiGe biCMoS Technology
for High Frequency Applications
G.G. Fischer
36 th european Microwave Conference 2006,
Manchester, September 10-15, 2006, uK
(35) SiGe:C biCMoS Technologie für 77 GHz
Radaranwendungen
G.G. Fischer
ItG / BMBF Statusseminar „Automobile Radarsensorik
für Fahrerassistenzsysteme“,
VDe Kongress Aachen,
october 24, 2006, Germany
(36) SiGe:C biCMoS Technologies for RF Auto-
motive Application
G.G. Fischer
5 th International Summerschool at IHp,
Frankfurt (oder),
August 28 - September 02, 2006, Germany
(37) SiGe:C biCMoS-Technologien für Mikroelektronik-Anwendungen
über 60 GHz
G.G. Fischer
GMM-Workshop Mikroelektronik-Anwendungen,
Duisburg, January 23, 2006, Germany
(38) UWb Transceiver for Data Communication
and indoor Localization
G. Fischer
36 th european Microwave Conference 2006,
Manchester, September 10-15, 2006, uK
V o R T R Ä G E – P R E S E N T A T i o N S
(39) Electron-Holographic Measurement of
“Dead Layer” Thickness, Amorphous
Surface Layer Thickness, Noise, and
inelastic Mean Free Path in Silicon
Specimens prepared by Argon Milling
and Fib
p. Formanek
the 16 th International Microscopy Congress
(IMC 16), Sapporo,
September 03-08, 2006, Japan
(40) Development and Characterization of a
Process Technology for a 0.25 µm SiGe:C
RF-biCMoS embedded Flash Memory
A. Fox .
5 th International Summerschool at IHp,
Frankfurt (oder),
August 28 - September 02, 2006, Germany
(41) Combination of Spectroscopic Ellipsometry
and Reflectometry for Characterization
of Ni Silicide Process
o. Fursenko, D. Bolze, I. Costina, p. Zaumseil,
t. Huelsmann, W. lerch
4 th Workshop ellipsometry, Berlin,
February 20-22, 2006, Germany
(42) Vollkostenrechnung im iHP
u. George
Workshop Finanzielle und rechtliche Aspekte
bei eu projekten im 6. und 7. Forschungsrahmenprogramm,
Dresden,
november 02, 2006, Germany
(43) A broadband Low Spur Fully integrated
biCMoS PLL for 60 GHz Wireless
Applications
S. Glisic, W. Winkler
Ieee Radio and Wireless Symposium – RWS
2006, San Diego, January 17-19, 2006, uSA
(44) SiGe iCs for the 77 GHz Automotive Radar
S. Glisic
eeefCoM Workshop, Hochfrequenztechnik,
Komponenten, Module und eMV, ulm,
June 27-29, 2006, Germany
A n n u A l R e p o R t 2 0 0 6
155

(45) 60 GHz Demonstrator in 0.25 µm SiGe:C
biCMoS Technology
e. Grass, M. piz, F. Herzel, K. Schmalz, Y. Sun,
S. Glisic, K. tittelbach-Helmrich
Ieee 802.15 Meeting, San Diego,
July 2006, uSA
(46) 60 GHz oFDM Demonstrator in SiGe biCMoS
Technology
e. Grass, M. piz, F. Herzel, K. Schmalz, Y. Sun,
S. Glisic, K. tittelbach-Helmrich, M. Krstic,
M. ehrig, R. Kraemer, J.C. Scheytt
BMBF Statusseminar 2006, Mobile Kommunikation
und Gan-elektronik, Fraunhofer
Institut für Integrierte Schaltungen – IIS,
erlangen, June 21-22, 2006, Germany
(47) Protocol integration of 60 GHz PHY
e. Grass, K. tittelbach-Helmrich, D. Dietterle,
J.-p. ebert, R. Kraemer
Ieee 802.15 Meeting, Denver,
March, 2006, uSA
(48) Scalable Low-Power High-Speed biCMoS
ECL Library
H. Gustat, G. Kell
36 th european Microwave Conference 2006,
Manchester, September 10-15, 2006, uK
(49) Ultra-High Speed A / D and D / A Converters
H. Gustat
36 th european Microwave Conference 2006,
Manchester, September 10-15, 2006, uK
(50) A 10 GS /s 2 V pp Emitter Follower only
Track and Hold Amplifier in SiGe biCMoS
Technology
S. Halder, S.A. osmany, H. Gustat,
B. Heinemann
Ieee International Symposium on Circuit
and Systems 2006 (ISCAS 2006), Island of Kos,
May 21-24, 2006, Greece
(51) An 8 bit 10 GS /s 2 V pp Track and Hold
Amplifier in SiGe biCMoS Technology
S. Halder, H. Gustat, J.C. Scheytt
156 A n n u A l R e p o R t 2 0 0 6
V o R T R Ä G E – P R E S E N T A T i o N S
eSSCIRC 2006, Montreux,
September 18-22, 2006, Switzerland
(52) Si-bauelemente am iHP - von Hochfrequenz-
und Hochvolttransistoren zum
VLSi-Schaltkreis
B. Heinemann
Festkolloquium „40 Jahre Forschung für die
Siliziumelektronik“, Frankfurt (oder),
April 10, 2006, Germany
(53) 60 GHz RF-Frontend for 1 Gbit /s WLAN
Transceiver
F. Herzel
36 th european Microwave Conference 2006,
Manchester, September 10-15, 2006, uK
(54) 60 GHz Transceiver Analog Frontend
F. Herzel
German-Korean Workshop on nanotechnology
nnFC - IHp, Frankfurt (oder),
February 14-15, 2006, Germany
(55) Creation of SiGe Radhard Library
H.-V. Heyer, u. Jagdhold
1 st International Workshop on Analog and
Mixed Signal Integrated Circuits for Space
Applications, AMICSA 2006, Xanthi,
october 02-03, 2006, Greece
(56) European Low Noise Local oscillator MMiC
in SiGe Technology at 10 GHz and 18.3 GHz:
the SiMs Project
H.-V. Heyer, R. Follmann, D. Köther, K. Schmalz,
F. Herzel, W. Winkler, J. nilsson, B.-M. Folio,
B. Glass
Microwave technology and techniques Workshop
enabling Future Space Systems, estec,
noordwijk, May 15-16, 2006, the netherlands
(57) impact of Ni Layer Thickness and Anneal
Time on Nickel Silicide Formation by Rapid
Thermal Processing
t. Huelsmann, J. niess, W. lerch, o. Fursenko,
D. Bolze
Rtp 2006-14 th Ieee International Conference

on Advanced thermal processing of Semiconductors,
Kyoto, october 10-13, 2006, Japan
(58) infrared Absorption Measurement of
Carbon Concentration in Silicon Crystals
n. Inoue, M. nakatsu, V. D. Akhmetov
eCS 10 th International Symposium on Silicon
Materials Science and technology, Denver,
May 07-12, 2006, uSA
(59) Einführung in das digitale VLSi-Design
u. Jagdhold
Fachhochschule lausitz, Senftenberg,
December 20, 2006, Germany
(60) Radiation Hardness
u. Jagdhold
5 th Workshop High-performance SiGe BiCMoS
for Wireless and Broadband Communication,
Frankfurt (oder),
September 25-26, 2006, Germany
(61) Cathodoluminescence investigation of
Silicon Nanowires
G. Jia, t. Arguirov, M. Kittler, Z. Su, D. Yang,
J. Sha
44. Arbeitskreis punktdefekte Combined with
CADReS expert Group Meeting, Dresden,
March 23-25, 2006, Germany
(62) Cathodoluminescence investigation on
Silicon Nanowires Fabricated by Thermal
Evaporation of Sio
G. Jia, t. Arguirov, M. Kittler, Z. Su, D. Yang,
J. Sha
International Conference on Beam Injection
Assessment of Microstructures in Semiconductors
(BIAMS 2006), St. petersburg,
June 11-15, 2006, Russia
(63) Luminescence of Silicon Nanowires
G. Jia, t. Arguirov, M. Kittler, D. Yang, J. Sha
International Conference on extended Defects
in Semiconductors 2006 (eDS 2006), Halle,
September 17-22, 2006, Germany
V o R T R Ä G E – P R E S E N T A T i o N S
(64) Defect Studies in Si 1-x Ge x Alloys and
Si / Si 1-x-y Ge x C y Multilayers
S. Kalem, e.V. lavrov, G. Kissinger, Y. Zhang,
A.n. larsen, H. Radamson, J. Weber
2 nd CADReS Workshop, Kalyves,
September 08-11, 2006, Greece
(65) innovative Mikroelektronik am iHP –
von ideen bis zu optimierten Prozessen
W. Kissinger
tagung der Kommission operations Research
des Verbandes der Hochschullehrer für
Betriebswirtschaft e.V. und der Deutschen
Gesellschaft für operations Research, europauniversität
Viadrina, Frankfurt (oder),
February 10, 2006, Germany
(66) interaction of Vacancies and oxygen for
oxide Precipitation in RTA Treated Silicon
Wafers
G. Kissinger, J. Dabrowski, A. Sattler,
C. Seuring, t. Müller, W. von Ammon
e-MRS Spring Meeting 2006, Symposium V:
Advanced Silicon for the 21 st Centry, nice,
May 29 - June 02, 2006, France
(67) Nanoelectronics and Ultrafast Communica-
tions Technology R&D at the iHP
W. Kissinger
Workshop „Future Developments in organic
electronics and photonics“, tFH Wildau,
June 27, 2006, Germany
(68) oxide Precipitation via Coherent “Seed”oxide
Phases
G. Kissinger, J. Dabrowski
High purity Silicon IX, 210 th eCS Meeting,
Cancun, october 29 - november 03, 2006, Mexico
(69) oxide Precipitation via Coherent “Seed”oxide
Phases
G. Kissinger, J. Dabrowski
2 nd CADReS Workshop, Kalyves,
Spetember 08-11, 2006, Greece
A n n u A l R e p o R t 2 0 0 6
157

(70) 1.5 µm Emission from a Silicon MoS-LED
based on a Dislocation Network
M. Kittler, M. Reiche, X. Yu, t. Arguirov,
o. Vyvenko, W. Seifert, t. Mchedlidze, G. Jia,
t. Wilhelm
2006 Ieee International electron Device
Meeting, IeDM 2006, San Francisco,
December 11-13 2006, uSA
(71) Light Emitters based on Silicon
Nanostructures
M. Kittler
German-Korean Workshop on nanotechnology
nnFC - IHp, Frankfurt (oder),
February 14-15, 2006, Germany
(72) A Low-Cost, High-Performance, High-
Voltage Complementary biCMoS Process
D. Knoll, B. Heinemann, K.-e. ehwald, A. Fox,
H. Rücker, R. Barth, D. Bolze, t. Grabolla,
u. Haak, J. Drews, B. Kuck, S. Marschmeyer,
H.H. Richter, M. Chaimanee, o. Fursenko,
p. Schley, B. tillack, K. Köpke, Y. Yamamoto,
e. Wulf, D. Wolansky
2006 Ieee International electron Device
Meeting, IeDM 2006, San Francisco,
December 11-13, 2006, uSA
(73) iHP‘s 0.25 µm biCMoS Technologies
D. Knoll
5 th Workshop High-performance SiGe BiCMoS
for Wireless and Broadband Communication,
Frankfurt (oder),
September 25-26, 2006, Germany
(74) Extraction of CTH with Pulsed Measurements
F. Korndörfer
Bipolar Arbeitskreis, erfurt,
october 27, 2006, Germany
(75) 60 GHz Communication Systems
R. Kraemer, e. Grass
Wireless World Research Forum Meeting 17,
Heidelberg, november 15-17, 2006, Germany
158 A n n u A l R e p o R t 2 0 0 6
V o R T R Ä G E – P R E S E N T A T i o N S
(76) An integrated 60 GHz Transceiver Front-
End for oFDM in SiGe: biCMoS
R. Kraemer, Y. Sun, S. Glisic, M. piz, F. Herzel,
K. Schmalz, e. Grass, W. Winkler, J.C. Scheytt
4 th Joint Symposium on opto- and Microelectronic
Devices and Circuits (SoDC 2006),
Duisburg, September 03 -08, 2006, Germany
(77) Drahtlose Kommunikation in eingebetteten
Automobilsystemen - Stand und Vision der
Funktechnik für den Einsatz in Fahrzeugen
R. Kraemer
8. Kongress Wireless technologies, Dortmund,
September 27-28, 2006, Germany
(78) Herausforderungen der Car-to-Car-
Kommunikation
R. Kraemer
2. Wirtschaftstreffen „IHp trifft Automotive“,
Frankfurt (oder), April 19, 2006, Germany
(79) iHP innovations and Research in Wireless
Systems
R. Kraemer
5 th International Summerschool at IHp,
Frankfurt (oder),
August 28 - September 02, 2006, Germany
(80) iHP Systems Circuits
R. Kraemer
German-Korean Workshop on nanotechnology
nnFC - IHp, Frankfurt (oder),
February 14-15, 2006, Germany
(81) iHP meets Automotive
R. Kraemer
2. Wirtschaftstreffen „IHp trifft Automotive“,
Frankfurt (oder), April 19, 2006, Germany
(82) UWb Transceiver for Data Communication
and indoor Localization
R. Kraemer, G. Fischer
WWRF 16, Shanghai, April 26-28, 2006, China

(83) Asynchronous and Synchronous Design
Methods for Communication Systems and
Applications
M. Krstic
1 st International Conference for Young
Researchers in Computer Science, Control,
electrical engineering and telecommunications,
ICYR 2006, Zielona Gora,
September 08, 2006, poland
(84) A Graphical Tool for Specification, Rapid
Prototyping and implementation of
Location based Services
p. langendörfer, S. Adam
Innovations for europe Mobility, ItG-Fachtagung
im Rahmen des VDe-Kongresses 2006,
Aachen, october 23-24, 2006, Germany
(85) Efficient Protection of Mobile Devices by
Cross Layer interaction of Firewall
Approaches
p. langendörfer, M. lehmann, K. piotrowski
4 th International Conference on Wired / Wireless
Internet Communications (WWIC 2006),
Bern, May 10-12, 2006, Switzerland
(86) interface Reactions between High K
Praseodymium Aluminate and TiN
G. lippert, J. Dabrowski, I. Costina, G. lupina,
V. Melnik, l. oberbeck, u. Schröder,
t. Schroeder, Ch. Wenger, p. Zaumseil,
H.-J. Müssig
e-MRS Spring Meeting 2006, Symposium l:
Characterization of High-k Dielectric Materials,
nice, May 29 - June 02, 2006, France
(87) innovative Materials: Key to Advances in
Microelectronics
G. lupina
Workshop From Research to Innovation,
Szczecin, May 17-19, 2006, poland
(88) Modern CMoS Transistor Physics
G. lupina
5 th International Summerschool at IHp,
V o R T R Ä G E – P R E S E N T A T i o N S
Frankfurt (oder),
August 28 - September 02, 2006, Germany
(89) Praseodymium Silicate High-k Dielectric
Layers on Si(100)
G. lupina, t. Schroeder, J. Dabrowski,
Ch. Wenger, A.u. Mane, G. lippert,
H.-J. Müssig
DpG Frühjahrstagung Dresden,
March 27-31, 2006, Germany
(90) Praseodymium Silicate High-k Dielectrics
G. lupina, t. Schroeder, Ch. Wenger,
H.-J. Müssig
e-MRS IuMRS ICeM Spring Meeting 2006, nice,
May 29 - June 02, 2006, France
(91) Praseodymium Silicate High-k Dielectrics
for CMoS Gate Dielectric Applications
G. lupina, t. Schroeder, Ch. Wenger,
J. Dabrowski, D. Schmeißer, H.-J. Müssig
Junior euromat 2006, lausanne,
September 04-08, 2006, Switzerland
(92) NEPP: Negotiation Enhancements for
Privacy Policies
M. Maaser, S. ortmann, p. langendörfer
W3C Workshop on languages for privacy
policy negotiation and Semantics-Driven
enforcement, Ispra, october 17-18, 2006, Italy
(93) on the implementation of a Low-Power
iEEE 802.11a Compliant Viterbi Decoder
K. Maharatna, A. troya, M. Krstic, e. Grass
VlSI Design Conference, Hyderabad,
January 03-07, 2006, India
(94) Atomic Vapour Deposition of High-k Hfo 2 :
Growth Kinetics and Electrical Properties
A.u. Mane, Ch. Wenger, J. Dabrowski,
G. lupina, t. Schroeder, G. lippert, R. Sorge,
p. Zaumseil, G. Weidner, I. Costina,
H.-J. Müssig, S. pasko, u. Weber, V. Méric,
M. Schumacher
DpG Frühjahrstagung Dresden,
March 27-31, 2006, Germany
A n n u A l R e p o R t 2 0 0 6
159

(95) iHP ADS and Catena Design Kits
t. Mausolf
5 th Workshop High-performance SiGe BiCMoS
for Wireless and Broadband Communication,
Frankfurt (oder),
September 25-26, 2006, Germany
(96) An optical indoor Positioning System for
the Mass Market
o. Maye, J. Schäffner, M. Maaser
3 rd Workshop on positioning, navigation and
Communication - WpnC 2006, Hannover,
March 16, 2006, Germany
(97) Effect of Various Substrates and Various
Heat Treatments on Crystallinity of Si
Layers in MQW Structures
t. Mchedlidze, t. Arguirov, S. Kouteva-
Arguirova, G. Jia, M. Kittler
BMBF-projekt-treffen „Bandstrukturdesign:
ladungsträgertransport in Si-basierten
Quantenstrukturen für zukünftige Höchsteffizienz-Solarzellen“,
Cottbus,
october 18- 20, 2006, Germany
(98) Electro- and Photoluminescence from
b and Si implanted p-n Junctions
t. Mchedlidze, t. Arguirov, M. Kittler
Seminar university of twente, enschede,
october 04, 2006, the netherlands
(99) Fe-P Complexes in n-Si
t. Mchedlidze, M. Kittler
44. Arbeitskreis punktdefekte Combined with
CADReS expert Group Meeting, Dresden,
March 23-25, 2006, Germany
(100) Structural and optical Properties of
Si / Sio 2 Multi-Quantum Wells
t. Mchedlidze, t. Arguirov, M. Kittler, R. Rölver,
B. Berghoff, M. Först, B. Spangenberg
e-MRS 2006, Symposium C, nice,
May 29 - June 02, 2006, France
160 A n n u A l R e p o R t 2 0 0 6
V o R T R Ä G E – P R E S E N T A T i o N S
(101) High-Performance SiGe biCMoS for Wireless
and broadband Communication and
Tutorial iHP Design Kits
W. Mehr
5 th Workshop High-performance SiGe BiCMoS
for Wireless and Broadband Communication,
Frankfurt (oder),
September 25-26, 2006, Germany
(102) Technologies and Circuits for Wireless
Communication
W. Mehr
5 th International Summerschool at IHp,
Frankfurt (oder),
August 28 - September 02, 2006, Germany
(103) A Complementary RF-LDMoS Architecture
Compatible with 0.13 µm CMoS Technology
n. Mohapatra, H. Rücker, K.e. ehwald, R. Sorge,
R. Barth, p. Schley, D. Schmidt, H.e. Wulf
18 th International Symposium on power
Semiconductor Devices and ICs (ISpSD 2006),
napoli, June 04-08, 2006, Italy
(104) High-k Dielectrics and Examples of
Application
H.-J. Müssig
German-Korean Workshop on nanotechnology
nnFC – IHp, Frankfurt (oder),
February 14-15, 2006, Germany
(105) Phase Noise and Jitter Modeling for
Fractional-N PLLs
S.A. osmany, F. Herzel, K. Schmalz, W. Winkler
„Integrierte digitale und analoge Schaltungen“
- Kleinheubacher tagung,
September 25-29, 2006, Germany
(106) Spike and Flash Annealing of Shallow
Arsenic and Phosphorus implants in
Different Gaseous Ambient
S. paul, W. lerch, S. McCoy, J. Gelpey, D. Bolze
16 th International Conference in Ion Implantation
technology IIt – 2006, Marseille,
June 11-16, 2006, France

(107) 60 GHz Channel Measurements for “Video
Supply in Trains, busses and Aircraft”
Scenario
M. peter, W. Keusgen, e. Grass
Ieee 802.15 Meeting, Dallas,
november 14, 2006, uSA
(108) How Public Key Cryptography influences
Wireless Sensor Node Lifetime
K. piotrowski, p. langendörfer, S. peter
4 th ACM Workshop on Security of Ad Hoc and
Sensor networks (SASn 2006), Alexandria,
october 30, 2006, uSA
(109) A Simple oFDM Physical Layer for Short-
Range High Data Rate Transmission at
60 GHz
M. piz, e. Grass
11 th International oFDM Workshop (InoWo ‘06)
Hamburg, August 31, 2006, Germany
(110) Quantum Effects in Si Nanocrystals
Embedded in oxide or Amorphous Matrix
p.n. Racec
BMBF-projekt-treffen „Bandstrukturdesign:
ladungsträgertransport in Si-basierten
Quantenstrukturen für zukünftige Höchsteffizienz-Solarzellen“,
Cottbus,
october 18-20, 2006, Germany
(111) Si / SiGe Double barrier Resonant Tunneling
Diodes
p.n. Racec, e.R. Racec, u. Wulf, G. Kissinger,
H. Richter
1 st leibnitz Conference of Advanced Science,
nanoscience 2005, lichtenwalde,
october 06-08, 2006, Germany
(112) on the Reliability of Scanning Probe based
Electrostatic Force Measurements
M. Ratzke, J. Reif
e-MRS 2006, Symposium F, nice,
May 29 - June 02, 2006, France
V o R T R Ä G E – P R E S E N T A T i o N S
(113) Scanning Probe based Electrical Characterization
of Dislocation Networks Formed by
Wafer Direct bonding
M. Ratzke, o. Vyvenko, X. Yu, J. Reif, M. Kittler,
M. Reiche
International Conference on extended Defects
in Semiconductors 2006 (eDS 2006), Halle,
September 17-22, 2006, Germany
(114) Light Emission by Dislocations in Silicon
M. Reiche, M. Kittler, t. Wilhelm, t. Arguirov,
W. Seifert, X. Yu
leoS 2006, 19 th Annual Meeting of the Ieee
lasers and electro-optics Society, Montreal,
october 29 - november 02, 2006, Canada
(115) Electrical Properties of Laser-Ablationinitiated
Self-oganized Nanostructures on
Silicon Surface
J. Reif, M. Ratzke, o. Varlamova, F. Costache
e-MRS 2006, Symposium V, nice,
May 29 - June 02, 2006, France
(116) Carbon Plasma Etching in Advanced
Semiconductor Technologies
H.H. Richter, K.A. pears, M. Markert,
S. Marschmeyer, S. Günther, G. Weidner,
H. Silz
DpG Frühjahrstagung Augsburg,
March 27-30, 2006, Germany
(117) 0.13 µm biCMoS Development
H. Rücker
5 th Workshop High-performance SiGe BiCMoS
for Wireless and Broadband Communication,
Frankfurt (oder),
September 25-26, 2006, Germany
(118) SiGe biCMoS Technology
H. Rücker
German-Korean Workshop on nanotechnology
nnFC - IHp, Frankfurt (oder),
February 14-15, 2006, Germany
A n n u A l R e p o R t 2 0 0 6
161

(119) Technologies for Radio Frequency
Applications
H. Rücker
5 th International Summerschool at IHp,
Frankfurt (oder),
August 28 - September 02, 2006, Germany
(120) 60 GHz SiGe Transceiver Frontend-iCs für
die drahtlose Nahfeldkommunikation
J.C. Scheytt, Y. Sun, S. Glisic, F. Herzel,
K. Schmalz, e. Grass, W. Winkler, R. Kraemer
eeefCoM Workshop, Hochfrequenztechnik,
Komponenten, Module und eMV, ulm,
June 27-29, 2006, Germany
(121) Frequenzagiler Synthesizer und effizienter
Leistungsverstärker für Multi-Standard
basisstationen
J.C. Scheytt
BMBF Statusseminar 2006 in erlangen,
June 20-22, 2006, Germany
(122) RF Circuit Design at iHP
J.C. Scheytt
5 th Workshop High-performance SiGe BiCMoS
for Wireless and Broadband Communication,
Frankfurt (oder),
September 25-26, 2006, Germany
(123) E-Test Measurements for biCMoS and Flash
Technologies - Experiences and Problems
p. Schley, A. Fox, B. Heinemann, D. Knoll,
H. Rücker
Keithley user Meeting, prague,
october 08, 2006, Czech Republic
(124) An integrated 5 GHz Wideband Quadrature
Modem in SiGe:C biCMoS Technology
K. Schmalz, F. Herzel, M. piz
36 th european Microwave Conference 2006,
Manchester, September 10-15, 2006, uK
(125) Cadence Design Kit and MPW Service
R.F. Scholz
5 th Workshop High-performance SiGe BiCMoS
for Wireless and Broadband Communication,
162 A n n u A l R e p o R t 2 0 0 6
V o R T R Ä G E – P R E S E N T A T i o N S
Frankfurt (oder),
September 25-26, 2006, Germany
(126) Design Kit & Multi Project Wafer Service
R.F. Scholz
German-Korean Workshop on nanotechnology
nnFC - IHp, Frankfurt (oder),
February 14-15, 2006, Germany
(127) Heteroepitaxial (Pr 2 o 3 ) 1-x (Y 2 o 3 ) Mixed
oxide Systems on Si Substrates as buffer
Layers for the Preparation of High -Quality
Single Crystalline Layer Systems
t. Schroeder, H.-J. Müssig
project Review Siltronic, Burghausen,
February, 2006, Germany
(128) on the Epitaxy of Twin-free Cubic (111)
Praseodymium Sesquioxide Films on
Si(111)
t. Schroeder, Ch. Wenger, H.-J. Müssig
DpG Frühjahrstagung Dresden,
March 27-31, 2006, Germany
(129) oxide Engineering and Lattice Matching
Approaches for the Preparation of Single
Crystalline Semiconductor-insulator-
Semiconductor Systems
t. Schroeder
Materials Science Seminar of tu Dresden,
october 07, 2006, Germany
(130) Physics of Metal-oxide-Semiconductor
(MoS) Structures
t. Schroeder
5 th International Summerschool at IHp,
Frankfurt (oder),
August 28 - September 02, 2006, Germany
(131) Studying the CMoS Process Compatibility
of Praseodymium Silicate Layers on
Si(001): Physical, Electrical, Thermal and
Etching Properties
t. Schroeder, G. lupina, Ch. Wenger, A.u. Mane,
J. Dabrowski, H.-J. Müssig
14 th Workshop on Dielectrics in Microelectro-

nics (WoDIM), Catania,
June 26-28, 2006, Italy
(132) An implementation Study on Fault-Tolerant
LEoN-3 Processor System
Z. Stamenkovic, C. Wolf, G. Schoof, J. Gaisler
Ip-Based SoC Design Conference, Grenoble,
December 06-07, 2006, France
(133) LEoN-2: General Purpose Processor for
a Wireless Engine
Z. Stamenkovic, C. Wolf, G. Schoof, J. Gaisler
9 th Ieee Workshop on Design and Diagnostics
of electronic Circuits and Systems, prague,
April 18-21, 2006, Czech Republic
(134) A Fully Differential 60 GHz Receiver Front-
End with integrated PLL in SiGe:C biCMoS
Y. Sun, S. Glisic, F. Herzel
european Microwave Integrated Circuits
Conference 2006, Manchester,
September 10-15, 2006, uK
(135) A Fully Differential 60 GHz Receiver Front-
End with integrated PLL in SiGe:C biCMoS
Y Sun, S. Glisic, F. Herzel
5 th Workshop High-performance SiGe BiCMoS
for Wireless and Broadband Communication,
Frankfurt (oder),
September 25-26, 2006, Germany
(136) An integrated 60 GHz Receiver Front-End
in SiGe:C biCMoS
Y. Sun, l. Wang, J. Borngräber, F. Herzel,
W. Winkler, R. Kraemer
the 6 th topical Meeting on Silicon Monolithic
Integrated Circuits in RF Systems (SiRFIC)
2006, San Diego, January 18-20, 2006, uSA
(137) An integrated 60 GHz Transceiver Front-
End for oFDM in SiGe biCMoS
Y. Sun, S. Glisic, F. Herzel, K. Schmalz, e. Grass,
W. Winkler, R. Kraemer
WWRF 16, Shanghai, April 26-28, 2006, China
V o R T R Ä G E – P R E S E N T A T i o N S
(138) Standardization of Test Methods of bulk
Microdefects and Denuded Zone in
Annealed CZ Si
R. takada, n. Inoue, K. Moriya, K. Kashima,
K. nakashima, M. Kato, S. Kitagawa, t. ono,
H. uzushido, n. nango and V. Akhmetov
eCS 10 th International Symposium on Silicon
Materials Science and technology, Denver,
May 07-12, 2006, uSA
(139) Development of SiGe biCMoS Technologies
at the iHP: introduction
B. tillack
5 th Workshop High-performance SiGe BiCMoS
for Wireless and Broadband Communication,
Frankfurt (oder),
September 25-26, 2006, Germany
(140) NNFC - iHP Workshop: introduction
B. tillack
German-Korean Workshop on nanotechnology
nnFC - IHp, Frankfurt (oder),
February 14-15, 2006, Germany
(141) Design and implementation of a QoS
Capable WLAN Modem for iEEE 802.11a
K. tittelbach-Helmrich, G. panic, D. Dietterle,
M. Krstic, J. Klatt, n. Fiebig, J. lehmann
Workshop Quality-of-Service over Wireless
lAns for Converged enterprise networks,
Berlin, May 24, Germany
(142) bias Conditions in Gamma Radiation
Assurance Tests of bipolar Technologies
for HEP Applications
M. ullan, S. Diez, F. Campabadal, M. lozano,
G. pellegrini, D. Knoll, B. Heinemann
2006 nuclear Science Symposium, Medical
Imaging Conference and 15 th International
Room temperature Semiconductor Detector
Workshop, San Diego,
october 29 - november 04, 2006, uSA
(143) Gamma Radiation Effects on Three
Different SiGe HbT Technologies
M. ullan, S. Diez, F. Campabadal, M. lozano,
A n n u A l R e p o R t 2 0 0 6
163

G. pellegrini, D. Knoll, B. Heinemann
RADeCS 2006, Athens,
September 27-29, 2006, Greece
(144) interaction of iron with Grown-in
Dislocations in p-type Silicon:
An EbiC / DLTS Study
o. Vyvenko, M. Kittler, W. Seifert
International Conference on extended Defects
in Semiconductors, eDS 2006, Halle,
September 17-22, 2006, Germany
(145) Transforming Protocol Specifications for
Wireless Sensor Networks into Efficient
Embedded System implementations
G. Wagenknecht, D. Dietterle, J.-p. ebert,
R. Kraemer
3 rd european Workshop on Wireless Sensor
networks (eWSn), Zurich,
February 13-15, 2006, Switzerland
(146) 77 GHz Automotive Radar Receiver Frontend
in SiGe:C biCMoS Technology
l. Wang, J. Borngräber, W. Winkler
eSSCIRC 2006, Montreux,
September 18-22, 2006, Switzerland
(147) A 0.7-1.4 GHz Variable band Low Noise
Amplifier for Multi-band Applications
l. Wang, W. Winkler, G. Wang, J. Borngräber
8 th International Conference on Solid-State
and Integrated-Circuit technology, Shanghai,
october 23-26, 2006, China
(148) An improved Highly-Linear Low-Power
Down-Conversion Micromixer for 77 GHz
Automotive Radar in SiGe Technology
l. Wang, R. Kraemer, J. Borngräber
Ieee Mtt-S International Microwave
Symposium, San Francisco,
June 11-16, 2006, uSA
(149) bAAD: bidirectional Arbitrated
Adaptive DFE
G. Wang, J.-p. ebert, R. Kraemer
164 A n n u A l R e p o R t 2 0 0 6
V o R T R Ä G E – P R E S E N T A T i o N S
2006 Ieee Sarnoff Symposium, princeton,
March 27-28, 2006, uSA
(150) Advanced Dielectric Thin Film Deposition
Techniques in Microelectronics: From
Research to Production
Ch. Wenger
5 th International Summerschool at IHp,
Frankfurt (oder),
August 28 - September 02, 2006, Germany
(151) High Quality Layered Pr 2 Ti 2 o 7 / Sio 2 MiM
Capacitor for Mixed-Signal Applications
Ch. Wenger, R. Sorge, t. Schroeder, A.u. Mane,
D. Knoll, J. Dabrowski, H.-J. Müssig
the 6 th topical Meeting on Silicon Monolithic
Integrated Circuits in RF Systems (SiRFIC)
2006, San Diego, January 18-20, 2006, uSA
(152) High-k Metal-insulator-Metal Capacitors
for Radio Frequency Mixed-Signal Application
Ch. Wenger, A.u. Mane, R. Sorge, G. Weidner,
t. Schroeder, J. Dabrowski, G. lippert,
p. Zaumseil, H.-J. Müssig
DpG Frühjahrstagung Dresden,
March 27-31, 2006, Germany
(153) Non-Linearity of High-k MiM Capacitors
Ch. Wenger, t. Schroeder, J. Dabrowski,
R. Sorge, H.-J. Müssig, S. pasko, Ch. lohe
14 th Workshop on Dielectrics in
Microelectronics (WoDIM), Catania,
June 26-28, 2006, Italy
(154) New Support System at iHP and Customer
Satisfaction Questionnaire
W. Wichmann
5 th Workshop High-performance SiGe BiCMoS
for Wireless and Broadband Communication,
Frankfurt (oder),
September 25-26, 2006, Germany
(155) An indoor Localization System based on
DTDoA for Different Wireless LAN
F. Winkler, e. Fischer, e. Grass, p. langendörfer

3 rd Workshop on positioning, navigation and
Communication – WpnC 2006, Hannover,
March 16, 2006, Germany
(156) Front-End MMiC for Low-Cost 24 GHz Radar
Systems
W. Winkler, J. Borngräber
International Radar Symposium (IRS 2006),
Krakow, May 22-26, 2006, poland
(157) Radar Circuits and Components
W. Winkler
36 th european Microwave Conference 2006,
Manchester, September 10-15, 2006, uK
(158) interconnect Technologies, Metallization,
Selected backend of Line (bEoL) Topics
D. Wolansky
5 th International Summerschool at IHp,
Frankfurt (oder),
August 28 - September 02, 2006, Germany
(159) Self-organized Pattern Formation of
biomolecules at Silicon Surfaces
A. Wolff, W. Fritzsche, M. Kittler, X. Yu,
M. Reiche, t. Wilhelm, M. Seibt, o. Voß
DnA-Based nanoscale Integration Symposium,
Jena, May 23-25, 2006, Germany
(160) Self-organized Pattern Formation of
biomolecules at Silicon Surfaces
A. Wolff, W. Fritzsche, M. Kittler, X. Yu,
M. Reiche, t. Wilhelm, M. Seibt, o. Voß
Summer School: Complex Materials:
Cooperative projects of the natural,
engineering and Biosciences; International
university Bremen,
June 24 - July 01, 2006, Germany
(161) Self-organized Pattern Formation of
biomolecules at Silicon Surfaces
A. Wolff, W. Fritzsche, M. Kittler, X. Yu,
M. Reiche, t. Wilhelm, M. Seibt, o. Voß
Symposium‚ DAnn-based nanoscale
Integration‘, Jena, May 18-22, 2006, Germany
V o R T R Ä G E – P R E S E N T A T i o N S
(162) P Segregation behavior in SiGe:C Epitaxy
Y. Yamamoto, K. Köpke, p. Zaumseil, B. tillack
ASM user Meeting, parsdorf,
September 28, 2006, Germany
(163) Phosphorus Segregation Control for SiGe:C
Epitaxy
Y. Yamamoto, K. Köpke, p. Zaumseil, B. tillack
3 rd International SiGe technology and Device
Meeting, IStDM 2006, princeton,
May 15-17, 2006, uSA
(164) Combined CL / EbiC / DLTS investigation of
a Regular Dislocation Network Formed by
Silicon Wafer Direct bonding
X. Yu, o. Vyvenko, M. Kittler, W. Seifert,
t. Mchedlidze, t. Arguirov, M. Reiche
International Conference on Beam Injection
Assessment of Microstructures in Semiconductors
(BIAMS 2006), St. petersburg,
June 11-15, 2006, Russia
(165) Enhancement of iR Emission from a
Dislocation Network in Si due to an
External bias Voltage
X. Yu, o.F. Vyvenko, M. Reiche, M. Kittler
e-MRS 2006 Spring Meeting, nice,
May 29 - June 02, 2006, France
(166) investigation of Dislocation Networks
Formed by Si Wafer Direct bonding
X. Yu, M. Kittler, t. Arguirov, W. Seifert,
M. Ratzke, M. Reiche
International Conference on extended Defects
in Semiconductors 2006 (eDS 2006), Halle,
September 17-22, 2006, Germany
(167) A 70 MHz – 4.1 GHz 5 th -order Elliptic gm-C
Low-Pass Filter in Complementary SiGe
Technology
l. Yuan, R. Krithivasan, W.-M.l. Kuo,
l. Xiangtao, J.D. Cressler, H. Gustat,
B. Heinemann
Ieee Bipolar / BiCMoS Circuits and technology
Meeting, BCtM 2006, Maastricht,
october 08-10, 2006, the netherlands
A n n u A l R e p o R t 2 0 0 6
165

(168) Qualification Status of iHP’s 0.25 µm
biCMoS Technologies
p. Zaumseil
5 th Workshop High-performance SiGe BiCMoS
for Wireless and Broadband Communication,
Frankfurt (oder),
September 25-26, 2006, Germany
(169) X-Ray Characterization of Dielectric Films
(an overview)
p. Zaumseil
5 th International Summerschool at IHp,
Frankfurt (oder),
August 28 - September 02, 2006, Germany
(170) X-Ray Characterization of Periodic Sub-nm
Surface Relief Gratings
p. Zaumseil, M. Birkholz, G. Weidner
Xtop 2006, Baden-Baden,
September 19-22, 2006, Germany
(171) optical Properties, Elasto-optical Effects,
and Critical-Point Parameters of biaxially
Stressed Si 1-y C y Alloys on Si (001)
St. Zollner, V. Vartanian, J.p. lui, p. Zaumseil,
H.-J. osten, A.A. Demkov, B-Y nguyen
2006 3 rd International SiGe technology and
Device Meeting, IStDM 2006, princeton,
May 15-17, 2006, uSA
166 A n n u A l R e p o R t 2 0 0 6
b E R i C H T E – R E P o R T S
Berichte
Reports
(1) Zum weiteren Vorgehen bei der
Zusammenarbeit mit biologie und Medizin
M. Birkholz
Strategiepapier, Frankfurt (oder), April 2006
(2) Scenario Definition and initial Threat
Analysis
A.J.D. Casaca, D. Westhoff, p. langendörfer,
K. piotrowski, S. peter
project ubiSec&Sens
(3) Ab initio investigation of Dielectrics for
Modern Microelectronics
J. Dabrowski, A. Fleszar, G. lupina, A.u. Mane
projekt: nIC hfo06, April 2006
(4) Feasibility Study Wireless Technologies
for NSR applications
D. Dietterle, J.-p. ebert, p. langendörfer,
G. panic, S. peter, K. piotrowski, J. Kersten,
K. Dombrowski
Final project Report for Airbus,
IHp GmbH, Frankfurt (oder), May 2006
(5) bASUMA – Projektzwischenbericht
J.-p. ebert, D. Dietterle, G. Wang,
A. J. Bakurudeen
2. Halbjahr 2005, IHp GmbH, Frankfurt (oder),
February 2006
(6) bASUMA – Projektzwischenbericht
J.-p. ebert, D. Dietterle, G. Wang,
A. J. Bakurudeen
1. Halbjahr 2006, IHp GmbH, Frankfurt (oder),
September 2006
(7) Contamination during High Temperature
Treatments in SiC Reactor Tubes
A. Fischer, V. Akhmetov, G. Kissinger,
M. Kittler
SIWeDS Fall Meeting, Cancun,
november 02-03, 2006, Mexico

(8) Future Silicon Wafers (Abschlussbericht)
G. Kissinger
projekt Future Silicon Wafers, Dezember 2006
(9) Future Silicon Wafers (Zwischenbericht)
G. Kissinger
projekt Future Silicon Wafers, Juli 2006
(10) Alternatives Silicium für Solarzellen
(ASiS): Einfluss von Verunreinigungen auf
die elektrische Wirkung von Kristalldefekten
M. Kittler, W. Seifert, t. Arguirov, G. Jia,
o.F. Vyvenko
Abschlussbericht BMu-projekt 0329846 H,
2006
(11) Zwischenbericht SobSi-Projekt
(Volkswagenstiftung)
M. Kittler, M. Reiche, M. Seibt,
W. Fritzsche et al.
Februar 2006
(12) DRAM Capacitors on TiN-Pr 2 o 3 /
Al 2 o 3 - TiN basis for DRAM Applications
G. lippert
Industry Report: IHp -Qimonda Feasibility
Study, Final Report, July 2006
(13) Pr 2 o 3 -Added Al 2 o 3 Dielectrics for Future
DRAM Technologies
G. lippert, H.-J. Müssig
Abschlussbericht zur Machbarkeitsstudie,
IHp-Infineon projekt, 01.03.2006
(14) Evaluation of Heteroepitaxial Si 1-x Ge x /
(Pr 2 o 3 ) 1-x (Y 2 o 3 ) x / Si(111) Systems as
Soi Materials
t. Schroeder
Industry Report: Appendix to the
IHp-SIltRonIC Feasibility study Burghausen,
06.02.06
b E R i C H T E – R E P o R T S
(15) Ge and Si Heteroepitaxy via bixbyte based
buffer oxides on the Si Technology
Platform
t. Schroeder
Industry Report of the Siltronic – IHp
technology project
(16) Monolithic integration of New Valuable
Semiconductors on the Si Technology
Platform
t. Schroeder, p. Storck
Industry Report of the Siltronic – IHp
technology project
(17) Final System Performance and Validation
Report
M. Spegel, p. Reinhardt, B. Cheetham, A. lunn,
F.-M. Krause, K. tittelbach-Helmrich
Deliverable D7.2 des WInDeCt projektes
(18) interim Report: Scientific Cooperation
between AiXTRoN and iHP
Ch. Wenger
project High-K (Aixtron), September 2006
(19) Specification of the Advanced Concealed
Data Aggregation
D. Westhoff, C. Castelluccia, S. peter,
p. langendörfer
project ubiSec&Sens
(20) Specification, implementation and Simulation
of Secure Distributed Data Storage
D. Westhoff, p. langendörfer, K. piotrowski,
A. poschmann
project ubiSec&Sens
A n n u A l R e p o R t 2 0 0 6
167

Monographien
Monographs
(1) Thin Film Analysis by X-Ray Scattering
M. Birkholz
with contributions by p. Fewster and C. Genzel,
Wiley-VCH, Weinberg, 356 pages, (2006)
(2) 2006 SiGe and Ge: Materials, Processing
and Devices Symposium
D. Harame, J. Cressler, B. tillack, G. Masini,
S. Koester, J. Boquet, K. Rim, M. Caymax,
A. Reznicek, S. Zaima ( eds.)
eCS transactions 3(7) (2006)
(3) The Silicon Age
M. Kittler, D. Yang (eds.)
proc. 2 nd Sino-German Symposium,
held 19-24 September 2005 in Cottbus,
Germany, Special issue:
physica Status Solidi (a), 203(4),
657-809 (2006)
(4) Wireless Network Security
S. Shen, C. lin, Y. Sun, J. pan, p. langendörfer,
Z. Cao .
Wireless Communications and Mobile
(Wiley) 6(3) (2006)
168 A n n u A l R e p o R t 2 0 0 6
M o N o G R A P H S – H A b i L i T A T i o N S / D i S S E R T A T i o N S
Habilitationen / Dissertationen
Habilitations / Dissertations
(1) Atomic Puzzle - Growth-Structure-Property
Relations in Thin Solid Films for Advanced
Technological Applications
M. Birkholz
Habilitation Btu Cottbus (2006)
(2) Development and Characterisation of a
Process Technology for a 0.25µm SiGe:C
RF-biCMoS embedded Flash Memory
A. Fox
Dissertation technische universität Kiel (2006)
(3) Request-driven GALS Technique for
Datapath Architectures
M. Krstic
Dissertation Btu Cottbus (2006)
(4) Praseodymium Silicate High-k Dielectrics
on Si(100)
G. lupina
Dissertation Btu Cottbus (2006)
(5) Key Management for Wireless Ad-Hoc
Networks
D. Sanchez
Dissertation Btu Cottbus (2006)

Diplomarbeiten / Masterarbeiten /
Bachelorarbeiten
Diploma Theses / Master Theses /
bachelor Theses
D i P L o M A T H E S E S / M A S T E R T H E S E S / b A C H E L o R T H E S E S
(1) Design und Entwicklung eines graphischen
Editors für Rapid Prototyping und Realisierung
kontext-sensitiver Dienste mit PLASMA
S. Adam
Masterarbeit Btu Cottbus (2006)
(2) Eine Datensicherungs- und Transportschicht
für drahtlose Sensornetze
M. Brzozowski
Masterarbeit Btu Cottbus (2006)
(3) Entwurf und implementation eines LDPC-
Kodierers / Dekodierers für ein Gbit-WLAN
M. ehrig
Diplomarbeit Humboldt-universität Berlin (2006)
(4) Simulation und Realisierung eines auf
differentiellen Laufzeiten basierenden
Systems zur Positionsbestimmung und
Anpassung an diverse Netzwerkstandards
e. Fischer
Diplomarbeit Humboldt-universität Berlin (2006)
(5) Automatische Verifizierung von
SPiCE-Modellen in Perl
t. Mausolf
Diplomarbeit FH Brandenburg (2006)
(6) Evaluation of Design Alternatives for
Flexible Elliptic Curve Hardware Accelerators
S. peter
Diplomarbeit Btu Cottbus (2006)
(7) Desing of a Power Saving Methodology for
Next Generation Wireless System-on-Chip
Design
K. Saeed
Master of Science KtH Stockholm (2006)
(8) Design of a Hardware Accelerator for
iEEE 802.15.3 MAC Protocol
H. Shah
Master of Science KtH Stockholm (2006)
(9) Dreidimensionale ortsbestimmung von
mobilen Funksensoren in schwierigen
Umgebungsbedingungen
S. Willenbacher
Masterarbeit Btu Cottbus (2006)
(10) Materialcharakterisierung von Solarzellen
aus multikristallinem Silicium
Y. Yeromenko
Diplomarbeit Btu Cottbus (2006)
(11) Femtosekunden-Laser-ionisations-Flugzeitmassensprektrometrie
für die Analyse
von Schichtsystemen
l. Zhu
Diplomarbeit Btu Cottbus (2006)
A n n u A l R e p o R t 2 0 0 6
169

Patente
Patents
(1) Vorrichtung und Verfahren zur
strukturierten immobilisierung von
Molekülen auf Halbleitersubstraten
M. Birkholz, J. Bauer, M. Kittler
De-patentanmeldung IHp.271.05,
am 02.03.06, AZ: 10 2006 010 495.1
(2) Protokollbeschleuniger für das iEEE
802.15.3 drahtlose Medienzugriffsprotokoll
D. Dietterle
De-patentanmeldung IHp.284.06,
am 14.09.06, AZ: 10 2006 043 779.9
(3) integrierter impuls-Generator mit
abstimmbarer impulsbreite
X. Fan
De-patentanmeldung IHp.293.06,
am 23.11.06, AZ: 10 2006 055 868.5
(4) Asynchrone Hüllschaltung für eine global
asynchrone, lokale synchrone (GALS)
Schaltung
e. Grass, M. Krstic
pCt-Anmeldung IHp.268.pCt, am 01.08.06,
AZ: pCt / ep2006 / 064898
(5) Leistungsverstärker mit Delta-Sigma-
Modulator mit hilfsweiser Rückkopplung
H. Gustat
De-patentanmeldung IHp.281.06,
am 21.11.06, AZ: 10 2006 055 577.5
(6) Sigma-Delta-Modulator mit variablem
Taktsignal
H. Gustat, p. ostrovskyy
De-patentanmeldung IHp.277.06,
am 17.11.06, AZ: 10 2006 054 776.4-42
170 A n n u A l R e p o R t 2 0 0 6
P A T E N T E – P A T E N T S
(7) Verfahren zum Kalibrieren von
Stromquellen
S. Halder, H. Gustat
De-patentanmeldung IHp.269.05,
am 06.06.06, AZ: 10 2006 027 165.3
(8) Halbleiterbauelement mit versetzungsbasiertem
vergrabenen Leitbahnsystem
M. Kittler, W. Seifert, X. Yu
De-patentanmeldung IHp.275.05,
am 13.02.06, AZ: 10 2006 007 611.7
(9) Versetzungsbasierte MiS-LED
M. Kittler, X. Yu, o. Vyvenko, t. Arguirov,
W. Seifert, M. Reiche
De-patentanmeldung IHp.283.06,
am 31.05.06, AZ: 10 2006 026 457.6
(10) Versetzungsbasierter Lichtemitter
M. Kittler, W. Seifert, t. Arguirov, M. Reiche
De-patentanmeldung IHp.265.05A,
am 16.02.06, AZ: 10 2006 008 025.4-33
(11) Versetzungsbasierter Lichtemitter
M. Kittler, W. Seifert, t. Arguirov, M. Reiche
pCt-patentanmeldung IHp.265.pCt,
am 03.05.06, AZ: pCt / ep2006 / 062030
(12) Komplementäre bipolar-Halbleitervorrichtung
D. Knoll, B. Heinemann, K.-e. ehwald
De-patentanmeldung IHp.294.06,
am 08.12.06, AZ: 10 2006 059 113.5
(13) Geschütztes Ausführen einer Datenverarbeitungsanwendung
eines Dienste-
anbieters für einen Nutzer durch eine
vertrauenswürdige Ausführungsumgebung
p. langendörfer, M. Maaser
De-patentanmeldung IHp.272.05,
am 26.04.06, AZ: 10 2006 020 093.4

(14) Verfahren und Vorrichtung zum berechnen
einer Polynom-Multiplikation, insbesondere
für die elliptische Kurven-Kryptographie
p. langendörfer, Z. Dyka, S. peter
pCt-patentanmeldung IHp.264.pCt,
am 06.03.06, AZ: pCt / ep2006 / 060494
(15) optischer Translations-Rotations-Sensor
o. Maye, M. Maaser, J. Schäffner
De-patentanmeldung IHp.287.06,
am 29.12.06, AZ: 10 2006 062 673.7
(16) MiM / MiS-Struktur mit Praseodymtitanat
oder Praseodymoxid als isolatormaterial
H.-J. Müssig, G. lippert, Ch. Wenger
uS-patentanmeldung
am 14.06.06, AZ: 11 / 454, 145
(17) Verfahren zur Reduktion eines Polynoms
in einem binären finiten Feld
S. peter, p. langendörfer
De-patentanmeldung IHp.276.05,
am 22.03.06, AZ: 10 2006 013 989.5
(18) integrierte Schaltung mit Strahlungsschutz
G. Schoof, R. Kraemer
De-patentanmeldung IHp.286.06,
am 23.11.06, AZ: 10 2006 055 867.7-34
P A T E N T E – P A T E N T S
(19) Verschlüsselungseinheit
F. Vater, S. peter, u. Jagdhold, p. langendörfer
De-patentanmeldung IHp.289.06,
am 22.12.06, AZ: 10 2006 062 649.4
(20) Method and Apparatus for Low-Complexity
and Fast Start-up Adaptive Equalization of
Multipath Channel Through Accurate
initialization
G. Wang
pCt-Anmeldung IHp.274.pCt, am 14.12.06,
AZ: pCt / ep2006 / 069711
(21) Verfahren und Vorrichtung geringer
Komplexität für eine adaptive Entzerrung
von Mehrwegkanälen
G. Wang
De-patentanmeldung IHp.274.05,
am 19.04.06, AZ: 10 2006 018 914.0
A n n u A l R e p o R t 2 0 0 6
171

172 A n n u A l R e p o R t 2 0 0 6
A N G E b o T E U N D L E i S T U N G E N – D E L i V E R A b L E S A N D S E R V i C E S
Deliverables and Services

A N G E b o T E U N D L E i S T U N G E N – D E L i V E R A b L E S A N D S E R V i C E S
Multiprojekt Wafer (MPW) und
Prototyping Service
Das IHP bietet seinen Forschungspartnern und Kunden
Zugriff auf seine leistungsfähigen 0,25-µm-SiGe-BiC-
MOS-Technologien.
Die Technologien sind insbesondere für Anwendungen im
oberen GHz-Bereich geeignet, so z.B. für die drahtlose und
Breitbandkommunikation oder Radar. Sie bieten integrierte
HBTs mit Grenzfrequenzen bis zu 220 GHz und integrierte
HF-LDMOS-Bauelemente mit Durchbruchspannungen bis
zu 33 V einschließlich komplementärer Bauelemente.
Verfügbar sind folgende vier Technologien:
SG25H1: Eine Hochleistungs-Technologie mit
npn-HBTs bis zu f T / f max = 180 / 220 GHz.
SG25H2: Eine komplementäre Hochleistungs-
Technologie mit npn-HBTs ähnlich SG25H1
und zusätzlichen pnp-HBTs mit
f T / f max = 90 / 120 GHz.
SG25H3: Eine Technologie mit mehreren npn-HBTs,
deren Parameter von einer hohen HF-Performance
(f T / f max = 110 / 180 GHz) zu größeren
Durchbruchspannungen bis zu 7 V reichen.
SGB25VD: Eine kostengünstige Technologie mit mehreren
npn-Transistoren mit Durchbruchspannungen
bis zu 7 V. Eine Besonderheit dieser Technologie
sind zusätzliche integrierte komplementäre
HF-LDMOS-Bauelemente mit
Durchbruchspannungen bis zu 33 V.
Ab 2008 bietet das IHP Zugriff auf seine 0,13-µm-
BiCMOS-Technologie als nächste Generation. Diese
Technologie wird integrierte HBTs mit Grenzfrequenzen
bis zu 300 GHz enthalten.
Es finden technologische Durchläufe nach einem festen,
unter www.ihp-microelectronics.com verfügbaren Zeitplan
statt.
Multiproject Wafer (MPW) and
Prototyping Service
IHp offers research partners and customers access to
its powerful 0.25 µm SiGe BiCMoS technologies.
the technologies are especially suited for applications
in the higher GHz bands (e.g. for wireless,
broadband, radar). they provide integrated HBts with
cut-off frequencies of up to 220 GHz and integrated
RF lDMoS devices with breakdown voltages of up to
33 V, including complementary devices.
The following four technologies are available:
SG25H1: A high-performance technology with
npn-HBts up to f t / f max = 180 / 220 GHz.
SG25H2: A complementary high-performance
technology with npn-HBts similar to
SG25H1 and additional pnp-HBts with
f t / f max = 90 / 120 GHz.
SG25H3: A technology with a set of npn-HBts
ranging from a high RF performance
(f t / f max = 110 GHz / 180 GHz) to higher
breakdown voltages up to 7 V.
SGB25VD: A cost-effective technology with a set of
npn-HBts up to a breakdown voltage of
7 V. A distinctive feature of this technology
is additional integrated complementary
RF lDMoS devices with breakdown
voltages up to 33 V.
From 2008 IHp will offer access to its next generation
0.13 µm BiCMoS technology. this technology will
include integrated HBts with cut-off frequencies of
up to 300 GHz.
the schedule for MpW & prototyping runs is located
at www.ihp-microelectronics.com.
A n n u A l R e p o R t 2 0 0 6
173

174 A n n u A l R e p o R t 2 0 0 6
A N G E b o T E U N D L E i S T U N G E N – D E L i V E R A b L E S A N D S E R V i C E S
Ein Cadence-basiertes Design-Kit für Mischsignale ist
verfügbar. Wiederverwendbare Schaltungsblöcke und
IPs des IHP für die drahtlose und Breitbandkommunikation
werden zur Unterstützung von Designs angeboten.
In den folgenden Tabellen sind die wesentlichen Parameter
der für MPW & Prototyping angebotenen Technologien
dargestellt:
1. High-Performance 0.25 µm SiGe biCMoS
(SG25H1)
Parameter npn1 npn2
bipolar Section
A e 0.21 x 0.84 µm 2 0.18 x 0.84 µm 2
peak f max 190 GHz 220 GHz
peak f t 190 GHz 180 GHz
BV Ce0 1.9 V 1.9 V
BV CBo 4.5 V 4.5 V
V A 40 V 40 V
β 200 200
A cadence-based mixed signal design kit is available.
For high frequency designs an analogue Design
Kit in ADS can be used. IHp’s reusable blocks and Ips
for wireless and broadband are offered to support
designs.
technical key-parameters of the technologies offered
for MpW & prototyping are:
2. Complementary High-Performance 0.25 µm
SiGe biCMoS (SG25H2)
Parameter npn pnp
bipolar Section
A e 0.21 x 0.84 µm 2
peak f max 170 GHz 120 GHz
peak f t 170 GHz 90 GHz
BV Ce0 1.9 V - 2.5 V
BV CBo 4.5 V - 4.0 V
V A 40 V 30 V
β 160 100
3. 0.25 µm SiGe biCMoS with a set of npn-HbTs, ranging from high RF performance to high breakdown
voltages (SG25H3)
Parameter High High Medium High
Performance1 Performance2 Voltage Voltage
bipolar Section
A e 0.22 x 0.84 µm 2 0.42 x 0.84 µm 2 0.22 x 2.24 µm 2 0.22 x 2.24 µm 2
peak f max 180 GHz 140 GHz 140 GHz 80 GHz
peak f t 110 GHz 120 GHz 45 GHz 30 GHz
BV Ce0 2.3 V 2.3 V 5 V > 7 V
BV CBo 6.0 V 6.0 V 15.5 V 21.0 V
V A 30 V 30 V 30 V 30 V
β 150 150 150 150

A N G E b o T E U N D L E i S T U N G E N – D E L i V E R A b L E S A N D S E R V i C E S
4. 0.25 µm SiGe biCMoS with High-Voltage Devices (SGb25VD)
bipolar Section
Parameter High Standard High
Performance Voltage
A e 0.42 x 0.84 µm 2
peak f max 95 GHz 90 GHz 70 GHz
peak f t 75 GHz 45 GHz 25 GHz
BV Ceo 2.4 V 4.0 V 7.0 V
BV CBo > 7 V > 15 V > 20 V
V A > 50 V > 80 V > 100 V
β 190 190 190
LDMoS Section
n-LDMoS p-LDMoS
n-LDMoS 23 n-LDMoS 13 n-LDMoS
i10****
p-LDMoS 8 p-LDMoS 12
BV DSS * 26 V 15 V 11.5 V -10 V -13.5 V
I Dsat ** 140 µA / µm 140 µA / µm 175 µA / µm 85 µA / µm 90 µA / µm
(V GS = 1.5 V) (V GS = 1.5 V) (V GS = 1.5 V) (V GS = -1.5 V) (V GS = -1.5 V)
I leakage < 15 pA / µm < 15 pA / µm < 15 pA / µm < 50 pA / µm < 50 pA / µm
(V DS = 20 V) (V DS = 10 V) (V DS = 8 V) (V DS = -8 V) (V DS = -8 V)
R ON 11 Ωmm 7 Ωmm 7.5 Ωmm 16 Ωmm 11.5 Ωmm
Peak f max *** 40 GHz 43 GHz 46 GHz 25 GHz 22 GHz
Peak f T *** 19 GHz 23 GHz 21 GHz 11 GHz 11 GHz
*:@100 pA / µm **:@V = 5 V ***:@V = 4 V ****: substrate isolated
DS DS
An addidional n-LDMOS with BV of 33 V is available.
DSS
A n n u A l R e p o R t 2 0 0 6
175

176 A n n u A l R e p o R t 2 0 0 6
A N G E b o T E U N D L E i S T U N G E N – D E L i V E R A b L E S A N D S E R V i C E S
CMoS and Passives of 0.25 µm Technologies
Design Kits
Parameter SG25H1 – H3 SGb25VD
CMoS Section
Core Supply Voltage 2.5 V
nMoS V th 0.6 V
I Dsat 540 µA / µm 570 µA / µm
I off 3 pA / µm
pMoS V th - 0.56 V - 0.51 V
I Dsat 230 µA / µm 290 µA / µm
I off 3 pA / µm
Passives
MIM Capacitor 1 fF / µm 2
n + poly Resistor 210 Ω /
p + poly Resistor 280 Ω / 310 Ω /
High poly Resistor 1600 Ω / 2000 Ω /
Varactor C max / C min 3
Inductor Q@2.4 GHz 12 (1 nH), 6 (15 nH)
I nductor Q@5.8 GHz 16 (1 nH), 10 (2 nH)
5. An Additional 0.13 µm BiCMOS With the Following Scheduled Parameters Will be Available From 2008
bipolar Section
Parameter
Die Design Kits unterstützen eine Cadence Mischsignal-
Plattform:
- Design Framework II (Cadence 5.0-5.1 / 6.1
vorgesehen ab 4. Quartal 2007)
- Verhaltens-Beschreibung (Verilog HDL)
- Logische Synthese & Optimierung (VHDL / HDL
Compiler, Design Compiler / Synopsys, Power
Compiler / Synopsys)
npn13P npn13V
A e 0.12 x 0.48 µm 2 0.12 x 0.48 µm 2
peak f max 300 GHz 120 GHz
peak f t 250 GHz 45 GHz
BV CBo 1.7 V 4 V
BV CBo 5.5 V 16 V
β 500 450
Design Kits
the design kits support a Cadence mixed signal platform:
- Design Framework II (Cadence 5.0-5.1 / 6.1
scheduled for Q4 2007)
- Behavioral Modeling (Verilog HDl)
- logic Synthesis & optimization
(VHDl / HDl Compiler, Design Compiler /
Synopsys, power Compiler / Synopsys)

A N G E b o T E U N D L E i S T U N G E N – D E L i V E R A b L E S A N D S E R V i C E S
- Test Generation / Synthetisierer / Test Compiler
(Synopsys)
- Simulation (RF: SpectreRF, Analog: SpectreS,
Verhaltens-Beschreibung / Digital: Leapfrog / NC-
Affirma / Verilog-XL / ModelSim)
- Platzieren & Verbinden (Silicon Ensemble & Preview)
- Layout (Virtuoso Editor-Cadence)
- Verifizierung (Diva and Assura: DRC / LVS / Extract /
Parasitic Extraction)
- ADS-Support über RFDE / RFIC mit dynamischem
Link zu Cadence ist verfügbar
- Ein eigenständiges ADS Kit einschließlich
Momentum Substrate Layer File wird unterstützt,
jedoch ohne Layout-Unterstützung
- Unterstützung von Analog Office und Tanner über
Partner
- ECL-Bibliothek für SGB25VD
- Strahlungsresistente CMOS-Bibliothek ist geplant
- β Design Kit für 0,13 µm BiCMOS ist ab
4. Quartal 2007 verfügbar
Verfügbare analoge und digitale Blöcke und Designs
für die drahtlose und Breitbandkommunikation
Zur Unterstützung von Designs bietet das IHP Schaltungsblöcke
und Schaltungen für Lösungen im Bereich
drahtlose und Breitbandkommunikation an:
- LC-VCO für 77-81 GHz mit Ausgangspuffer
- Komponenten für 60-GHz-Analog-Frontends
(LNA, Mischer, vollständig integrierte PLL)
- 60 nach 5 GHz Empfänger-Frontend mit vollständig
integrierter PLL
- 5 nach 60 GHz Sender-Frontend mit vollständig
integrierter PLL
- Mischer, VCOs, Prescaler, VCO-Prescaler für 24 GHz
- DAC-Komponenten für mittlere und hohe
Geschwindigkeiten bis zu 30 GSps
- UWB Transceiver-Komponenten wie Mischer-
Korrelator und Breitband-LNA
- Statische und dynamische Teilerschaltungen bis
zu 60 GHz
- 5-GHz Breitband-Modem (1 Gbps) für OFDM
- 8-11 GHz und 16-19 GHz Integer-N PLLs mit
integriertem VCO mit geringem Phasenrauschen
- test Generation / Synthesizer / test Compiler
(Synopsys)
- Simulation (RF: SpectreRF, Analog: SpectreS,
Behavioral / Digital: leapfrog / nC-Affirma /
Verilog-Xl / ModelSim)
- place & Route (Silicon ensemble & preview)
- layout (Virtuoso editor-Cadence)
- Verification (Diva and Assura: DRC / lVS / extract /
parasitic extraction)
- ADS-support via RFDe / RFIC dynamic link to
Cadence is available
- A standalone ADS Kit including Momentum
substrate layer file is supported, but without
layout support
- Support of Analog office, Catena, and tanner
via partners is available
- eCl library for SGB25VD
- Radiation hard CMoS library is planned
- β Design Kit for 0.13 µm BiCMoS will be available
from Q4 2007
Available Analog and Digital blocks and Designs
for Wireless and broadband Communications
to support designs, IHp offers a wide range of blocks
and designs for wireless & broadband solutions:
- 77-81 GHz lC-VCo with output buffer
- 60 GHz Analog Frontend Components
(lnA, Mixers, fully-integrated pll)
- 60 to 5 GHz RX-Frontend with fully-integrated
pll
- 5 to 60 GHz tX-Frontend with fully-integrated
pll
- 24 GHZ mixers, VCos, prescaler, VCo-prescaler
- DAC components for medium and high speed up
to 30 GSps
- uWB transceiver components such as mixer
correlator, broadband lnA
- Static and dynamic divider circuits for up
to 60 GHz
- 5 GHz broadband modem (1 Gbps) for oFDM
- 8-11 GHz and 16-19 GHz Integer-n plls with
integrated low phase-noise VCo
A n n u A l R e p o R t 2 0 0 6
177

178 A n n u A l R e p o R t 2 0 0 6
A N G E b o T E U N D L E i S T U N G E N – D E L i V E R A b L E S A N D S E R V i C E S
- I 2 C-Interface
- SPI-Interface
- SPW (Signal Processing Worksystem) und MATLAB-
Modelle für einen digitalen Basisband-Prozessor für
ein IEEE 802.11a / p-konformes Modem einschliess-
lich der Einheiten für Synchronisation und
Kanalschätzung
- Designs für Basisband-Verarbeitung (Viterbi
Decoder, FFT / IFFT Prozessor, CORDIC Prozessor)
- Synthetisierbares VHDL-Modell des kompletten
IEEE 802.11a OFDM Basisband- Prozessors einschließlich
der Synchronisation und Kanalschätzung
- Echtzeit-Implementierung des MAC-Layer für ein
IEEE 802.11a-kompatibles Modem für eingebettete
Anwendungen, bestehend aus einem auf MIPS- oder
ARM-Prozessoren laufenden C-Programm, sowie
einem speziellen Hardware-Beschleuniger
- Ein abstraktes SDL-Modell des MAC-Layer für ein
IEEE 802.11a- und HiperLAN / 2-kompatibles Modem
mit Testbenches für verschiedene Anwendungs-
Szenarien
- Ein abstraktes SDL-Modell für IEEE 802.15.3 und
IEEE 802.15.4
- 5-GHz-Link-Emulator und Entwicklungsumgebung
für WLAN
- TCP / IP-Prozessor einschließlich Hardware-
Beschleuniger für das Protokoll sowie symmetrische
und asymmetrische Verschlüsselung einschließlich
MD5
- Flexible ECC- und AES-Kryptoprozessoren
- Basisband-Modelle und Realisierungen für
Gigabit-WLAN
- Kontext-sensitive verteilte Middleware-Plattform
(PLASMA) für das drahtlose Internet
Transfer von Technologien und Technologie-Modulen
Das IHP bietet den Transfer seiner 0,25-µm-BiCMOS-
Technologien und Technologiemodule (HBT, LDMOS)
an. Die technologischen Parameter entsprechen weitgehend
den oben für MPW & Prototyping genannten.
- I 2 C-Interface
- SpI-Interface
- SpW (Signal processing Worksystem) and
MAtlAB models of a digital baseband
processor for an Ieee 802.11a / p compliant
modem, including the synchronization and
channel estimation units
- Designs for baseband processing (Viterbi decoder,
FFt / IFFt processor, CoRDIC processor)
- Synthesizable VHDl model of the complete
Ieee 802.11a oFDM baseband processor including
synchronization and channel estimation
- Realtime implementation of the MAC layer for an
Ieee 802.11a compliant modem for embedded
applications consisting of a C-program running
on MIpS or ARM processors, and a dedicated hardware
accelerator
- Abstract SDl model of MAC layer for
Ieee 802.11a and HiperlAn / 2 compliant
modem with testbenches for various deployment
scenarios
- Abstract SDl model for Ieee 802.15.3 and
Ieee 802.15.4
- 5 GHz link emulator and WlAn design /
debug kit
- tCp / Ip-processor including hardware
accelerators for protocol and symmetric
and asymmetric encryption including
MD5
- Flexible eCC and AeS cryptoprocessors
- Baseband-models and realisations for
Gigabit WlAn
- Context-sensitive distributed Middleware plat-
form (plASMA) for wireless internet applications
Transfer of Technologies and Technology Modules
IHp offers its 0.25 µm BiCMoS technologies and technology
modules (HBt-Modules, lDMoS-Modules) for
transfer. the technological parameters comply to a
large extent with the parameters described above for
MpW & prototyping.

A N G E b o T E U N D L E i S T U N G E N – D E L i V E R A b L E S A N D S E R V i C E S
Unterstützung bei Prozess-Modulen
Das IHP bietet Unterstützung bei der Realisierung spezieller
Prozess-Module für Forschung und Entwicklung
und für Prototyping bei geringen Volumina für Standard-Prozess-Module
und Prozess-Schritte.
Verfügbar sind u.a. folgende Prozess-Module:
- Standard-Prozesse (Implantation, Ätzen, CMP &
Abscheidung von Schichtstapeln wie thermisches
SiO 2 , PSG, Si 3 N 4 , Al, TiN, W)
- Epitaxie (Si, Si:C, SiGe, SiGe:C)
- Optische Lithographie (i-Linie und 248 nm bis
hinab zu 100 nm Strukturgröße)
- Verkürzte Prozessabläufe.
Fehleranalyse und Diagnostik
Das IHP bietet Unterstützung bei der Ausbeuteerhöhung
durch Fehleranalyse mit modernen Ausrüstungen
wie z.B. AES, AFM, FIB, LST, REM, SIMS, STM und
TEM.
Process Module Support
IHp offers support for advanced process
modules for research and development
purposes and small volume prototyping.
process modules available include:
- Standard processes (implantation, etching,
CMp & deposition of layer stacks such
as thermal Sio 2 , pSG, Si 3 n 4 , Al, tin, W)
- epitaxy (Si, Si:C, SiGe, SiGe:C)
- optical lithography (i-line and 248 nm down
to 100 nm structure size)
- Short-flow processing.
Failure Mode Analysis and Diagnostics
IHp offers support for yield enhancement through
failure mode analysis with state-of-the-art equipment,
including AeS, AFM, FIB, lSt, SeM, SIMS, StM
and teM.
Für weitere Informationen wenden Sie sich bitte an: For more information please contact:
Dr. Wolfgang Kissinger Dr. René Scholz
(General contact) (MPW & Prototyping contact)
IHP IHP
Im Technologiepark 25 Im Technologiepark 25
15236 Frankfurt (Oder), Germany 15236 Frankfurt (Oder), Germany
Email: kissinger@ihp-microelectronics.com Email : scholz@ihp-microelectronics.com
Tel: +49 335 56 25 410 Tel : +49 335 56 25 647
Fax: +49 335 56 25 222 Fax +49 335 56 25 327
A n n u A l R e p o R t 2 0 0 6
179

Wegbeschreibung zum IHP
180 A n n u A l R e p o R t 2 0 0 6
W E G b E S C H R E i b U N G Z U M i H P – D i R E C T i o N S T o i H P
per Flugzeug
- Vom Flughafen Berlin-Tegel mit der Buslinie X9 bis
Bahnhof Berlin-Zoologischer Garten (19 Minuten);
dann mit dem RegionalExpress RE 1 bis Frankfurt
(Oder) Hauptbahnhof (ca. 1 Stunde 20 Minuten).
- Vom Flughafen Berlin-Schönefeld mit dem Airport-
Express oder der S-Bahnlinie S 9 bis Bahnhof Berlin-Ostbahnhof
(19 bzw. 32 Minuten); dann mit dem
RegionalExpress RE 1 bis Frankfurt (Oder) Hauptbahnhof
(ca. 1 Stunde).
- Vom Flughafen Berlin-Tempelhof mit der U-Bahnlinie
U 6 Richtung Alt-Tegel bis zur Haltestelle Friedrichstraße
(11 Minuten); umsteigen in den Regional-
Express RE 1 bis Frankfurt (Oder) Hauptbahnhof
(ca. 1 Stunde 15 Minuten).
per Bahn
- Von den Berliner Bahnhöfen Zoologischer Garten,
Hauptbahnhof, Friedrichstraße, Alexanderplatz
oder Ostbahnhof mit dem RegionalExpress RE 1 bis
Frankfurt ( Oder) Hauptbahnhof.
per Auto
- Über den Berliner Ring auf die Autobahn A 12 in Richtung
Frankfurt (Oder) / Warschau; Abfahrt Frankfurt
(Oder)-West, an der Ampel links in Richtung Beeskow
und dem Wegweiser „Technologiepark Ostbrandenburg“
folgen.
per Straßenbahn in Frankfurt (Oder)
- Ab Frankfurt (Oder) Hauptbahnhof mit der Linie 3
oder 4 in Richtung Markendorf Ort bis Haltestelle
Technologiepark (14 Minuten).
Directions to iHP
by plane
- From Berlin-tegel Airport take the bus X9 to the
railway station Berlin-Zoologischer Garten (19 minutes);
then take the Regionalexpress Re 1 to Frankfurt
(oder) Hauptbahnhof (appr. 1 hour 20 minutes).
- From Berlin-Schönefeld Airport take the Airport-
express or the S-Bahn line S 9 to the railway
station Berlin ostbahnhof (19 resp. 32 minutes);
then take the Regionalexpress Re 1 to
Frankfurt (oder) Hauptbahnhof (appr. 1 hour).
- From Berlin-tempelhof Airport take the subway
line u 6 in the direction Alt-tegel to the station
Friedrichstraße (11 minutes); there transfer to
the Regionalexpress Re 1 to Frankfurt (oder)
Hauptbahnhof (appr. 1 hour 15 minutes).
by train
- take the train Regionalexpress Re 1 from the
Berlin railway stations Zoologischer Garten,
Hauptbahnhof, Friedrichstraße, Alexanderplatz
or ostbahnhof to Frankfurt (oder) Hauptbahnhof.
by car
- take the highway A 12 from Berlin in the direction
Frankfurt (oder) / Warschau (Warsaw); take
exit Frankfurt (oder)-West, at the traffic lights
turn left in the direction Beeskow and follow
the signs to “technologiepark ostbrandenburg”.
by tram in Frankfurt (oder)
- take the tram 3 or 4 from railway station Frankfurt
(oder) Hauptbahnhof in the direction Markendorf
ort to technologiepark (14 minutes).

Herausgeber / Publisher
IHp GmbH – Innovations for High performance Microelectronics
/ Institut für innovative Mikroelektronik
Postadresse / Postbox
postfach 1466 / postbox 1466
15204 Frankfurt (oder)
Deutschland / Germany
Besucheradresse / Address for Visitors
Im technologiepark 25
15236 Frankfurt (oder)
Deutschland / Germany
Telefon / Fon +49 335 56 25 0
Telefax / Fax +49 336 56 25 300
e-Mail ihp@ihp-microelectronics.com
Internet www.ihp-microelectronics.com
i M P R E S S U M – i M P R i N T
Redaktion / Editors
Dr. Wolfgang Kissinger / Heidrun Förster
Gesamtherstellung / Production in design and layout
GIRAFFe Werbeagentur
leipziger Straße 187
15232 Frankfurt (oder)
Telefon / Fon +49 335 50 46 46
Telefax / Fax +49 336 50 46 45
e-Mail kontakt@giraffe.de
Internet www.giraffe.de
Bildnachweise / Photocredits
IHp, Winfried Mausolf, Rainer Weißflog
A n n u A l R e p o R t 2 0 0 6
181

182 A n n u A l R e p o R t 2 0 0 6
N o T i Z E N – N o T E S

N o T i Z E N – N o T E S
A n n u A l R e p o R t 2 0 0 6
183

184 A n n u A l R e p o R t 2 0 0 6
N o T i Z E N – N o T E S