Annual Report 2005 (PDF 4.3 MB) - IHP Microelectronics

Annual Report 2005 

JAHRESBERICHT 2005 | INSTITUT FÜR INNOVATIVE MIKROELEKTRONIK

Annual Report 2005 

JAHRESBERICHT 2005 | INSTITUT FÜR INNOVATIVE MIKROELEKTRONIK

Vorwort Foreword 

Im vergangenen Jahr ist das IHP bei der erfolgreichen 

Realisierung seiner Forschungsprojekte, der Erweiterung 

der Kooperationen sowie bei der Modernisierung 

der Infrastruktur deutlich vorangekommen. 

Die wissenschaftlichen Leistungen des Institutes fanden 

national und international großes Interesse, so 

zum Beispiel die Ergebnisse zu 60-GHz-Komponenten 

(vorgestellt auf der ISSCC), zu ultraschnellen Wandlern 

(BCTM) oder zu siliziumbasierten Lichtemittern (IEDM). 

Deutlich nahm die Nutzung des Multi-Projekt-Wafer & 

Prototyping Services durch Universitäten, andere Forschungseinrichtungen 

sowie Industrieunternehmen zu. 

Die Forschungsarbeiten zu neuen Hoch-k-Materialien 

waren Basis für neue, auf konkrete Anwendungen zielende 

Projekte. 

Die Kooperationsbeziehungen des IHP haben sich in Umfang 

und Qualität spürbar weiterentwickelt. Sie spiegeln 

sich auch in den im vergangenen Jahr deutlich gesteigerten 

Drittmitteleinnahmen wider. 

Die Zusammenarbeit mit Forschungseinrichtungen, 

Universitäten und Industrieunternehmen in Berlin und 

Brandenburg ist für uns ebenso wichtig wie die Pflege 

unserer zahlreichen internationalen Forschungskooperationen. 

Daher sind wir aktiv dabei, unsere Kompetenzen 

auf dem Gebiet der drahtlosen Kommunika- 

tionstechnologien noch intensiver für Kooperationen 

mit den in Berlin und Brandenburg stark vertretenen 

Branchen wie Sensortechnik, Automotive, Luft- und 

Raumfahrt sowie Lebenswissenschaften einzusetzen. 

Im Rahmen der Verfahren zur Qualitätssicherung in der 

Leibniz-Gemeinschaft fand eine fachliche Begutachtung 

der Arbeit des IHP durch den Wissenschaftlichen Beirat 

statt. Neben einer positiven Einschätzung der Ziele und 

Leistungen des Institutes erhielten wir dabei auch wertvolle 

Hinweise für neue strategische Forschungsrichtungen. 

Die Forschungsergebnisse des vergangenen Jahres 

konnten nur durch die engagierte und kreative Arbeit 

unserer Belegschaft und die starke Unterstützung 

durch die Brandenburgische Landesregierung und die 

Bundesregierung erreicht werden, wofür wir an dieser 

Stelle danken möchten. 

Wolfgang Mehr 

Wiss.-Techn. Geschäftsführer 

2 

Manfred Stöcker 

Adm. Geschäftsführer 

J A H R E S B E R I C H T 2 0 0 5 | I H P A N N U A L R E P O R T 

During the last year, IHP 

made a significant progress 

in the successful 

realization of its research 

projects, in the extension 

of its cooperation as well 

as in the modernization 

of the infrastructure. 

The scientific achievements 

of the institute at- 

Prof. Dr. Wolfgang Mehr tracted large national and 

international interest, for example, the results of the 

60 GHz components (introduced at the ISSCC), of ultra 

fast converters (BTCM) or of the silicon-based light 

emitters (IEDM). The utilization of the Multi-Project 

Wafer & Prototyping Service by universities, other research 

institutions and industrial enterprises increased 

considerably. The research work of new high-k 

materials was the basis for new projects, focused on 

specific applications. 

The cooperation relationships of the IHP further developed 

noticeably in circumference and quality. This is 

reflected clearly also in the increased third-party fundings 

during the last year. 

The collaboration with research institutes, universities 

and industrial enterprises is just as important for 

us as our numerous international research cooperation. 

Therefore, we apply actively our competencies 

in wireless communication technologies in cooperation 

with firms from branches such as sensor technique, 

automotive, aerospace industry as well as life 

sciences which are strongly represented in Berlin and 

Brandenburg. 

In the framework of procedures to secure the quality 

in the Leibniz Association, an examination of the 

work at the IHP by the Scientific Advisory Board took 

place. Besides a positive evaluation of the goals and 

achievements of the institute, we also got valuable 

advice for new strategic areas of research. 

The research results of the past year are attributable 

to the dedicated and creative work of our staff and the 

strong support from the regional government of Brandenburg 

and the federal government, which we would 

like to pay our particular thanks.

Vorwort/Foreword 

Aufsichtsrat/Supervisory Board 

Wissenschaftlicher Beirat/Scientific Advisory Board 

Das IHP auf einen Blick/IHP in a Nutshell 

Das Jahr 2005/Update 2005 

Angebote und Leistungen/Deliverables and Services 

Forschung des IHP/IHP’s Research 

Ausgewählte Projekte/Selected Projects 

Drahtloses Internet/Wireless Internet 

Technologieplattform/Technology Platform 

Materialien für die Mikroelektronik/Materials 

for Microelectronics 

Gemeinsames Labor IHP/BTU – IHP/BTU Joint Lab 

Konferenzen und Workshops/Conferences and 

Workshops 

Zusammenarbeit und Partner/Collaboration and 

Partners 

Gastwissenschaftler und Seminare/Guest Scientists 

and Seminars 

Publikationen/Publications 

Nachdrucke ausgewählter Publikationen/ 

Reprints of Selected Publications 

Erschienene Publikationen/ 

Published Papers 

Eingeladene Vorträge/Invited Presentations 

Vorträge/Presentations 

Berichte/Reports 

Monografien/Monographs 

Patente/Patents 

Wegbeschreibung zum IHP/ Directions to IHP 

Impressum / Imprint 

Inhaltsverzeichnis 

Seite 

2 

4 

5 

6 

8 

16 

24 

28 

62 

66 

70 

74 

78 

158 

159 

29 

41 

52 

79 

130 

143 

145 

153 

155 

156 

Contents 

Page 

J A H R E S B E R I C H T 2 0 0 5 | I H P A N N U A L R E P O R T 3

Aufsichtsrat Supervisory Board 

Aufsichtsrat 

Konstanze Pistor 

Vorsitzende 

Ministerium für Wissenschaft, Forschung und Kultur 

Land Brandenburg 

MinDirig Dr. Wolf-Dieter Lukas 

Stellvertretender Vorsitzender (bis 07.06.2005) 

Bundesministerium für Bildung und Forschung 

MinR Thomas Sondermann 

Stellvertretender Vorsitzender (ab 08.06.2005) 

Bundesministerium für Bildung und Forschung 

Dr.-Ing. Peter Draheim 

Silicon Manufacturing Itzehoe SMI GmbH 

(ab 08.02.2005) 

Christian Funke 

Stellvertretendes Mitglied für die Person der Vorsitzenden 

(ab 02.08.2005) 

Ministerium für Wissenschaft, Forschung und Kultur 


Prof. Dr. Helmut Gabriel 

Freie Universität Berlin 

Dr. Eckhard Grass 

IHP GmbH (ab 14.12.2005) 

Norbert Quinkert 

Motorola GmbH, Taunusstein (ab 08.02.2005) 

Dr. Harald Richter 

IHP GmbH 

Prof. Dr. Ernst Sigmund 

Brandenburgische Technische Universität Cottbus 

Dr. Wolfgang Winkler 

IHP GmbH (bis 14.12.2005) 

MinR Gerhard Wittmer 

Ministerium der Finanzen 


4 

Supervisory Board 

Konstanze Pistor 

Chair 

Ministry of Science, Research and Culture 

State of Brandenburg 

Dr. Wolf-Dieter Lukas 

Deputy Chair (until June 7, 2005) 

Federal Ministry of Education and Research 

MinR Thomas Sondermann 

Deputy Chair (since June 8, 2005) 

Federal Ministry of Education and Research 

Dr.-Ing. Peter Draheim 

Silicon Manufacturing Itzehoe SMI GmbH 

(since February 8, 2005) 

Christian Funke 

Deputy member of the person of the chair 

(since August 2, 2005) 

Ministry of Science, Research and Culture 


Prof. Helmut Gabriel 

Freie Universität Berlin 

Dr. Eckhard Grass 

IHP GmbH (since December 14, 2005) 

Norbert Quinkert 

Motorola GmbH, Taunusstein (since February 2, 2005) 

Dr. Harald Richter 


Prof. Ernst Sigmund 

Technical University of Brandenburg, Cottbus 

Dr. Wolfgang Winkler 

IHP GmbH (until December 14, 2005) 

Gerhard Wittmer 

Ministry of Finance 


J A H R E S B E R I C H T 2 0 0 5 | I H P A N N U A L R E P O R T

Wissenschaftlicher Beirat 

Prof. Dr. Hermann G. Grimmeiss 

Vorsitzender 

Department of Solid State Physics 

Lund University, Schweden 

Dr. Jürgen Arndt 

Stellvertretender Vorsitzender 

ATMEL Germany GmbH, Heilbronn 

Prof. Dr. Ignaz Eisele 

Fakultät für Elektrotechnik und Informationstechnik 

Universität der Bundeswehr München 

Prof. Dr. Christian Enz 

CSEM SA, Neuchatel, Schweiz 

Prof. Dr. Ulrich Rohde 

Synergy Microwave Corporation, USA 

Dr. Josef Winnerl 

Infineon Technologies AG, München 

Prof. Dr. Günter Zimmer 

Fraunhofer IMS, Duisburg 

Leitung 

Prof. Dr. Wolfgang Mehr 

Wissenschaftlich-Technischer Geschäftsführer 


Administrativer Geschäftsführer 

Wissenschaftlicher 

Beirat 

Scientific Advisory Board 

Prof. Hermann G. Grimmeiss 

Chair 

Department of Solid State Physics 

Lund University, Sweden 

Dr. Jürgen Arndt 

Deputy 

ATMEL Germany GmbH, Heilbronn 

Prof. Ignaz Eisele 

Faculty of Electrical Engineering and Information 

Technology, University of the Bundeswehr, Munich 

Prof. Christian Enz 

CSEM SA, Neuchatel, Switzerland 

Prof. Ulrich Rohde 

Synergy Microwave Corporation, USA 

Dr. Josef Winnerl 

Infineon Technologies AG, Munich 

Prof. Günter Zimmer 

Fraunhofer IMS, Duisburg 

Management 

Prof. Wolfgang Mehr 

Director 


Administrative Director 

Scientific Advisory 

Board 


Das IHP auf einen Blick 

IHP in a Nutshell

Das Institut 

- Gegründet 1983; 1991 Neugründung aus einem 

früheren Akademieinstitut mit langjähriger Erfahrung 

in der Mikroelektronik auf Silizium-Basis 

- ca. 200 Mitarbeiter aus 16 Ländern 

- Mitglied der Leibniz-Gemeinschaft 

Aufgabe 

- Wirkung als Europäisches Forschungs- und Innovationszentrum 

für drahtlose Kommunikationstechnologien 

- Stärkung der Wettbewerbsfähigkeit der deutschen 

und europäischen Mikroelektronik- und Kommunikationsforschung 

- Erhöhung der Attraktivität der Region als Hochtechnologiestandort 

Strategie 

- Konzentration auf drahtlose und Breitbandkommunikation 

- Erarbeitung zukunftsorientierter Technologien, 

Schaltkreise und Systeme bis zu Prototypen 

- Wertschöpfung durch Innovation 

Infrastruktur 

- Vollständige Innovations-Kette vom Material bis zu 

Systemen, einschließlich Pilotlinie mit 0,25 (0,13) µm- 

BiCMOS-Technologien 

Kompetenzen 

- Systeme für die drahtlose Kommunikation 

- HF-Schaltkreisentwurf 

- Erweiterung von Silizium-CMOS-Technologien für 

neue Funktionen 

- Materialien für die Mikroelektronik-Technologie 

IHP auf einen Blick IHP in a Nutshell 

The Institute 

- Founded in 1983; re-established in 1991 as a successor 

institution to the former institute of the 

East German Academy with extensive experience 

in silicon microelectronics 

- 200 employees from 16 countries 

- Member of the Leibniz Association 

Mission 

- To act as a European Research- and Innovation 

Center for wireless communication technologies 

- To strengthen the competitive position of the German 

and European microelectronic and communication 

research 

- To enhance the attractiveness of the region as a 

location for high technology 

Strategy 

- To focus on solutions for wireless and broadband 

communications 

- Development of forward-looking technologies, circuits 

and systems up to prototypes 

- To create value through innovation 

Facilities 

- Complete innovation chain from materials to systems, 

including a pilot line with 0.25 (0.13) µm BiCMOS 

technologies 

Competencies 

- Systems for wireless communication 

- RF circuit design 

- Extension of silicon CMOS technologies for new 

functionalities 

- Materials for microelectronic technology 


Das Jahr 2005 

Update 2005

Über die wissenschaftlichen Arbeiten hinaus gab es 

im Jahr 2005 zahlreiche Initiativen zur weiteren Vernetzung 

der Forschung des IHP, zur Vorbereitung neuer 

Forschungsprojekte und zur Nutzung erzielter Ergebnisse. 

Wissenschaftler des IHP waren aktiv als Initiatoren, Organisatoren 

oder Vortragende wissenschaftlicher Konferenzen 

und Workshops. Beispiele dafür sind die internationale 

Konferenz GADEST, ein Fachsymposium 

im Rahmen der 69. Jahrestagung der DPG, ein Symposium 

an der BTU Cottbus gemeinsam mit chinesischen 

Partnern sowie internationale Workshops in Frankfurt 

(Oder) und Moskau. Mit dem National NanoFab Center 

Korea wurde ein Memorandum of Understanding für 

eine Forschungskooperation unterzeichnet. 

Die Kooperation des IHP mit regionalen Hoch- und 

Fachhochschulen entwickelte sich deutlich weiter. Die 

Grundlagenforschung im gemeinsamen Labor mit der 

BTU Cottbus führte zu international beachteten Ergebnissen. 

In Würdigung seiner Leistungen wurde Herr Dr. 

Martin Kittler, der auch das gemeinsame Labor leitet, 

zum außerplanmäßigen Professor der BTU ernannt. Für 

Studenten des Studienganges Physikalische Technik 

der TFH Wildau wurde am IHP ein Praktikum mit Vorlesungen 

und praktischen Übungen durchgeführt. Die 

bisherige wissenschaftliche Zusammenarbeit mit der 

TU Berlin wurde 2005 in einem Kooperationsvertrag 

verankert. 

Die erweiterte Zusammenarbeit des IHP mit der Industrie 

dokumentiert sich u.a. in Verbundprojekten und zahlreichen 

bilateralen Verträgen. Eine Vereinbarung zur Forschungskooperation 

wurde zwischen der AIXTRON AG 

und dem IHP unterzeichnet. Im Juni wurde eine Epitaxie- 

Anlage der Centrotherm GmbH im Reinraum des IHP in 

Betrieb genommen, auf der gemeinsam mit dem Institut 

hochproduktive Abscheideprozesse entwickelt werden. 

Die Arbeit der 2005 eröffneten Transferstelle der 

Zukunftsagentur Brandenburg für das IHP und die Europa-Universität 

Viadrina zielt besonders auf eine Verstärkung 

der Zusammenarbeit mit mittelständischen 

Firmen in Berlin und Brandenburg. 

Die Nutzung der Forschungsergebnisse des IHP war 

2005 Gegenstand mehrerer Veranstaltungen. So 

fand im Februar ein Workshop zum Thema „Verwertung 

von Schutzrechten – Vertragsstrategien zu Forschungskooperationen 

mit der Industrie“ statt. Im 

November wurde am IHP zum Thema „Firmengründun- 


Das Jahr 2005 Update 2005 

Beyond the scientific work of the IHP, the year 2005 

produced numerous initiatives for the further networking 

of the institute’s research, for the preparation of 

new research projects and for the utilization of attained 

results. 

The scientists of the institute actively participated in 

many international conferences and workshops as initiators, 

organizers or lecturers. Examples are the international 

conference GADEST, a specialized symposium 

in the framework of the 69th annual conference 

of the German Physical Society, a symposium at the 

BTU Cottbus together with Chinese partners and international 

workshops in Frankfurt (Oder) and Moscow. A 

Memorandum of Understanding for a research cooperation 

was signed together with the National NanoFab 

Center Korea. 

The IHP cooperation with regional universities and universities 

of applied sciences was enhanced distinctly. 

The basic research of the joint laboratory with BTU 

Cottbus led to internationally recognized results. In appreciation 

of his achievements, Dr. Martin Kittler, who 

is also the head of the joint laboratory, was appointed 

as associate professor of the BTU. A training including 

lectures and practical exercises were offered by the 

IHP for students studying Physical Technology at the 

TFH Wildau. The already existing scientific cooperation 

with the TU Berlin was anchored with a cooperation 

contract in 2005. 

The expanded cooperation of the IHP with industries 

expresses itself, among other things, in cooperation 

projects and numerous bilateral contracts. An agreement 

about a research cooperation was signed between 

the AIXTRON AG and the IHP. In June an epitaxy-system 

of the centrotherm GmbH was put into 

operation in the cleanroom of the IHP, on which, jointly 

with the institute, high productive deposition processes 

will be developed. The work of the Brandenburg 

Economic Development Board (ZAB) transfer position 

for the European University Viadrina and the IHP, founded 

in 2005, focuses especially on a stronger cooperation 

of the IHP with medium-sized firms in Berlin and 

Brandenburg. 

The utilization of IHP`s research results was objective 

in several events in 2005. For instance, a workshop 

with the theme “Making use of property rightscontract 

strategies for research cooperation with 

the industry” took place in February. In November, 

9


gen“ ein Science2Market-Tag gemeinsam mit LeibnizX, 

der Europa-Universität Viadrina und der BTU Cottbus 

durchgeführt. Ein Forscherteam des IHP wurde mit seiner 

Gründungsidee „Silicon Radar“ in der ersten Stufe 

des Businessplan-Wettbewerbs Berlin-Brandenburg 

mit dem ersten Preis ausgezeichnet. 

Wissenschaftliche Ergebnisse 

10 

Drahtloses Internet: Systeme und Anwendungen 

Die Arbeiten auf diesem sehr dynamischen Forschungsgebiet 

erfolgten unter starker Beteiligung des IHP an 

nationalen und europäischen Verbundprojekten. Die Ergebnisse 

fanden eine hohe internationale Beachtung. 

Auf besonderes Interesse stießen dabei die erreichten 

Lösungen zu 60-GHz-Transceivern und schnellen A/D- 

bzw. D/A-Wandlern. 

Beispiele für Ergebnisse im Jahr 2005 sind: 

1. Integrierte Lösungen für Systeme zur drahtlosen 

Kommunikation mit sehr hohen Datenraten. 

Weitere Schaltungen zur 5-GHz-Technik (IEEE 

802.11a) wurden fertiggestellt. Zusätzlich wurden 

Schaltungen für die Car2car-Kommunikation bei 

5,9 GHz entworfen. 

Die Transceiver-Komponenten für 60 GHz wurden 

fertiggestellt und optimiert. Zwei Versionen integrierter 

60-GHz-Receiver und Transmitter (mit und 

ohne integrierte Antenne) wurden entworfen. 

2. Radarsensoren bei 24 GHz und bei 77 GHz. 

Verschiedene Mischer und VCO-Versionen bei 24 GHz 

wurden nach Lösung technischer Probleme im Zusammenhang 

mit der Flip-Chip-Technik erfolgreich 

präpariert. Weitere Entwicklungen auf der Basis 

von aktiven und passiven Mischern wurden fertiggestellt 

und ausgewertet. 

Die 77-GHz-Komponenten für das FMCW-Radar wurden 

weiter optimiert und vermessen. Erste Integrationsschritte 

werden derzeit für das Tape-Out vorbereitet 

(siehe auch Projekt KOKON). 

3. Schnelle A/D- und D/A-Wandler. 

In diesem 2004 begonnenen Projekt konnten bereits 

internationale Spitzenergebnisse erreicht 

werden. So wurde ein Track-and-Hold (THC)-Modul 

entwickelt, das bei 10 GSps eine Auflösung von 


a Science2Market-day at the IHP with the topic “firm 

foundations” was jointly organized with LeibnizX, the 

European University Viadrina and the BTU Cottbus. A 

research team of the IHP won the first prize with its 

foundation idea “Silicon Radar” in the first round of the 

business plan competition Berlin-Brandenburg. 

Scientific Results 

Wireless Internet: Systems and Applications 

The work of this very dynamic research area took 

place under strong participation of the IHP in National 

and European cooperation projects. The results received 

high international recognition, especially the attained 

solutions for the 60 GHz transceivers and fast 

A/D- and D/A-converters. 

Examples of results in 2005 were: 

1. Integrated solutions for systems of wireless communication 

with high data rates. 

Further circuits for 5 GHz technology (IEEE 

802.11a) were completed. In addition to that, circuits 

for the Car2car-Communication at 5.9 GHz 

were designed. 

The transceiver components for 60 GHz were completed 

and optimized. Two versions of integrated 

60 GHz receivers and transmitters (with and without 

an integrated antenna) were designed. 

2. Radar sensors at 24 GHz and at 77 GHz. 

Several mixers and VCO-Versions at 24 GHz were 

prepared successfully after having solved technical 

problems in connection with the flip chip technology. 

Further developments on the basis of active 

and passive mixers were completed and analyzed. 

The 77 GHz components for the FMCW radar were 

further optimized and measured. First integration 

steps are in preparation for the tape-out (also see 

KOKON project). 

3. Fast A/D- and D/A-Converter. 

In this project, initialized in 2004, international first 

rate results were attained. For instance, a Trackand-Hold 

(THC)-Module was developed, which at 

10 GSps reaches a resolution of 8 Bit. For this de-

echten 8 Bit erreicht. Für diese Entwicklung wurden 

neueste Hochleistungs-Technologien des IHP 

eingesetzt. 

4. Integriertes Wireless-Bus-System für medizinische 

Anwendungen im Rahmen des Projektes BASUMA. 

Die erforderliche Knotenarchitektur wurde realisiert 

und erfolgreich getestet. Das generische, ereignisgesteuerte 

Betriebssystem REFLEX wurde 

portiert und zusammen mit einer innovativen SDL- 

Laufzeitumgebung integriert. Dadurch werden die 

Entwicklungszeiten für MAC und Netzwerkprotokolle 

deutlich verkürzt. Erstmals wurde eine auf dem 

neuen LEON-Prozessor basierende Modulbasis gewählt. 

Ausgehend von diesen Ergebnissen wurden 

verschiedene weiterführende Projekte zu Sensornetzwerken 

initiiert. 

5. Ultra-Wide-Band-Schaltkreise. 

Die Arbeiten erfolgten im Rahmen des Europäischen 

Projektes PULSERS, dessen Ziel die Entwicklung 

innovativer UWB-Schaltkreise ist. Erste 

am IHP entwickelte UWB-Komponenten wurden 

ausgewertet und optimiert. Erste Komponentengruppen 

wurden integriert. Im Rahmen der begonnenen 

zweiten Phase des Projektes erfolgt die Realisierung 

vollständiger UWB-Transceiver. 

6. Modulare Prozessor-Bibliothek. 

LEON-2- und LEON-3-Prozessoren wurden erfolgreich 

realisiert und getestet. Da diese Prozessoren 

in einer strahlungsharten Ausführung auch für z. B. 

Satelliteneinsätze verwendet werden sollen, wurde 

mit einer Prüfung der Strahlungsfestigkeit begonnen. 

Technologieplattform für drahtlose und Breitbandkommunikation 

Die 0,25-µm-BiCMOS-Technologien wurden 2005 stabilisiert 

und in ausgewählten Punkten weiterentwickelt. 

Ein zweiter wesentlicher Schwerpunkt war die Entwicklung 

eines 0,13-µm-BiCMOS-Prozesses als nächste 

Technologiegeneration des IHP für die Erforschung 

neuer Bauelemente-, Schaltungs- und Systemkonzepte 

sowie für den Prototyping-Service. Der Prototyping- 

Service des IHP wurde 2005 ausgebaut und weiter qualifiziert. 


velopment, latest high-performance technologies 

of the IHP were applied. 

4. Integrated wireless bus system for medical applications 

in the framework of the BASUMA project. 

The required node architecture was realized and 

successfully tested. The generic, event-controlled 

operating system REFLEX was ported and together 

with an innovative SDL cycle time environment integrated. 

That is the reason why the development 

periods for MAC and network protocols were distinctly 

shortened. For the first time a module basis, 

based on the new LEON processor, was selected. 

Based on these results, various ongoing projects 

on sensor networking were initiated. 

5. Ultra-Wideband circuits. 

The works were realized within the framework of 

the European project PULSERS, whose goal is the 

development of innovative UWB integrated circuits. 

First UWB-components, developed by the IHP, were 

analyzed and optimized. First component groups 

were integrated. In the framework of the initialized 

second phase of the project, the realization of integrated 

UWB transceivers takes place. 

6. Modular processor library. 

LEON-2- and LEON-3-Processors were successfully 

realized and tested. The processors in a radiation 

hard version also will be used for e.g. satellite 

missions. That is why, in a first step, the radiation 

resistance was tested. 

Technology platform for Wireless and Broadband 

Communication 

The 0.25 µm BiCMOS technologies were stabilized in 

2005 and were enhanced in specific points. A second 

essential emphasis was the development of a 0.13 µm 

BiCMOS process as the next technology generation of 

the IHP for the exploration of new devices-, circuits- 

and system concepts as well as for the Prototyping 

Service. The Prototyping Service of the IHP was enlarged 

and further qualified in 2005. 



12 

Beispiele für Ergebnisse 2005 sind: 

1. Stabilisierung und Weiterentwicklung der 0,25-µm- 

BiCMOS-Technologien. 

Das IHP stellte im Jahr 2005 vier 0,25-µm-BiCMOS- 

Technologien für die Realisierung interner Projekte 

sowie für den MPW & Prototyping Service zur 

Verfügung. Angeboten wurde die Technologiefamilie 

SG25 mit den Technologien SG25H1, H2 und 

H3, mit identischem CMOS- und Metallisierungsteil, 

aber unterschiedlichem Bipolarteil, sowie die Technologie 

SGB25VD. Detaillierte Angaben zu diesen 

Technologien finden sich im Kapitel „Angebote und 

Leistungen“ dieses Berichtes. 

2. Integration nichtflüchtiger Speicher in 0,25-µm- 

SiGe-BiCMOS. 

Es ist eine Prozesstechnologie zur Integration von 

„Embedded Flash“-Speichern, basierend auf einem 

„Floating-Gate“-Ansatz, in die 0,25-µm-SiGe- 

BiCMOS Technologieplattform entwickelt worden. 

Das Integrationskonzept ist modular und erfordert 

nur vier zusätzliche Maskenebenen. Für die Realisierung 

von nichtflüchtigen Registern wurde eine 

Konzep-tion zur Integration eines weiteren Zelltyps, 

der Single-Poly-Zelle, erarbeitet und es wurden erste 

Testschaltungen damit entworfen. 

3. SiGe-BiCMOS-Technologie für 77/79-GHz-Automobil- 

Radar 

Die Arbeiten des IHP erfolgten im Rahmen des 

BMBF-Verbundprojektes KOKON, in dem deutsche 

Automobilhersteller und die Halbleiterindustrie gemeinsam 

die Integration und Zuverlässigkeit von 

Si-Millimeterwellen-Schaltkreisen (MMIC) für die 

Anwendung als Radar-Sende/Empfangseinheit 

(Anti-Kollisions-Radar, Nahbereichs-Radar) im Frequenzbereich 

76-81 GHz testen. Im Rahmen des 

Projektes wurden spannungsgesteuerte Oszillatoren 

(VCO) bei 78 GHz entworfen und mit Technologien 

des IHP realisiert, wobei mit einem einstufigen 

Leistungsverstärker 9 mW Ausgangsleistung 

erreicht wurden. 

4. Entwicklung einer 0,13-µm-SiGe-BiCMOS-Techno- 

logie. 

2005 wurde mit der Entwicklung eines 0,13-µm- 

SiGe-BiCMOS-Prozesses als nächste Technologiegeneration 

für die Erforschung neuer Bauelemente, 

Schaltungs- und Systemkonzepte sowie für den 

Prototyping-Service des IHP begonnen. Bisher 



1. Stabilization and enhancement of the 0.25 µm 

BiCMOS technologies 

The IHP offered four 0.25 µm BiCMOS technologies 

in 2005 for the realization of IHP-intern projects as 

well as in MPW & Prototyping Service. Offered in 

this year was the SG25 technology family with the 

SG25H1, H2 and H3 technologies, with identical 

CMOS- and metallization but different bipolar part, 

as well as the SGB25VD technology. Detailed information 

about these technologies can be found 

in the chapter “Deliverables and Services” of this 

report. 

2. Integration of non-volatile memory in 0.25 µm SiGe 

BiCMOS. 

It is a technological process for the integration of 

“embedded flash”-memories, based on a “Floating- 

Gate”-approach, that was developed in the 0.25 µm 

SiGe BiCMOS technology platform. The integration 

concept is modular and demands only four additional 

mask levels. For the realization of non-volatile 

registers, a concept for the integration of another 

cell type, the Single-Poly-Cell, was developed, and 

first test circuits were designed with it. 

3. SiGe BiCMOS technology for 77/79 GHz automotive 

radar. 

The works of the IHP were realized in the framework 

of the BMBF cooperation project KOKON, in 

which German automobile producers and the semiconductor 

industry are jointly testing the integration 

and the reliability of Si-millimeter-wave integrated 

circuits (MMIC) for the application as radar 

transmitter/receiver units (Anti-Collision-Radar, Close-Range-Radar) 

in the frequency range 76-81 GHz. 

In the framework of the project, voltage-controlled 

oscillators (VCO) at 78 GHz were designed and realized 

with technologies of the IHP, whereas with 

a single stage power amplifier 9 mW output power 

were attained. 

4. Development of a 0.13 µm SiGe BiCMOS technology. 

In 2005 the development of a 0.13 µm SiGe BiCMOS 

process as the next technology generation for the 

exploration of new devices-, circuits- and system 

concepts as well as for the Prototyping Service of 

the IHP was initiated. Up to now, process modules

wurden die Prozessmodule für die Herstellung der 

Strukturen im 0,13-µm-Niveau entwickelt und erste 

Bipolar- und MOS-Transistoren mit 0,13 µm-Designregeln 

hergestellt. 

5. Weltweite Nutzung der IHP-Technologien durch 

MPW und Prototyping-Service. 

Die regelmäßigen Technologie-Shuttles am IHP ermöglichen 

auch Industriepartnern, Hochschulen 

und anderen Forschungseinrichtungen die Präparation 

innovativer Entwicklungsmuster und Prototypen. 

Derzeit arbeiten weltweit Designer aus mehr 

als 100 Einrichtungen mit dem Design-Kit des IHP. 

2005 wurden vier Shuttle Runs durchgeführt. Außer- 

dem wurden vier Engineering Runs für Partner 

präpariert. Durch eine verbesserte Infrastruktur 

(Design-Kit-Server) und zusätzliche Design-Kit-Versionen 

konnte das Angebot für Partner und Kunden 

weiter verbessert werden. 

Materialien für die Mikroelektronik-Technologie 

Ein Schwerpunkt der Materialforschung war die Nutzung 

der Ergebnisse zu Hoch-k-Isolatoren auf Basis 

von Praseodym für spezifische Anwendungen. Arbeiten 

zu neuen Gebieten wie silizium-basierte Lichtemitter 

und zur Verbindung von Drahtlos-Technologien mit 

biologischen Technologien wurden weitergeführt. 

Beispiele für Ergebnisse 2005 sind: 

1. Praseodymsilikat als Gateisolator für CMOS. 

Für die Anwendung als Gateisolator wurden Praseodymsilikate 

entwickelt, deren dielektrische Konstante 

den Wert 12 erreicht. Pr-Silikat-Schichten mit einer 

äquivalenten Oxidschichtdicke (EOT) von 1,8 nm 

zeigen eine um drei Größenordnungen kleinere Leckstromdichte 

im Vergleich zu Oxynitridschichten derselben 

EOT. Die Pr-arme Interfaceschicht bewirkt 

eine hohe Ladungsträgerbeweglichkeit im Kanal 

des MOSFETs. Der Schichtstapel ist bis zu CMOStypischen 

Prozesstemperaturen stabil. Die Integration 

der Schichten in einen konventionellen CMOS- 

Prozess wurde experimentell erprobt. 

2. MIM-Kondensatoren. 

Durch den laminaren Aufbau zweier dielektrischer 

Schichten, bestehend aus SiO 2 und Pr 2 Ti 2 O 7 , gelang 

es, einen leistungsstarken Kondensator für 

HF-Anwendungen zu entwickeln. Durch die Kombination 

einer 8 nm dicken SiO 2 - und einer 24 nm 


for the production of structures on 0.13 µm level 

were developed, and first bipolar- and MOS-transistors 

with 0.13 µm design rules were produced. 

5. Worldwide use of the IHP technologies by the MPW 

and Prototyping Service. 

The regular technology shuttles at IHP also allow 

industrial partners, universities and research institutes 

to prepare innovative development samples 

and prototypes. Designers are currently working 

worldwide in more than 100 organizations with 

the IHP design kit. Four Shuttle Runs were organized 

in 2005. Moreover, four Engineering Runs for 

partners were prepared. Through an improved infrastructure 

(Design-Kit-Server) and additional Design-Kit-Versions, 

the offer for partners and clients 

could be further improved. 

Materials for Microelectronics Technology 

A main focus of the materials research was the use 

of the results of High-k-Isolators on the basis of praseodymium 

for specific applications. Works on new 

areas like silicon-based light emitters and on the linking 

of wireless technologies with biological technologies 

were further developed. 


1. Praseodymium silicate as gate isolator for CMOS. 

For the application as gate isolator, praseodymium 

silicates were developed, whose high-k dielectric attained 

a value of 12. Pr-silicate layers with an equivalent 

oxide layer thickness (EOT) of 1.8 nm show 

a leakage current density that is three magnitudes 

smaller than the oxide nitride layers of the same 

EOT. The Pr-poor interface layer causes high charge 

carrier mobility in the MOSFET channel. The layer 

stack is constant up to CMOS-typical process temperatures. 

The integration of the layers in a conventional 

CMOS process was experimentally tested. 

2. MIM capacitors. 

Through the laminar construction of two dielectrical 

layers, which consist of SiO 2 and Pr 2 Ti 2 O 7 , the 

IHP succeeded in developing a powerful capacitor 

for RF-applications. Through the combination of 

8 nm thick SiO 2 - and a 24 nm thick Pr 2 Ti 2 O 7 -layer, 



14 

dicken Pr 2 Ti 2 O 7 -Schicht konnte eine Kapazität von 

3,2 fF/µm 2 bei extrem kleinen Leckströmen und 

vernachlässigbaren Kapazitäts-Spannungs-Koeffizienten 

erzielt werden. 

MIM-Kondensatoren mit Pr 2 O 3 als Dielektrikum erreichen 

hingegen eine sehr hohe Dielektrizitätskonstante, 

weisen aber zu hohe Leckströme auf. Mit 

Al 2 O 3 /Pr 2 O 3 /Al 2 O 3 -Schichtstapeln gelang es, eine 

Kapazität von 5,7 fF/µm 2 bei ausreichend geringer 

Leckstromdichte zu erreichen. 

3. Heteroepitaxie auf Si-Wafern. 

Die kontrollierte Herstellung heteroepitaktischer 

Halbleiter-Isolator-Halbleiter-Systeme ermöglicht die 

Fertigung innovativer SOI-Wafer. Im Mittelpunkt der 

Arbeiten des IHP stand 2005 die Entwicklung eines 

zwillingsfreien, kubischen Pr 2 O 3 (111)/Si(111)-Trägersystems. 

Dieses System steht jetzt als Basis für die 

Herstellung einkristalliner, heteroepitaktischer Epi- 

Si/Pr 2 O 3 /Si(111)-Schichtsysteme zur Verfügung. 

4. Kohärente Nukleation von Sauerstoffpräzipitaten in 

Silizium. 

Es wurde ein neues Modell für die kohärente Nukleation 

von Sauerstoffpräzipitaten entwickelt, das 

auf der Agglomeration von VO 2 -Komplexen beruht. 

Es ist das erste Modell, das die Nukleation von 

Sauerstoffpräzipitaten in Silizium auf der Basis kohärenter 

Keimbildung beschreibt. Alle bisherigen 

Modelle gehen von einem inkohärenten Nuklea- 

tionsprozess aus, der jedoch energetisch viel unwahrscheinlicher 

ist. 

5. Silizium-basierte Lichtemitter. 

Es wurde nachgewiesen, dass auf Implantation basierende 

Emitter (Band-Band-Linie bei 1,1 µm) eine 

ausgedehnte Lichtquelle darstellen können. Die 

Nutzung als On-Chip-Lichtquelle erscheint jedoch 

unwahrscheinlich, da die notwendige Rotverschiebung 

eine sehr dicke SiGe-Schicht erfordert. 

Direktes Si-Waferbonden (in Zusammenarbeit mit 

dem MPI für Mikrostrukturphysik Halle) erlaubt die 

reproduzierbare Erzeugung von Versetzungsnetzwerken. 

Dabei kann Licht sowohl bei Wellenlängen 

von 1,55 µm (D1-Linie) als auch 1,3 µm (D3-Linie) 

erzeugt werden. Wir erwarten, dass diese versetzungsbasierte 

Lichtquelle eine praktikable Lösung 

für den On-Chip-Lichtemitter werden kann. 


a capacity of 3.2 fF/µm 2 by extreme small leakage 

currents and negligible capacitance voltage coefficients 

was reached. 

By contrast, MIM-capacitors with Pr 2 O 3 as dielectric 

reach a very high permittivity but have a 

high leakage current. With Al 2 O 3 /Pr 2 O 3 /Al 2 O 3 -layer 

stacks, the IHP succeeded in reaching a capacity 

of 5.7 fF/µm 2 at a sufficient minor leakage current 

density. 

3. Heteroepitaxy on Si-wafers. 

The controlled production of heteroepitaxial semiconductor-insulator-semiconductor 

systems facilitated 

the production of innovative SOI wafers. In 

2005, the work of the IHP focused on the development 

of a twin-free, cubic Pr2O3(111)/Si(111)-carrier 

system. This system is now available as basis 

for the growth of monocrystalline, heteroepitaxial 

Epi-Si/Pr 2 O 3 /Si(111)-layer systems. 

4. Coherent nucleation of oxygen precipitates in silicon. 

A new model for coherent nucleation of oxygen 

precipitates that is based on the agglomeration of 

VO2-complexes was developed. It is the first model 

that describes the nucleation of oxygen precipitates 

in silicon on the basis of coherent nucleation. 

All the previous models assume an incoherent 

nucleation process, that is, however, energetically 

more improbable. 

5. Silicon-based light emitters. 

It was proven that implantation-based emitters 

(Band-Band-Line at 1.1 µm) can represent an expanded 

light source. However, the use as on-chip 

light source seems to be improbable, because the necessary 

red shift demands a very thick SiGe layer. 

Direct Si-wafer bonding (in cooperation with the 

MPI of Microstructure Physics, Halle) permits the 

reproducible creation of dislocation networks. Thereby, 

light at wavelengths both of 1.55 µm (D1- 

Line) and of 1.3 µm (D3-Line) can be generated. 

We expect that the dislocation-based light source 

can become a viable solution for the on-chip light 

emitter.

6. Projekte und Projektstudien zur Verbindung elektronischer 

und biologischer Technologien. 

Ziel des Projektes SOBSI ist die kontrollierte selbstorganisierte 

Anlagerung von Biomolekülen an die 

Si-Oberfläche unter Ausnutzung der Coulombschen 

Wechselwirkung zwischen den Versetzungen und 

Biomolekülen. Realisiert wurden bisher die gesteuerte 

Herstellung eines Versetzungsnetzwerkes und 

der Nachweis der Streufelder oberhalb der Si-Oberfläche. 

Eine Projektstudie zu integrierten SAW-Bauelementen 

für die Anwendung als Hochfrequenzfilter sehr 

hoher Güte und auch als Biosensoren wurde begonnen. 

Ziel ist die Integration in die BiCMOS-Technologie 

des IHP. 

Eine Projektstudie zur Entwicklung von Mikrochips 

für die biophysikalische Forschung wurde ebenfalls 

begonnen. Auf diesen Chips sollen Biomoleküle 

auf aktiven Gebieten immobilisiert und mit hochfrequenten 

elektrischen Feldern angeregt werden 

können. Diese Methodik ist geeignet für neuartige 

zeitaufgelöste Untersuchungen, die sowohl für 

die aktuelle biophysikalische Forschung als auch 

für die Sensorik von Biomolekülen von Bedeutung 

sind. 


6. Projects and project studies for the linking of electronic 

and biological technologies. 

The aim of the SOBSI project is the controlled, 

self-organized adsorption of biomolecules on the 

Si-surface with the exploitation of the Coulomb’s 

interaction between the dislocations and the biomolecules. 

Up to now, the controlled production of 

a dislocation network and the evidence of the stray 

fields above the Si-surface were realized. 

A project study about integrated SAW-devices for 

the application as high frequency filters in very 

high quality and also as biosensors was initiated, 

main objective being the integration in the BiCMOS 

technology of the IHP. 

A project study about the development of microchips 

for the biophysical research was also initiated. 

On these chips, biomolecules in active areas 

are to be immobilized and to be stimulated with 

high-frequency electrical fields. This method is suitable 

for novel time-resolved investigations, which 

are important for both the present biophysical research 

and the sensors for biomolecules. 


Angebote und Leistungen 

Deliverables and Services

Multiprojekt Wafer (MPW) 

und Prototyping Service 

Das IHP bietet seinen Kunden und Partnern Zugriff auf 

seine leistungsfähige 0,25-µm-SiGe-BiCMOS-Technologien. 

Die Technologien sind insbesondere für Anwendungen 

im oberen GHz-Bereich geeignet, so z.B. für die drahtlose 

und Breitbandkommunikation oder Radar. Sie 

bieten integrierte HBTs mit Grenzfrequenzen bis zu 

220 GHz und integrierte HF-LDMOS-Bauelemente mit 

Durchbruchspannungen bis zu 26 V einschließlich komplementärer 

Bauelemente. 

Verfügbar sind folgende vier Technologien: 

SG25H1: Eine Hochleistungs-Technologie mit npn- 

HBTs bis zu f T /f max = 180/220 GHz. 

SG25H2: Eine komplementäre Hochleistungs-Technologie 

mit npn-HBTs ähnlich SG25H1 

und zusätzlichen pnp-HBTs mit f T /f max = 

85/120 GHz. 

SG25H3: Eine Technologie mit mehreren npn-HBTs, 

deren Parameter von einer hohen HF-Performance 

(f T /f max = 110/190 GHz) zu höheren 

Durchbruchspannungen bis zu 7 V reichen. 

SGB25VD: Eine kostengünstige Technologie mit mehreren 

npn-Transistoren mit Durchbruchspannungen 

bis zu 7 V. Eine Besonderheit 

dieser Technologie sind zusätzliche integrierte 

komplementäre HF-LDMOS-Bauelemente 

mit Durchbruchspannungen bis zu 

26 V. 

Die Technologiefamilie SGC25 des IHP (SGC25A, 

SGC25B, SGC25C) wird weiterhin genutzt, aber derzeit 

durch die neue Familie SG25H mit verbesserten 

Parametern und zusätzlichen Leistungen ersetzt. 

Das IHP entwickelt derzeit eine 0,13-µm-BiCMOS-Technologie 

als nächste Generation. 

Es finden technologische Durchläufe nach einem festen, 

unter www.ihp-microelectronics.com verfügbaren 

Zeitplan statt. 

Angebote und 

Leistungen 


Multiproject Wafer (MPW) 

and Prototyping Service 

Deliverables and 

IHP offers customers and partners access to its powerful 

0.25 µm SiGe:C BiCMOS technologies. 

The technologies are suited to applications in the higher 

GHz bands (e.g. for wireless, broadband, radar). 

They provide integrated HBTs with cut-off frequencies 

of up to 220 GHz and RF LDMOS devices with breakdown 

voltages up to 26 V, including complementary 

devices. 

The following four technologies are available: 

Services 

SG25H1: A high-performance technology with npn- 

HBTs up to f T /f max = 180/220 GHz. 

SG25H2: A complementary high-performance technology 

with npn-HBTs comparable to 

SG25H1 and additional pnp-HBTs with 

f T /f max = 85/120 GHz. 

SG25H3: A technology with a set of npn-HBTs, 

ranging from a high RF performance 

(f T /f max = 110/190 GHz) to high breakdown 

voltages up to 7 V. 

SGB25VD: A cost-effective technology with a set of 

npn-HBTs up to a breakdown voltage of 7 V. 

A distinctive feature of this technology is 

additional integrated complementary RF 

LDMOS devices with breakdown voltages 

up to 26 V. 

IHP’s SGC25-family of technologies (SGC25A, SGC25B, 

SGC25C) is still running but is currently replaced by 

the new SG25H-family with improved parameters and 

additional features. 

IHP is developing its next generation 0.13 µm BiCMOS 

technology. 

The schedule for MPW & Prototyping runs is available 

at www.ihp-microelectronics.com. 

17

Angebote und 

Leistungen 

18 

Parameter npn pnp 

Bipolar Section 

A E 


Services 

Ein Cadence-basiertes Design-Kit für Mischsignale ist 

verfügbar. Wiederverwendbare Schaltungsblöcke und 

IPs des IHP für die drahtlose und Breitbandkommunikation 

werden zur Unterstützung von Kundendesigns 

angeboten. 

In den folgenden Tabellen sind die wesentlichen Parameter 

der für MPW und Prototyping angebotenen Technologien 

dargestellt: 

1. 0,25-µm-Hochleistungs-SiGe-BiCMOS-Techno- 

logie (SG25H1). 

2. Komplementäre 0,25-µm-Hochleistungs-SiGe- 

BiCMOS-Technologie (SG25H2). 

0.21 x 0.84 µm 2 

Peak f max 170 GHz 120 GHz 

Peak f T 170 GHz 85 GHz 

BV CE0 1.9 V 2.5 V 

V A 40 V 30 V 

� 160 100 

Der CMOS-Bereich und die passiven Bauelemente entsprechen 

SG25H3. 


A cadence-based mixed signal design kit is available. 

IHP’s reusable blocks and IPs for wireless and broadband 

are offered to support customer designs. 

Technical key-parameters of the technologies offered 

for MPW and Prototyping are: 

1. High-Performance 0.25 µm SiGe BiCMOS-Technology 

(SG25H1). 

Parameter npn1 npn2 


A E 0.21 x 0.84 µm 2 0.18 x 0.84 µm 2 

Peak f max 190 GHz 220 GHz 

Peak f T 190 GHz 180 GHz 

BV CE0 1.9 V 1.9 V 

V A 40 V 40 V 

� 200 200 

Der CMOS-Bereich und die passiven Bauelemente entsprechen 

SG25H3. 

For CMOS section and passives please see SG25H3. 

2. Complementary High-Performance 0.25 µm 

SiGe BiCMOS (SG25H2). 

For CMOS section and passives please see SG25H3.

3. 0,25-µm-SiGe-BiCMOS-Technologie mit mehreren 

npn-HBTs im Bereich von großer HF Performance 

bis zu höheren Durchbruchspannungen 

(SG25H3). 

Parameter High 

Performance 


Angebote und 

Leistungen 

High 

Performance 1 


Services 

3. 0.25 µm SiGe BiCMOS with a set of npn-HBTs, 

ranging from high RF performance to high 

breakdown voltages (SG25H3). 

High 

Performance SHP 

High 

Performance 2 

A E 0.21 x 0.84 µm 2 0.42 x 0.84 µm 2 0.21 x 0.84 µm 2 0.21 x 0.84 µm 2 

Peak f max 190 GHz 140 GHz 140 GHz 80 GHz 

Peak f T 110 GHz 120 GHz 45 GHz 25 GHz 

BV CE0 2.3 V 2.3 V 5 V 7 V 

V A 30 V 30 V 30 V 30 V 

� 150 150 150 150 

CMOS Section (0.25 µm) Value 

Passives 

Core Supply Voltage 2.5 V 

nMOS Vth 0.6 V 

IDsat 540 µA/µm 

I off 3 pA/µm 

pMOS Vth -0.56 V 



MIM Capacitor 1 fF/µm 2 

N + Poly Resistor 210 �/[ ] 

P + Poly Resistor 295 �/[ ] (SG25H3) 

280 �/[ ] (SG25H1/H2) 

High Poly Resistor 1850 �/[ ] (SG25H3) 

1600 �/[ ] (SG25H1/H2) 

Varactor C /C max min 

3 

Inductor Q@2.4 GHz 12 (1 nH), 6 (15 nH) 



Angebote und 

Leistungen 

20 

n-LDMOS p-LDMOS 

n-LDMOS 23 n-LDMOS 13 n-LDMOS 

I10**** 

p-LDMOS 8 p-LDMOS 12 

BV DSS * 26 V 16 V 11.5 V -11 V -13.5 V 

I Dsat ** 140 µA/µm 

(V GS = 1.5 V) 

I leakage 

< 15 pA/µm 

(V DS = 20 V) 


Services 

4. 0,25-µm-SiGe-BiCMOS-Technologie mit Bau- 

elementen für höhere Spannungen (SGB25VD). 

Die Technologie enthält neben HBTs auch komplementäre 

HF-LDMOS-Bauelemente. In den folgenden zwei 

Tabellen sind wichtige Parameter zusammengefasst. 


Parameter 

A E 

140 µA/µm 

(V GS = 1.5 V) 

< 15 pA/µm 

(V DS = 10 V) 

175 µA/µm 

(V GS = 1.5 V) 

< 15 pA/µm 

(V DS = 8 V) 


85 µA/µm 

(V GS = -1.5 V) 

< 50 pA/µm 

(V DS = -8 V) 

90 µA/µm 

(V GS = -1.5 V) 

< 50 pA/µm 

(V DS = -8 V) 

R ON 11 �mm 7 �mm 7.5 �mm 16 �mm 11.5 �mm 

Peak f max *** 40 GHz 43 GHz 46 GHz 21 GHz 22 GHz 

Peak f T *** 19 GHz 23 GHz 21 GHz 8 GHz 11 GHz 

*:@100 pA/µm **:@V DS = 5 V ***:@V DS = 4 V ****: substrate isolated 

4. 0.25 µm SiGe BiCMOS with High-Voltage Devices 

(SGB25VD). 

In addition to HBTs the technology also has complementary 

RF LDMOS. Key parameters are summarized 

in the following two tables. 

High 

Performance Standard 

0.5 x 0.9 µm 2 

High 

Voltage 

Peak f max 95 GHz 90 GHz 70 GHz 

Peak f T 75 GHz 45 GHz 25 GHz 

BV CEO 2.4 V 4.0 V 7.0 V 

BV CBO > 7 V > 15 V > 20 V 

V A >50 V >80 V >100 V 

� 190 

CMOS Section (0.25 µm) 

Passives 

Core Supply Voltage 2.5 V 

nMOS Vth 0.6 V 



pMOS Vth -0.51 V 



MIM Capacitor 1 fF/µm 2 

P + Poly Resistor 310 �/[ ] 

High Poly Resistor 2000 �/[ ] 

Varactor C /C max min 

3 


Inductor Q@5.8 GHz 16 (1 nH), 10 (2 nH)

Design Kit 

Die Design Kits unterstützen eine Cadence Mischsignal- 

Plattform: 

- Design Framework II (Cadence 5.0-5.1) 

- Verhaltens-Beschreibung (Verilog HDL) 

- Logische Synthese und Optimierung (VHDL/HDL 

Compiler, Design Compiler/Synopsys, Power Compiler/Synopsys) 

- Test Generation/Synthetisierer/Test Compiler (Synopsys) 

- Simulation (RF: SpectreRF, Analog: SpectreS, Verhaltens-Beschreibung/Digital:Leapfrog/NC-Affirma/Verilog-XL/ModelSim) 

- Platzieren und Verbinden (Silicon Ensemble und 

Preview) 

- Layout (Virtuoso Editor-Cadence) 

- Verifizierung (Diva and Assura: DRC/LVS/Extract/ 

Parasitic Extraction) 

- ADS-Support über RFDE/RFIC mit dynamischem 

Link zu Cadence ist verfügbar 

- Ein eigenständiges ADS Kit einschließlich Momentum 

Substrate Layer File wird unterstützt, jedoch 

ohne Layout-Unterstützung 

- Unterstützung von Analog Office und Tanner über 

Partner. 

Verfügbare analoge und digitale 

Blöcke und Designs für die drahtlose 

und Breitbandkommunikation 

Zur Unterstützung von Kundendesigns bietet das IHP 

Schaltungsblöcke und Schaltungen für Lösungen im 

Bereich drahtlose und Breitbandkommunikation an: 

- 2,4-GHz-Transceiver-Komponenten wie LNAs, Mischer, 

VCOs, Teiler, Prescaler, Demodulatoren, Frequenzsynthesizer 

und Zwischenfrequenz-Verstärker 

- 2,4-GHz-Single-Chip PA/LNA/RX/TX-Switch in hybrider 

Technologie 

- 5-GHz-(IEEE 802.11a/p, HiperLAN/2)-Single-Chip- 

Transceiver und Komponenten wie z.B. 5 GHz 

VCOs, Polyphasenfilter, Zwischenfrequenz-Abwärts- 

Angebote und 

Leistungen 

Design Kit 

The design kits support a Cadence mixed signal platform: 

- Design Framework II (Cadence 5.0-5.1) 

- Behavioral Modeling (Verilog HDL) 

- Logic Synthesis and Optimization (VHDL/HDL Compiler, 

Design Compiler/Synopsys, Power Compiler/ 

Synopsys) 

- Test Generation/Synthesizer/Test Compiler (Synopsys) 

- Simulation (RF: SpectreRF, Analog: SpectreS, Behavioral/Digital: 

Leapfrog/NC-Affirma/Verilog-XL/ 

ModelSim) 

- Place and Route (Silicon Ensemble and Preview) 

- Layout (Virtuoso Editor - Cadence) 


- Verification (Diva and Assura: DRC/LVS/Extract/ 

Parasitic Extraction) 

- ADS-support via RFDE/RFIC dynamic link in Cadence 

is available 

- A standalone ADS Kit including Momentum substrate 

layer file is supported but without layout 

support. 

- Support of Analog Office and Tanner via partners 

is available. 

Available Analog and Digital 

Blocks and Designs for Wireless 

and Broadband 

Services 

To support customer designs, IHP offers a wide range 

of blocks and designs for wireless and broadband 

solutions: 

- 2.4 GHz transceiver components, such as LNAs, 

mixers, VCOs, dividers, prescalers, demodulators, 

frequency synthesizers, and IF amplifiers 

- Hybrid 2.4 GHz single-chip PA/LNA/RX/TX-switch 

- 5 GHz (IEEE 802.11a/p, HiperLAN/2) single-chip 

transceiver and components, such as 5 GHz VCOs, 

polyphase filters, IF down mixers, gain controlled 


Angebote und 

Leistungen 

22 

Mischer, spannungsgesteuerte Verstärker, aktive 

Basisband-Filter, Synthetisierer, I 2 C-Bus Interface; 

vollständiger Single-Chip IP-Block 

- DAC-Komponenten für mittlere und hohe Geschwindigkeiten 

bis zu 10 GSps 

- UWB Transceiver-Komponenten wie Pulsgenerator, 

Mischer Korrelator, LNA 

- 24-GHz-Mischer, 24-GHz-VCO 

- Statische und dynamische Teilerschaltungen bis zu 

60 GHz; 60-GHz-LNA, PLL, Mischer und VCO 

- 76-GHz-LC-Oszillator 


Services 

- SPW (Signal Processing Worksystem) und MATLAB- 

Modelle für einen digitalen Basisband-Prozessor 

für ein IEEE 802.11a/p-konformes Modem einschließlich 

der Einheiten für Synchronisation und 

Kanalschätzung 

- Designs für Basisband-Verarbeitung (Viterbi Decoder, 

FFT/IFFT Prozessor, CORDIC Prozessor) 

- Synthetisierbares VHDL Modell des kompletten 

IEEE 802.11a OFDM Basisband-Prozessors einschließlich 

der Synchronisation und Kanalschätzung 

- Echtzeit-Implementierung des MAC-Layer für ein 

IEEE 802.11a-kompatibles Modem für eingebettete 

Anwendungen, bestehend aus einem auf MIPS- 

oder ARM-Prozessoren laufenden C-Programm sowie 

einem speziellen Hardware-Beschleuniger 

- Ein abstraktes SDL-Modell des MAC-Layer für ein 

IEEE 802.11a-und HiperLAN/2-kompatibles Modem 

mit Testbenches für verschiedene Anwendungs- 

Szenarien 

- Ein abstraktes SDL-Modell für IEEE 802.15.3 und 

IEEE 802.15.4 

- 5-GHz-Link-Emulator und Entwicklungsumgebung 

für WLAN 

- TCP/IP-Prozessor einschließlich Hardware-Beschleuniger 

für das Protokoll sowie symmetrische und 

asymmetrische Verschlüsselung einschließlich MD5. 


amplifiers, active baseband filters, synthesizer, and 

I 2 C-Bus interface; full single-chip IP block 

- DAC components for medium and high speed up to 

10 GSps 

- UWB transceiver components such as pulse generator, 

mixer correlator, LNA 

- 24 GHz mixers, 24 GHz VCOs 

- Static and dynamic divider circuits for up to 60 GHz; 

60 GHz LNA, PLL, mixers, VCO 

- 76 GHz LC-oscillator 

- SPW (Signal Processing Worksystem) and MAT- 

LAB models of a digital baseband processor for 

an IEEE 802.11a/p compliant modem, including the 

synchronization and channel estimation units 

- Designs for baseband processing (Viterbi decoder, 

FFT/IFFT processor, CORDIC processor) 

- Synthesizable VHDL model of the complete IEEE 

802.11a OFDM baseband processor including synchronization 

and channel estimation 

- Realtime implementation of the MAC layer for an 

IEEE 802.11a compliant modem for embedded 

applications consisting of a C-program running on 

MIPS or ARM processors, and a dedicated hardware 

accelerator 

- Abstract SDL model of MAC layer for IEEE 802.11a 

and HiperLAN/2 compliant modem with testbenches 

for various deployment scenarios 

- Abstract SDL model for IEEE 802.15.3 and IEEE 

802.15.4 

- 5 GHz link emulator and WLAN design/debug kit 

- TCP/IP-processor including hardware accelerators 

for protocol and symmetric and asymmetric encryption 

including MD5 .

Transfer von Technologien und 

Technologie-Modulen 

Das IHP bietet den Transfer seiner 0,25-µm-BiCMOS- 

Technologien und Technologiemodule (HBT, LDMOS) 

an. Die technologischen Parameter entsprechen weitgehend 

den oben für MPW & Prototyping genannten. 

Für die Technologie SGB25VD sind außerdem Bau- 

elemente mit höherer als der genannten Performance 

verfügbar. 

Unterstützung bei Prozess-Modulen 

Das IHP bietet Unterstützung bei der Realisierung spezieller 

Prozess-Module für Forschung und Entwicklung 

und für Prototyping bei geringen Volumina für Standard-Prozess-Module 

und Prozess-Schritte. 

Verfügbar sind u.a. folgende Prozess-Module: 

- Standard-Prozesse (Implantation, Ätzen, CMP und Abscheidung 

von Schichtstapeln wie thermisches SiO 2 , 

PSG, Si 3 N 4 , Al, TiN, W) 

- Hochtemperatur- und Niedertemperatur-Epitaxie 

(Si, Si:C, SiGe, SiGe:C) 

- Optische Lithographie (i-Linie und 248 nm bis hinab 

zu 100 nm Strukturgröße) 

- Verkürzte Prozessabläufe. 

Fehleranalyse und Diagnostik 

Das IHP bietet Unterstützung bei der Ausbeuteerhöhung 

durch Fehleranalyse mit modernen Ausrüstungen 

wie z.B. AES, AFM, FIB, LST, REM, SIMS, STM 

und TEM. 

Für weitere Informationen wenden Sie sich bitte an/ For more information please contact: 

Dr. Wolfgang Kissinger 


Im Technologiepark 25 

15236 Frankfurt (Oder), Germany 

Email kissinger@ihp-microelectronics.com 

Telefon +49 335 56 25 410 

Telefax +49 335 56 25 222 

Angebote und 

Leistungen 

Transfer of Technologies and 

Technology Modules 

IHP offers its 0.25 µm BiCMOS technologies and technology 

modules (HBT-Modules, LDMOS-Modules) for 

transfer. 

The technological parameters comply to a large extent 

with the parameters described above for MPW and 

Prototyping. For SGB25VD, additional devices with a 

higher performance are available. 

Process Module Support 

IHP offers support for advanced process modules for 

research and development purposes and small volume 

prototyping. 

Process modules available include: 

- Standard processes (implantation, etching, CMP 

and deposition of layer stacks such as thermal 

SiO 2 , PSG, Si 3 N 4 , Al, TiN, W) 

- High-temperature and low-temperature epitaxy (Si, 

Si:C, SiGe, SiGe:C) 

- Optical lithography (i-line and 248 nm down to 100 nm 

structure size) 

- Short-flow processing. 


Failure Mode Analysis and Diagnostics 

IHP offers support for yield enhancement through failure 

mode analysis with state-of-the-art equipment, 

including AES, AFM, FIB, LST, SEM, SIMS, STM and 

TEM. 

Dr. Renè Scholz 




Email scholz@ihp-microelectronics.com 

Phone +49 335 56 25 647 

Fax +49 335 56 25 222 

Services 


Forschung des IHP 

IHP’s Research

Das IHP arbeitet an drei eng miteinander verbundenen 

Forschungsprogrammen. Gemeinsames Ziel ist 

die Schaffung innovativer Lösungen für Anwendungen 

in den Bereichen drahtlose und Breitbandkommunikation. 

Die Forschungsprogramme nutzen die besonderen 

Möglichkeiten des IHP. So verfügt das IHP über eine 

Pilotlinie für technologische Entwicklungen sowie für 

die Fertigung von Chips für eigene Projekte und Entwicklungen 

Dritter. Eine weitere Besonderheit ist das 

vertikale Forschungskonzept des IHP unter Nutzung 

der zusammenhängenden und aufeinander abgestimmten 

Kompetenzen des Institutes auf den Gebieten Systementwicklung, 

Schaltungsentwurf, Technologie und 

Materialforschung. 

Die Forschung des IHP setzt ebenso auf die typischen 

Stärken eines Leibniz-Institutes: Sie ist charakterisiert 

durch eine langfristige, komplexe Arbeit, die Grundlagenforschung 

mit anwendungsorientierter Forschung 

verbindet. 

Die Realisierung der Forschungsprogramme erfolgt 

mit Hilfe eines regelmäßig aktualisierten Portfolios 

von Projekten. Die Aktualisierung geschieht aufgrund 

inhaltlicher Erfordernisse sowie der Möglichkeiten für 

Kooperationen und Finanzierung. Drittmittelprojekte 

werden im Einklang mit den strategischen Zielen des 

IHP eingeworben. 

Im Folgenden werden wesentliche Zielstellungen der 

Forschungsprogramme des IHP beschrieben. 

Drahtloses Internet: Systeme und 

Anwendungen 

In diesem Programm werden komplexe Systeme für 

das drahtlose Internet in Form von Prototypen und Anwendungen 

untersucht und entwickelt. Ziel sind Hardware/Software-Systemlösungen 

auf hochintegrierten 

Single-Chips. Der vertikale Forschungsansatz zeigt 

sich auch in der Architektur der erarbeiteten Systeme. 

Im Wesentlichen wird die Wechselwirkung zwischen 

den Schichten optimiert und eine vertikale Migration 

der semantischen Elemente realisiert. 

Die drei Hauptforschungsrichtungen sind Systeme mit 

hoher Performance, Systeme mit geringem Energieverbrauch 

und Middleware für kontextabhängige Anwendungen. 


Forschung des IHP IHP‘s Research 

IHP is working on three closely connected research 

programs. The joint objective is the creation of innovative 

solutions for wireless and broadband applications. 

The research programs make use of the special opportunities 

of the IHP. In this way the institute has a 

pilot line for technological developments as well as 

for manufacturing chips for its own projects and the 

developments of third parties. An additional particularity 

is the IHP vertical research concept employing 

the associated and harmonized competencies of the 

institute in the fields of system development, circuit 

design, technology and materials research. 

The research of the IHP is based on the typical 

strengths of a Leibniz Institute; it is dominated by 

long-term, complex efforts which connect basic research 

with application-oriented research. 

The realization of the programs is accomplished through 

a project portfolio which is regularly updated according 

to the content requirements as well as through opportunities 

for cooperations and outside funding. Grant projects 

are acquired in such a manner as to serve the 

strategic goals of IHP. 

Significant goals of IHP’s research programs are specified 

below. 

Wireless Internet: Systems and Applications 

This program investigates and develops complex systems 

for wireless Internet as prototypes and applications 

with the objective to find solutions for Hardware/ 

Software systems on highly integrated single chips. 

The vertical approach is also reflected in the architecture 

of the addressed systems. Basically inter-layer 

interaction is optimized and vertical migrations of semantic 

elements are performed. 

The three major directions of research are systems 

with high performance, systems with low-power consumption 

and middleware systems for context sensitive 

applications. 

25


Für drahtlose Systeme mit hoher Performance ist es das 

Ziel, alle Funktionen eines drahtlosen PDA auf einem Chip 

zu integrieren. Dabei sollen Datenraten bis über 1 Gbps 

bei Trägerfrequenzen bis zu 60 GHz erreicht werden. 

Die Forschung zu Systemen mit geringem Energieverbrauch 

hat zum Ziel, Sensornetze auf einem Chip zu 

realisieren. Typische Anwendungen dafür sind Body- 

Area-Netze für medizinische Anwendungen oder Wellness. 

Die Forschung zu kontextabhängigen Middleware-Systemen 

betrifft insbesondere auch den Schutz der Privatsphäre 

und die Sicherheit bei der Nutzung mobiler 

Endgeräte. Darüber hinaus wird die symmetrische 

bzw. asymmetrische Verteilung von Ressourcen zwischen 

Endgeräten und Servern im Gesamtsystem untersucht. 

Technologieplattform für drahtlose 

und Breitbandkommunikation 

In diesem Programm sollen Technologien mit zusätzlichen 

Funktionen entwickelt werden, insbesondere 

durch die Erweiterung industrieller CMOS-Technologien. 

Die Hauptforschungsrichtungen in diesem Programm 

sind Technologien mit hoher Performance, kostengünstige 

Technologien und System-on-Chip, sowie die Sicherung 

des Zugriffs interner und externer Designer auf 

die Technologien des IHP. 

Die Forschung in Richtung Technologien hoher Performance 

zielt auf extrem schnelle SiGe-HBTs, einschließlich 

komplementärer Bauelemente und neuer Bauelementekonzepte 

für Anwendungen bei Frequenzen bis 

oberhalb 100 GHz. 

Zielstellung der Forschung für kostengünstige Technologien 

ist es, BiCMOS-Technologien mit ausreichender 

Performance und geringen Fertigungskosten zu ent- 

wickeln sowie darin zusätzliche Module wie HF-LDMOS, 

Flash und passive Bauelemente zu integrieren. 

Die 0,25-µm-BiCMOS-Technologien des IHP sind weltweit 

für Designer nutzbar. Ein Zeitplan für die entsprechenden 

technologischen Durchläufe in der Pilotlinie 

in Frankfurt (Oder) ist über die Internetadresse des 

IHP verfügbar. Eine neue 0,13-µm-BiCMOS-Technologie 

wird entwickelt. 

26 


The goal for high-performance wireless systems is to integrate 

all functionalities of a wireless PDA on a single 

chip. The targets are to achieve a data rate exceeding 

1 Gbps at carrier frequencies of up to 60 GHz. 

The research on systems with low energy consumption 

is directed towards sensor networks on single 

chips. Typical applications are body-area networks for 

health care or wellness. 

Research in context-sensitive middleware systems 

addresses privacy and security questions in using mobile 

devices. Moreover we investigate symmetrical and 

asymmetrical resource distribution between client and 

server parts of the overall system. 

Technology Platform for Wireless 

and Broadband 

The aim of this program is to develop value-added 

technologies, preferably BiCMOS technologies, by the 

modular extension of industrial CMOS. The major directions 

of the research in this program are technologies 

with a high performance, low-cost technologies 

including system-on-chip, and the provision of technology 

access for internal and external designers. 

The research towards high-performance technologies 

targets ultrafast SiGe HBTs, including complementary 

devices and new device concepts, for applications at 

frequencies of up to more than 100 GHz. 

The aim of the research for low-cost technologies is 

to develop BiCMOS technologies with ample performance 

and low manufacturing costs and to integrate 

additional modules such as RF LDMOS, Flash and passive 

devices. 

IHP’s 0.25 µm BiCMOS technologies are worldwide 

available for designers. A schedule for technological 

runs in the pilot line in Frankfurt (Oder) is available via 

IHP`s internet address. A new 0.13 µm SiGe BiCMOS 

technology is under development.

Materialien für die Mikroelektronik- 

Technologie 

Die Materialforschung am IHP hat die Integration neuer 

Materialien in die Technologie zum Ziel, um so zusätz- 

liche oder bessere Funktionalitäten zu erreichen. Außerdem 

bereitet sie neue Forschungsgebiete am IHP vor. 

Derzeit ist die Auswahl und Fertigung von Isolatoren 

hoher Dielektrizitätskonstante einschließlich der zugehörigen 

Gate-Materialien ein Schwerpunkt der Materialforschung 

am IHP. Anwendungsspezifische Entwicklungen 

dieser Isolatoren für MIMs (Metall Isolator 

Metall), Speicher, CMOS und SOI werden gemeinsam 

mit den Technologen des IHP bzw. mit industriellen 

Partnern realisiert. 

Weitere Projekte werden auf neuen und aussichtsreich 

erscheinenden Gebieten durchgeführt. Bei erfolgversprechenden 

Ergebnissen werden sie mit höherer Kapazität 

fortgesetzt. Beispiel für derartige Forschungsgebiete 

ist die Integration optischer Datenübertragung in 

der Mikroelektronik oder die Nutzung drahtloser Netzwerke 

für biologische oder medizinische Anwendungen. 

Auf den folgenden Seiten sind ausgewählte Projekte 

der Forschungsprogramme des IHP beschrieben. 


Materials for Microelectronics Technology 

Materials research at IHP targets the integration of 

new materials into the technology to achieve additional 

or better functionalities. It also geared towards the 

preparation of new research fields at the institute. 

Currently, the selection and manufacturing of insulators 

with high permittivity, including the associated 

gate materials, is one focal point of IHP’s materials 

research. Application-specific developments of these 

insulators for MIMs (metal insulator metal), memory, 

CMOS and SOI are realized together with IHP’s technology 

or with industrial partners. 

Additional projects are conducted in new and promising 

areas. In successful cases they are then worked 

on with increased capacity. Examples for promising 

research areas include the integration of optical data 

transmissions in microelectronics ort he employment 

of wireless networks for biological or medical applications. 

On the following pages you will find a description of selected 

projects from IHP’s research programs. 


Ausgewählte Projekte 

Selected Projects

Drahtloses Internet/ 

Wireless Internet 

Mobile Business Engine Mobile Business Engine 

Im Rahmen des Projektes „Mobile Business Engine“ 

werden Mechanismen zum Schutz der Privatsphäre 

und von privaten sowie geschäftlichen Daten im drahtlosen 

Internet untersucht. Diese Ansätze werden in die 

am IHP entwickelte Middleware-Plattform PLASMA, die 

die Realisierung kontext-sensitiver Dienste unterstützt, 

integriert. 

Das Zusammenwachsen von Mobilkommunikation und 

Internet bietet die Möglichkeit zur Realisierung neuartiger 

Dienste, Arbeitsabläufe und Geschäftsmodelle. 

Der Erfolg derartiger Dienste hängt stark von dem 

ihnen entgegen gebrachten Vertrauen ab. In Business-to-Employee-Prozessen 

steht der Schutz der 

Geschäftsdaten im Vordergrund, wohingegen in Business-to-Consumer-Prozessen 

eher der Schutz der Privatsphäre 

gewährleistet werden muss. Für beide Bereiche 

gilt: Alle Daten müssen während des Transportes, 

aber auch auf den verwendeten Endgeräten geschützt 

werden. 

Für den Schutz der Privatsphäre wurden mit dem 

Werkzeug Privacy Advocate und dem Micro Payment 

System MONETA zwei Ansätze verfolgt. 

Der Privacy Advocate (PrivAd) ist ein Werkzeug, das 

den Nutzern von Diensten die Möglichkeit gibt, mit 

Dienstanbietern darüber zu verhandeln, welche Daten 

bereitgestellt werden müssen und für welche Zwecke 

diese anschließend verwendet werden dürfen. Das Verhandlungsergebnis 

wird von beiden Seiten digital signiert 

und gespeichert. PrivAd nutzt für die Verhandlungen 

ein am IHP entwickeltes Datenmodell und ist zu 

P3P kompatibel. Daher können Server, die PrivAd einsetzen, 

auch mit P3P-basierten Werkzeugen wie dem 

PrivacyBird von AT&T kommunizieren. Auch PrivAd nutzende 

mobile Endgeräte können weiterhin mit Servern 

interagieren, die keine oder nur statische Privacy Policies 

nutzen. Dabei verhält sich PrivAd dann ähnlich wie 

der PrivacyBird und gibt lediglich Warnungen ab, wenn 

die Privacy Policy des Servers nicht zu den Wünschen 

des Nutzers passt. Unsere Messungen zeigen die Effizienz 

des PrivAd. Die Dauer der Verhandlung hängt von 

den eingesetzten Strategien ab. Unsere Experimente 


Drahtloses Internet 


Selected Projects 


The project Mobile Business Engine includes research 

on mechanisms that allow protecting privacy and business 

information in the wireless Internet. These approaches 

are integrated in PLASMA, a middleware platform 

for context-aware services developed at the IHP. 

The evolution of mobile communication and Internet 

allows new innovative services and also new ways 

for working and doing business. The success of these 

new services depends on the trust users have in 

them. In the business-to-employee scenario the most 

important issue is the protection of business information, 

whereas in the business-to-consumer scenario 

the privacy of the user must be protected. However, 

in both cases the data should be protected also while 

it is transmitted over the network and also while it is 

processed on the device. 

Two approaches that protect privacy were investigated. 

The first one is the Privacy Advocate tool and the 

second is the micro payment scheme MONETA. 

The Privacy Advocate (PrivAd) tool allows the service 

user to negotiate with the service provider which data 

is going to be used in a specific transaction and for 

what purposes this data may be used later on. The result 

of this negotiation is digitally signed by both parties 

and stored. For the negotiation, the PrivAd uses a 

data model developed at the IHP which is compatible 

with P3P, i.e., the servers that use PrivAd are able to 

communicate with P3P based tools such as Privacy- 

Bird from AT&T. Additionally, PrivAd allows mobile devices 

to interact with servers that use a static Privacy 

Policy or even those without any Privacy Policy, but 

in these cases PrivAd behaves similar to PrivacyBird 

and just warns the user that the Privacy Policy of the 

server does not fit to the user’s requirements. Our 

measurements show that PrivAd is an efficient tool. 

The negotiation time depends on the strategies used. 

We experimentally determined negotiation times of 

100-200 ms. Fig. 1 demonstrates the influence of the 

network on the negotiation time. It takes about 2 s in 

wireless networks but only about 250 ms in a fast wired 

LAN. 

29

haben Verhandlungsdauern von ca. 100-200 ms ergeben. 

Abb. 1 zeigt den Einfluss des Netzwerkes auf die 

Verhandlungsdauer. In drahtlosen Netzen beträgt diese 

ca. 2 s, während eine Verhandlung über ein schnelles 

drahtgebundenes Netzwerk nur ca. 250 ms benötigt. 

MONETA bietet die Möglichkeit, Kleinstbeträge für die 

Nutzung eines Dienstes abzurechnen. Hierfür werden 

e-Coins zwischen dem Dienstnutzer und dem Dienstanbieter 

ausgetauscht. Die MONETA-Architektur kommt 

daher ohne Payment-Service-Provider aus. Die MONE- 

TA e-Coins sind so gestaltet, dass die Identität des Besitzers 

nicht sichtbar ist, solange dieser keinen e-Coin 

mehrfach zum Bezahlen nutzt. Hierfür wurden die Hidden-Identity-Ansätze 

von Brands und Neumann/Baumgart 

überarbeitet, insbesondere verwendet MONETA 

elliptische Kurven-Kryptographie (ECC) als asymme- 

trisches Verschlüsselungsverfahren. Gemeinsam mit 

der lesswire AG wurde ein bezahlter ortssensitiver Informationsdienst 

auf der Basis von PLASMA und MONETA 

realisiert und bei der CeBIT 2005 vorgestellt. Die Leistungsdaten 

dieses Demonstrators belegen eindeutig 

die Tragfähigkeit des Ansatzes. Die in Tabelle 1 dargestellten 

Messergebnisse zeigen sowohl die Effizienz 

unserer Lösung für anonyme Bezahlung als auch unserer 

Plattform PLASMA für ortsabhängige Dienste. 

Sowohl PrivAd als auch MONETA können die im Rahmen 

dieses Projektes entwickelten Hardware-Beschleuniger 

für AES (Advanced Encryption Standard) 

und ECC zur Realisierung weiterer Leistungsverbesserungen 

nutzen. 

30 





Operation Client PLASMA Service 

Location 

Forwarding 1) 0.0625 ms -- 

Location 

Query 2) 

-- 45 ms 

Payment 0.1 ms/coin 3) -- 200 ms/coin 4) 

1) : Client sends position to PLASMA 

2) : Service requests client position from PLASMA 

3) : Client prepares coin 4) : Server checks coin 

Tabelle 1: Leistungsparameter für kostenpflichtigen Informationsservice 

bei Einsatz der folgenden Geräte: Mobiles Endgerät: 

IPAQ 5500 (400 MHz, Xscale Prozessor); Server: PC (2 GHz). 

Table 1: Performance of the paid information application running on 

the following devices: Client: IPAQ 5550 (400 MHz, Xscale 

processor); Server: PC (2 GHz). 


MONETA makes it possible to pay a small amount of 

money for the use of a service. To do this the user 

transfers e-coins to the service provider. The architecture 

of MONETA does not involve any Payment Provider. 

The e-coins are designed in such a manner that 

the identity of the owner is not shown unless the owner 

uses one MONETA coin more than once. In order to 

provide this functionality, approaches from Brands 

and Neumann/Baumgart were investigated and adapted. 

The MONETA micro payment scheme uses 

Elliptic Curve Cryptography (ECC). Together with 

lesswire AG we presented the implementation of 

MONETA and PLASMA at CeBIT 2005. The information 

about the performance of this demonstrator is shown 

in Table 1. 

To improve the performance of both approaches mentioned 

above, our AES (Advanced Encryption Standard) 

and ECC hardware accelerators may be used. 

They were also developed as part of the project Mobile 

Business Engine. 

Seconds 

3.0 

2.5 

2.0 

1.5 

1.0 

0.5 

0 

accepted 

not accepted 

PDA WLAN PDA WLAN PC LAN 

(~ 45 % Signal) (~ 70 % Signal) (100 Mbit) 

Abb. 1: Messergebnisse erfolgreicher und erfolgloser Verhandlungen 

bei drahtlosen und drahtgebundenen LAN-Verbindungen. 

Fig. 1: Measurement results of successful and unsuccessful 

negotiations via WLAN and fixed LAN connections.

BASUMA − Body Area System for Ubiquitious 

Multimedia Communication 

Drahtlose Sensornetzwerke (WSN) sind sowohl durch 

ihr wirtschaftliches als auch durch ihr technologisches 

Potential ein vielbeachtetes Feld der gegenwärtigen 

Forschung. Sie müssen typischer Weise längere Zeit 

ohne Wartung fehlerfrei funktionieren. Anwendungen 

und auch Kommunikationsprotokolle für WSNs werden 

durch den immer vielschichtigeren Einsatz komplexer. 

Es ist deshalb notwendig, energieeffiziente, kleine 

drahtlose Sensorknotenmodule zu entwickeln, die 

trotzdem zuverlässig arbeiten. 

BASUMA ist ein Forschungsprojekt, das sich genau mit 

diesen Fragestellungen beschäftigt. Sein Ziel ist es, 

eine Plattform für ein drahtloses, körpernahes Funknetzwerk 

(BAN) zu entwickeln. Die Plattform besteht 

sowohl aus Hardware- als auch aus Software-Komponenten, 

die speziell für kleine, verbrauchsarme Systeme 

entwickelt werden. 

Die sich aus einer solchen Technologie ergebenden 

Möglichkeiten sollen beispielhaft in einer telemedizi- 

nischen Anwendung demonstriert werden. Dabei werden 

einige batteriebetriebene Sensoren verschiedene 

Bioparameter des menschlichen Körpers wie EKG, 

Puls, Temperatur oder Sauerstoffgehalt des Blutes 

aufnehmen. Ein solches BAN eignet sich hervorragend 

zur medizinischen Überwachung von chronischkranken 

Patienten. Die aufgezeichneten medizinischen Parameter 

werden lokal ausgewertet und nur im Bedarfsfall 

zum Arzt übertragen. 

Die Fortschritte im System-on-Chip-Entwurf und -Fertigung 

(SoC) ermöglichen jetzt die Entwicklung von 

LEON2 

proc. 

AHB 

Controller 

Protocol 

Accelerator 

Memory 

Controller 

Abb. 2: Blockdiagram der BASUMA-Hardware-Plattform. 

Memory Bus 






BASUMA − Body Area System for Ubi- 

quitious Multimedia Communication 

Wireless sensor networks (WSN) have attracted much 

research efforts in recent years. Typical WSN applications 

target several months or years of unsupervised 

operation. Applications as well as communication protocols 

for WSNs are becoming increasingly complex 

as the processing capabilities of sensor nodes grow. 

There is a strong need for reliable, energy-efficient 

software and hardware when WSNs shall become economically 

successful. 

BASUMA is a research project started in 2004 that has 

the objective to develop a platform for wireless communication 

around the human body. This platform will 

consist of hardware and software components that are 

specifically designed for small, low-power devices. 

The capabilities of the BASUMA platform are to be demonstrated 

with a medical application. A number of 

battery-powered sensor nodes measuring various bioparameters, 

such as heart rate, temperature, or ECG 

are attached to the human body and form a wireless 

network. This body area (sensor) network (BAN) forms 

the basis for long-term monitoring of chronically ill patients. 

The signals measured by the sensor nodes are 

locally analyzed and the evaluation within a medical 

center is only initiated when necessary. 

Advances in System-on-Chip (SoC) design and wireless 

communication technology enable the development 

of tiny, autarkic running sensor nodes that can 

be worn on the human body. As shown in Fig. 2 we follow 

a modular concept, which is going to be integrated 

in a SoC. 

IrqCtrl 

I/O port 

PROM SRAM 

Baseband 

Processing 

Timers 

UARTS 

APB 

AHB 

RF 

Frontend 

AHB/APB 

Bridge 

Fig. 2: Block diagram of the BASUMA hardware platform. 

31



32 



kleinen, autarken Sensorknoten. Wie in Abb. 2 zu sehen 

ist, verwenden wir ein modulares Plattformdesign, 

wobei alle Module auf einem einzigen Chip integriert 

werden. 

Die Energieeffizienz der Hardwareplattform wird durch 

Hardwarebeschleuniger erreicht, die besonders zeit- 

und energiekritische Teile der Signalverarbeitung, der 

Kommunikationsprotokolle und allgemein verwendeter 

Funktionen als Hardware realisieren. Beispielsweise 

wurde gezeigt, dass eine Hardware-CRC-Generierung 

(Cyclic Redundancy Check) 238 mal schneller ausgeführt 

wird als eine vergleichbare Softwareimplementierung, 

die auf einem 50- MHz-LEON2-Prozessor läuft. 

Um die Zeitvorgaben des Kommunikationsprotokolls 

zu treffen, müsste eine CRC-Softwareimplementierung 

auf einen mit 704 MHz getakteten LEON2-Prozessor 

ausgeführt werden. Die Hardwareimplementierung benötigt 

einen Takt von lediglich 2,9 MHz. Da der Stromverbrauch 

proportional zur Taktfrequenz ist, kann man 

von einer beträchtlichen Energieersparnis ausgehen. 

Des Weiteren wird ein Energiemanagement-Modul entwickelt, 

das vor allem die Leckströme in den Phasen 

mit Inaktivität reduziert, in denen weder Sensormessungen 

noch Kommunikation stattfinden. Abb. 3 zeigt 

für unterschiedliche Aktivitäts/Ruhe-Verhältnise deutlich, 

dass der Energieverbrauch durch Leckströme einen 

Anteil von bis zu 90 % erreichen kann. 

Zu den methodischen Arbeiten in diesem Projekt gehört 

die Entwicklung eines Werkzeugs, das eine automatische 

Transformation von quasiformalen SDL-Kommunikationsprotokoll-Spezifikationen 

in eine effiziente 

Implementierung erlaubt. Das ist insofern von Bedeutung, 

als hierdurch die Fehleranfälligkeit und der 

Zeitaufwand für die Implementierung des validierten 

SDL-Modells erheblich verbessert und trotzdem eine 

gewisse Effizienz erreicht wird. Tabelle 2 zeigt die Verbesserung 

gegenüber dem Standardtool für SDL-Spezifikationen, 

Telelogic TAU RTE. 

Number of Signals IHP Approach Telelogic TAU RTE 

1000 0.050 s 0.120 s 

3000 0.140 s 0.360 s 

8000 0.400 s 0.980 s 

Tabelle 2: Zeitdauer für den Austausch von Signalen zwischen zwei 

Prozessen. 

Table 2: Exchange time for signals between two processes. 


We use hardware accelerators to achieve a high energy-efficiency 

of the hardware platform. These accelerators 

perform otherwise time and energy-consuming 

tasks. For example, we have shown that a hardware 

implementation of a CRC (Cyclic Redundancy Check) 

is 238 times as fast as an equivalent software implementation 

running on a 50 MHz LEON2 processor. To 

perform the CRC computation in the time limits given 

by the communication protocol, the LEON2 processor 

would have to run at 704 MHz, whereas the hardware 

implementation needs only 2.9 MHz. The energy consumption 

is directly proportional to the clock speed, 

corroborating the assumption of a high energy reduction 

potential of this approach. Furthermore, we develop 

an energy management module to reduce the 

leakage power consumed during inactive phases of 

the sensor node platform, which occur if there are no 

sensor measurements or sensor node communication. 

Fig. 3 shows for different duty cycles that the leakage 

energy can have a share of 90 % of the overall energy 

consumption. 

In this project we also developed a method that automatically 

transforms a formal SDL specification of a 

communication protocol into an efficient implementation. 

The importance of this approach can be found in 

an improvement of the system robustness and reduction 

of the implementation time of formally specified 

and validated protocols. Moreover, we achieve a much 

better efficiency. Table 2 demonstrates the improvement 

compared to the standard tool for SDL-Specifications, 

Telelogic TAU RTE. 

Leakage Loss (%) 

100 

90 

80 

70 

60 

50 

40 

30 

20 

10 

0 

Leakage Power 

Contribution 

20 10 1 0.1 

Duty Esleep/Etotal Cycle (%) 

(%) 

Abb. 3: Leckleistungsverlust vs. Aktivitäts/Ruhe-Verhältnis. 

Fig. 3: Leakage loss vs. duty cycle. 

1 % 

0.2 % 

0.1 % 

0.01 % 

0.02 %

WIGWAM − Wireless Gigabit with 

Advanced Multimedia Support 

Ziel des IHP im Rahmen dieses Verbundprojektes ist 

es, ein im 60-GHz-Band arbeitendes Höchstgeschwindigkeits-Kommunikationssystem 

mit Datenraten oberhalb 

von 1 Gbps zu entwerfen und prototypisch zu implementieren. 

Die wesentlichen Beiträge des IHP sind 

die Entwicklung des analogen Frontends (AFE), des 

Basisbandprozessors (BB) und des Medium Access 

Control Prozessors (MAC). Die Funktionsweise des 

Systems soll mit Hilfe eines Demonstrators nachgewiesen 

werden. 

Der Basisbandteil im Sender ist primär für die Kodierung 

und digitale Modulation der Nachrichten und damit 

verbundene Signalformung des IQ-Sendestromes 

verantwortlich. Im Empfänger wird das ankommende 

Nachrichtensignal analysiert, demoduliert und dekodiert. 

Hierfür muss das Empfangssignal mit ausreichender 

Genauigkeit synchronisiert werden. Im Laufe 

des Projektes wurde ein MATLAB-Simulationsmodell 

entwickelt, welches nicht nur den Basisbandteil abbildet, 

sondern auch Störeinflüsse des analogen Frontends 

sowie den Einfluss der Übertragungsstrecke 

modelliert. Algorithmen zur Synchronisation und Kanalschätzung 

sind mit Hilfe dieses Modells erfolgreich 

getestet worden. Die funktionalen Blöcke der Basis- 

Interpolation 

Filter 

IFFT 

Encoder 

Encoder 

Encoder 

SP 

APC 

D/A 

Mapper 

Buffler, 

Central Control 

Interleaver 

Interleaver 

Interleaver 

AFE 

Abb. 4: Architektur des OFDM Basisbandprozessors. 

CRC 

CRC 

CRC 

Viterbidecoder 



Interleaver 

Interleaver 

Interleaver 





WIGWAM − Wireless Gigabit with 

Advanced Multimedia Support 

The goal of the IHP in this cooperative project is to develop 

an ultra-high-speed communication system with 

data rates beyond 1 Gbps, operating in the 60 GHz 

band. Developing and implementing the analog frontend 

(AFE), the baseband processor (BB) and a highthroughput 

medium access control processor (MAC) 

are the main contributions of IHP. The operation of the 

system will be verified by a demonstrator. 

The baseband part in the transmitter is primarily responsible 

for coding and digital modulation of the information 

stream forming the IQ baseband signal. In 

the receiver, the signal is analysed, demodulated and 

decoded. For the receiver to work accurately, precise 

synchronization is mandatory. During the project, a 

MATLAB model has been developed for the simulation 

of the baseband processor. Impairments of the analog 

frontend and the radio channel are included in this 

model. Synchronization and channel estimation has 

been tested successfully using the simulation model. 

The functional blocks are realized as VHDL blocks and 

mapped on a commercial FPGA platform. The major 

blocks have been successfully realized: Fast Fourier 

Transformation (FFT), Viterbi decoder, interpolation filter 

and decimation filter, interleaver and deinterleaver. 

Deinterleaver 

Deinterleaver 

Mapper 

P/S Demapper 

Deinterleaver 

J A H R E S B E R I C H T 2 0 0 5 | I H P A N N U A L R E P O R T 33 

AFE 

FFT 

AGC 

D/A 

Channel 

estimation 

& correction 

Phase 

correction 

Buffer 

Fig. 4: Architecture of the OFDM baseband processor. 

Decimation 

Filter 

Buffer 

coarse SYNC 

FINE SYNC



34 



bandverarbeitung werden auf einer kommerziellen 

FPGA-Plattform mit synthetisierten VHDL-Modulen realisiert. 

Die wesentlichen Module sind bereits erfolgreich 

implementiert worden. Dazu gehören eine schnelle 

Fouriertransformation (FFT), ein Viterbi-Dekoder, Interpolations- 

und Dezimationsfilter sowie Interleaver und 

Deinterleaver. Neben der Entwicklung des OFDM-Basisbandprozessors 

wurden auch geeignete Parameter der 

physikalischen Schicht (PHY) spezifiziert und für den 

Übertragungskanal optimiert. In Abb. 4 ist die Architektur 

des Basisbandprozessors dargestellt. 

Die 60-GHz-Empfänger- und Senderchips wandeln das 

60-GHz-Signal in ein Zwischenfrequenzsignal (ZF) von 

etwa 5 GHz bzw. umgekehrt. Dies erfordert einen frequenzstabilen 

Lokaloszillator bei etwa 55 GHz. Wir haben 

diese Anforderung dadurch gelöst, dass wir eine 

Phase-locked Loop (PLL) zusammen mit einem rauscharmen 

Verstärker und einem Gilbert-Mischer auf demselben 

Chip integriert haben. Abb. 5 zeigt das Layout und 

die Konversions-Verstärkung des Empfänger-Chips. 

LNA mixer 

PLL 

Die Umwandlung des ZF-Signals in das Basisband und 

umgekehrt erfordert einen Empfänger- und einen Senderchip 

ähnlich zu einem 802.11a-Frequenzkonverter. 

Diese Chips wurden unter Benutzung eines 5-GHz- 

Quadratursignals, abgeleitet aus einem 10-GHz-VCO 

durch Frequenzteilung in Verbindung mit einem Einseitenbandmischer 

und einem regelbaren Verstärker 


The 60 GHz broadband transmission is based on OFDM 

as the basic modulation technique. Besides the development 

of the baseband processor, the main para- 

meters of the physical layer (PHY) have been specified, 

and some optimizations have been applied. In 

Fig. 4, an overview of the baseband architecture is 

given. 

The 60 GHz receiver and transceiver chips convert 

the 60 GHz signal to an intermediate frequency (IF) of 

about 5 GHz or vice versa, respectively. This requires 

a stable local oscillator frequency around 55 GHz. We 

have realized this requirement by using a phase-locked 

loop (PLL), which has been integrated with a low-noise 

amplifier (LNA) and a Gilbert mixer on the same chip. 

Fig. 5 shows the layout and the measured conversion 

gain of the receiver chip. 

The conversion of the IF signal to baseband and vice 

versa requires a receiver and transceiver chip similar 

to an 802.11a direct down-converter and direct upconverter. 

These chips have been implemented using 

Conversion Gain (dB) 

35 

25 

Measurement 

Simulation 

15 

56 58 60 62 64 66 

RF Frequency (GHz) 

Abb. 5: Vollintegrierter 60-GHz-Empfänger-Chip (Layout und Konversions-Verstärkung). 

Fig. 5: Fully integrated 60 GHz receiver chip (layout and conversion 

gain). 

an integrated quadrature 5 GHz signal derived from a 

10 GHz VCO by frequency division in conjunction with 

a single-sideband mixer and a variable-gain amplifier. 

The IF chips were successfully tested. They provide 

a sideband-rejection of 38 dB over a wide frequency 

range. Fig. 6 shows the output spectra of the receiver 

and the transmitter. 

IHP actively contributes to the emerging 60 GHz standard 

IEEE 802.15.3c.

ealisiert. Diese ZF-Chips wurden erfolgreich getestet 

und liefern eine Seitenbandunterdrückung von 38 

dB über einen weiten Frequenzbereich. Die Ausgangsspektren 

vom Empfänger und Sender sind in Abb. 6 

dargestellt. 

Durch das IHP wurden aktiv Beiträge zum entstehenden 

60-GHz-Standard IEEE 802.15.3c geleistet. 

Abb. 6: Ausgangsspektrum von Empfänger (links) und Sender 

(rechts). 

Fig. 6: Output spectrum of the receiver (left) and transmitter 

(right). 








36 



Integrierter Radar-Chip Integrated Radar Chip 

Ziel des Projektes ist es, integrierte Radar-Schaltungen 

zu entwickeln, die trotz der hohen Komplexität auf 

einem oder wenigen Chips integriert werden können. 

Radartechniken finden immer mehr Eingang in den 

Alltag einer modernen Gesellschaft. So funktionieren 

z. B. Alarmanlagen, automatische Sanitär-Systeme 

oder Tür-öffner auf der Grundlage von neuen Radar- 

Techniken. Auch im Bereich Sicherheitstechnik, beispielsweise 

in fahrerlosen U- und S-Bahn-Systemen 

und anderen automatisch betriebenen Anlagen, setzen 

sich Radarsysteme wegen ihrer großen Zuverlässigkeit 

und hohen Genauigkeit zunehmend durch. In 

privaten PKW werden im Jahre 2010 bis zu 10 Radarsysteme 

eingebaut sein. 

Diese Radarsysteme werden heute zum großen Teil auf 

der Basis von GaAs-Bauelementen mit vielen diskreten 

Bauteilen hergestellt. Mit der im IHP entwickelten SiGe- 

Technologie wird es möglich, die Radar-Schaltungen 

kostengünstiger und mit einem größeren Integrationsniveau 

zu realisieren. Die ultimative Lösung ist die Integration 

eines vollständigen Radar-Systems auf einem 

Chip. Nur die Antennen werden dann außerhalb des 

Chips angebracht. Für Anwendungen im 24-GHz-ISM- 

Bereich (reserviertes Frequenzband für Industrie, Wissenschaft 

und Medizin) wurden im IHP mehrere integrierte 

Schaltungen für industrielle Partner entwickelt. 

Daneben wurden auch vorausschauende Forschungen 

für weit in der Zukunft liegende Anwendungen berücksichtigt. 

Abb. 7 zeigt das Blockschaltbild eines integrierten 

Radarsystems. Es besteht aus einem Sendeteil und 

einem Empfangsteil. Beide Teile besitzen je einen 

24-GHz-Oszillator. Die beiden Oszillatoren sind über 

die Vctrl-Leitung synchronisiert, so dass sie exakt die 

gleiche Schwingfrequenz besitzen. Der Empfangsteil 

wurde als Prototyp in der SGB25VD-Technologie des 

IHP hergestellt und analysiert. Abb. 8 zeigt das Chip- 

Foto. Man erkennt, dass die Bond-Pads mit Lotkugeln 

versehen sind, die eine direkte Verbindung des Chips 

mit einer Leiterplatte gewährleisten. 

In Abb. 9 sind einige Messungen an dem integrierten 

Schaltkreis dargestellt. In dem linken Diagramm erkennt 

man den breiten Abstimmbereich des integrierten 

Oszillators, der von 22 GHz bis 25,8 GHz reicht. 


The goal of the project is the development of complex 

radar circuits integrated on a single chip or at most 

on a few chips. 

More and more, radar techniques are penetrating our 

everyday life. For example the working principle of 

alarm systems, automatic sanitary systems or door 

openers is based on new radar systems. Also in the 

security field, e.g. in driverless high-speed railroads 

and subway, radar systems will be installed. They will 

be used because of their inherent reliability and accuracy. 

Up to ten radar systems will be installed in private 

cars in the year 2010. 

Today many radar systems are produced by using 

GaAs devices with a huge number of discrete elements 

on the printed circuit board. With the SiGe technologies 

of the IHP it is possible to produce radar circuits 

more cost-effective and with a higher level of integration. 

The ultimate solution is the fully integrated radar 

system on a single chip. Only the antennas will be 

placed outside the chip. For applications in the 24 GHz 

ISM band (reserved frequency region for non-commercial 

use for industrial, scientific and medical purposes) 

the IHP developed several integrated circuits for 

industrial partners. Besides this, foresighted research 

works concerned with applications in the more distant 

future were considered. 

Fig. 7 shows the block schematic of an integrated radar-system. 

It consists of a transmitter part and a receive 

part. Both parts are comprised of a 24 GHz oscillator. 

The two oscillators are synchronized by the 

Vctrl line connecting the two chips. With this, the two 

oscillators possess exactly the same oscillation frequency. 

The receive part was fabricated and tested 

in the SGB25VD technology of the IHP. Fig. 8 shows 

the chip photo. On the bond pads we can see bumps 

for direct soldering of the chip to the printed circuit 

board. 

Fig. 9 shows some measurement results for the integrated 

circuit. In the left diagram, we can see the wide 

tuning range of the integrated oscillator from 22 GHz 

to 25.8 GHz. The other diagram shows the gain of the 

signal derived from the antenna as a function of the 

oscillator frequency. In this process, the receive-signal 

is down-converted to a much lower intermediate

In dem rechten Diagramm ist die Verstärkung des von der 

Antenne kommenden Signals in Abhängigkeit von der Oszillator-Frequenz 

dargestellt. Dabei wird in dem Mischer 

die Empfangsfrequenz auf eine niedrige Zwischen- 

Transmitter 

Abb. 7: Die Systemarchitektur des integrierten Radar-Chips. 

Fig. 7: The system architecture of the integrated radar chip. 

frequenz heruntergemischt. Das Verhältnis der an die 

50-Ohm-Last gelieferten Leistung zu der Leistung von 

der 24-GHz-Quelle bezeichnet man als Conversion- 

Gain. Man erkennt an dem flachen Frequenzverhalten, 

dass der Schaltkreis über einen breiten Frequenzbereich 

verwendbar ist. 

Frequency (GHz) 

oscillator 1 

Vctrl synchronisation 

Receiver MMIC 

oscillator 2 

IF signal 

26 

25 

24 

23 

22 

21 

0 

0.5 

amplifier 

1.0 

power amplifier 

V ctrl (V) 

mixer 

1.5 

LPF 

2.0 

2.5 

transmit 

antenna 

LNA receive 

antenna 

3.0 

3.5 

Abb. 9: Abstimmbereich und Verstärkung in Abhängigkeit von der 

Oszillatorfrequenz. 





frequency. The conversion gain of the receiver is the 

power delivered to a 50 Ohm load at the IF-port divided 

by the power from the 24 GHz RF-source. It can 

be seen that there is a very flat frequency response 

gnd 

RF input 

mixer 

filter 

Vctrl 

24 GHz 

oscillator 

gnd IF out 

gnd 

indicating the possible use of the front-end MMIC over 

a wide frequency range. 


gnd 

Vcc 

Abb. 8: Chip-Foto des Radar-Frontend (Flip-Chip vorbereitet). 

Fig. 8: Chip photo of the flip-chip ready integrated front-end. 

Gain (dB) 

10 

8 

6 

4 

2 

0 

22 23 24 25 26 

f LO (GHz) 

Fig. 9: Tuning range and gain as a function of LO frequency.

38 



Ultraschnelle A/D- und D/A-Wandler Ultra-Fast A/D and D/A Converters 

Analog-Digital-Wandler (ADC) und Digital-Analog-Wandler 

(DAC) bilden die Schnittstelle zwischen den zwei 

Welten der Signalverarbeitung, der analogen, in der 

die Signale in Zeit und Amplitude kontinuierlichen Werteverlauf 

haben und mit analogen Schaltungen wie Verstärkern 

und Filtern verarbeitet werden, und der digitalen, 

in der die Signale Ströme binärer Daten sind 

und mit Logikschaltungen, Prozessoren und Software 

verarbeitet werden. Wurden ADC und DAC früher vor 

allem in Messgeräten eingesetzt, verrichten sie heute 

in fast jedem elektronischen Gerät unauffällig ihre 

Dienste und vermitteln zwischen digitalen Systemen 

und analoger Umwelt. 

Zwei wesentliche Motive treiben die Anforderungen an 

die Geschwindigkeit von ADC und DAC immer weiter 

in die Höhe: Stetig wachsende Datenraten sowie die 

Verlagerung der A/D- und D/A-Schnittstellen elektronischer 

Systeme zu immer höheren Frequenzen. 

Basierend auf den hervorragenden Eigenschaften der 

SiGe-BiCMOS-Technologie des IHP zielt das ADC-DAC- 

Projekt am IHP auf den ultraschnellen Bereich weit jenseits 

von einer Milliarde Abtastungen (Giga-Samples) 

Analog 

Signal 

Abb. 10: Funktionsgruppen eines A/D-Wandlers. 




A/D and D/A converters (ADCs and DACs) are interfacing 

the two worlds of electronic signal processing. 

Having been used mainly in measurement technology 

in earlier years, they can be found now in most electronic 

devices. 

Two main reasons cause pressure of ADCs and DACs 

towards higher sampling rate: The continued growth 

of communication data rate and the ongoing shift of 

the A/D interface of electronic systems to higher radio 

frequencies. 

Based on the outstanding parameters of the SiGe 

BiCMOS technology of the IHP, the ADC-DAC project 

of the IHP is aimed at the ultra fast range well beyond 

one Gigasamples per second. Here, the IHP has 

some special advantages, e.g. the vertical research 

approach including expertise on various fields and the 

unique complementary technology providing pnp transistors 

with f max beyond 100 GHz. 

The medium-term goal is to achieve ADCs and DACs at 

8 bit resolution and 10 GSps sampling rate. This is five 

times faster than commercially available chips. 

Sampling Quantising Encoding 

Time domain 

quantisation 

- Discrete time: 

Track-and-Hold 

Amplifier (THA) 

- Critical for speed 

and accuracy 

Amplitude domain 

quantisation 

- Discrete amplitude: 

Various architectures 

depending on speed / resolution 

- Critical for chip area, power 

dissipation and accuracy 

Fig. 10: Functional blocks of an ADC. 

0 1 0 1 1 

1 0 1 0 1 

1 1 1 1 0 

Digital 

Data stream

pro Sekunde. SiGe-BiCMOS ist hier die Technologie 

der Wahl. Das IHP hat dabei einige besondere Vorteile, 

die u.a. in seiner vertikalen Forschungsausrichtung 

und der damit verbundenen viele Fachgebiete umfassenden 

Expertise liegen, und weil es weltweit die einzige 

komplementäre Technologie anbieten kann, die 

nicht nur npn-Transistoren, sondern auch pnp-Transistoren 

mit einer Frequenzgrenze f max von über 100 GHz 

bietet. 

Als mittelfristiges Ziel sollen ADC und DAC mit 8-Bit- 

Auflösung und 10 GSps Abtastrate erreicht werden, 

fünfmal schneller als auf dem Markt derzeit erhältlich. 

f sample 

(GHz) 

f in 

(GHz) 

Input 

(V pp ) 

ENOB 

(bit) 

BW 

(GHz) 

Supply 

Tabelle 3: Abtast- und Halteverstärker in SiGe (> 5 Bit, > 1 GSps). 

(V) 

Abb. 10 stellt dar, dass die Abtastrate bei einer gewünschten 

Genauigkeit von 6 Bit und mehr durch die 

Zeit-Quantisierung begrenzt wird. Ein geeigneter Abtast- 

und Halteverstärker (Track-and-Hold-Amplifier, 

THA) war deshalb das erste Ziel des ADC-DAC-Projekts 

des IHP. Innerhalb nur eines Jahres wurden dabei bereits 

Weltrekorde wie in Tabelle 3 dargestellt erreicht: 

Die höchsten Abtastraten in der Klasse ab 6 Bit erreichen 

die beiden THA des IHP (in den farbig hervorgehobenen 

Zeilen). Der eine, etwas genauere, wurde 

in Kooperation mit Prof. Cressler, Georgia Tech, USA, 

entwickelt, der andere, wesentlich stromsparendere, 

direkt am IHP. Normiert man den Energieverbrauch 

wie in der Formel in Abb. 11 angegeben, so sieht man, 

dass der stromsparende THA des IHP bei weitem der 

effektivste ist. Dies ist ein wichtiger Vorteil, wenn mehrere 

ADC auf einem Chip untergebracht werden sollen, 

oder in mobilen Anwendungen. 

Wird hohe Linearität eines THA bei hoher Geschwindigkeit 

und gleichzeitig großer Signalamplitude gefor- 





Fig. 10 shows that the sampling rate is limited by the 

Track-and-Hold-Amplifier (THA) at six and more bits 

of accuracy. Therefore the first focus was set on designing 

appropriate THAs. As shown in Table 3, world 

records have been achieved within the first project 

year: The IHP THAs have the highest sampling rate 

in the >5 bits class. The upper one of the IHP THAs 

is more accurate. It results from a co-operation with 

Prof. Cressler, Georgia Tech, USA. The lower one has 

been designed directly at the IHP. It is the most effective 

THA in terms of normalized power consumption, 

as shown in Fig. 11, which is important for interleaved 

ADCs or mobile applications. 

Pdiss 

(W) 

Process / f T 

(GHz) 

Author 

2 0.9 0.8 8 0.9 -3.3 0.55 SiGe/65 Vessal, Salama 2004 

4 8 0.6 6 10 5.2 0.55 SiGe/45 Jensen, Larson 2000 

12.1 1.5 1 8 5.5 3.5 0.7 SiGe/200 IHP Lu et al. 2005 

10 1 1 6.8 2.7 3.3 0.03 SiGe/200 IHP Borokhovych et al., 2005 

IHP Lu et al., 2005 IHP Borokhovych et al., 2005 

Table 3: Track-and-Hold-Amplifiers in SiGe technology (> 5 bit, 

> 1 GSps). 

FOM (pJ) 

2.5 

2.0 

1.5 

1.0 

0.5 

0 

Vessal 

P diss 

FOM = 2·2 ENOB ·ERBW 

Jensen 

IHP 

Lu et al. 

IHP 

Borokh. 

Abb. 11: Abtast- und Halteverstärker im Vergleich des normierten 

Energieverbrauchs. 

Fig. 11: Track-and-Hold-Amplifiers with normalized power 

dissipation. 


dert, dann stoßen die bisherigen THA-Schaltungen an 

ihre Grenzen. Ein Ausweg ist, den THA ausschließlich 

aus Emitterfolgern aufzubauen, die sehr gute Linearität 

aufweisen. Hierzu benötigt man neue THA-Schaltungen 

mit schnellen pnp-Transistoren, (Q1 und Q2 in 

Abb. 12). Wie die Grafik in Abb. 13 zeigt, ist ein solcher 

aus komplementären Emitterfolgern aufgebauter 

THA ab etwa 1 V Signalamplitude der üblichen npn-Differenzstufe 

hinsichtlich der Verzerrungen, die von der 

dritten Harmonischen der Grundwelle dominiert werden, 

überlegen. 

Das kleine Team des ADC-DAC-Projekts am IHP ist optimistisch, 

dass auch die anderen Funktionsblöcke für 

ultraschnelle ADC und DAC mit Weltrekordparametern 

erreicht werden. Nächste Ziele sind ADC von 3- bis 4-Bit- 

Auflösung mit sehr geringer Verlustleistung bei 10 bis 

20 GSps, wie sie für drahtlose Kommunikation im Ultra-Wide-Band-Bereich 

gebraucht werden, D/A-Wandler 

bei 10 GSps sowie schließlich ADC bei 10 GSps und 

8-Bit-Auflösung. 

40 



Abb. 12: Neuer komplementärer Abtast- und Halteverstärker. 


If high THA linearity is required at both high speed and 

large signal amplitude, then the common state of the 

art of THAs is at its limits. One solution is to build the 

THA completely from emitter followers, requiring very 

fast pnp transistors (Q1 and Q2 in Fig. 12). In Fig. 13 

it can be seen that this new type of THA is superior in 

linearity beyond 1 Volt of signal amplitude. 

Input buffer SEF1 SEF2 

Input buffer 

R1 

Level shifter 


C ff 

Inp Inn 

I 


C H 

T Q4 Q5 T 

T Q7 Q8 H 

C H 

C ff 

Q3 Q6 

Q1 Q2 

Abb. 13: Nichtlinearität des komplementären Emitterfolgers im 

Vergleich zur üblichen Differenzstufe. 

Fig. 13: Nonlinearity of the complementary emitter follower versus 

common differential stage. 

I 

The small ADC-DAC project team at the IHP is convinced 

that the other blocks of an ultra-fast ADC can 

also be designed at world record level. Next goals are 

low-power ADCs at 3-4 bits (needed for Ultra-Wide- 

Band communication), DACs at 10 GSps and eventually 

ADCs at 10 GSps and 8 bits resolution. 

R2 

Level shifter 

Fig. 12: New complementary Track-and-Hold-Amplifier. 

3rd Harmonic (dBc) 

-30 

-40 

-50 

-60 

-70 

-80 

-90 

pnp-npn EF 

npn diff amp 

0.2 0.4 0.6Input 

0.8 1.0 (Vpp) 1.2 1.4 1.6 1.8 2.0 

Input (Vpp)

Technologieplattform/ 

Technology Platform 

SiGe-BiCMOS-Technologie für 

77/79 GHz Auto-Radar 

(Projekt KOKON) 

Im Rahmen des BMBF-Verbundprojektes KOKON werden 

spannungsgesteuerte Oszillatoren (VCO) mit Leistungsverstärkern 

für 77/79 GHz Radarsignalgeneratoren in 

der SiGe-BiCMOS-Technologie des IHP entwickelt. 

Radarsysteme in modernen Autos erhöhen sowohl die 

Sicherheit (Stop-and-go-Funktion, Kollisionswarnung), 

als auch den Fahrkomfort (Parkhilfe). Leider sind heutige 

Systeme entweder sehr teuer oder wie das kürzlich 

eingeführte 24-GHz-System aus frequenzregulatorischen 

Gründen nur Interimslösungen (in der EU 

zu ersetzen ab 2013). Eine sinnvolle Alternative sind 

Schaltungen in SiGe-Technologie für die zwei Radarvarianten: 

• 77-GHz-Weitbereichsradar 

• 79 +/- 2-GHz-Ultra-Weitband-Nahbereichsradar 

Die anspruchsvollen Anforderungen der Automobilindustrie 

betreffen dabei nicht nur die technischen Parameter 

(hohe Ausgangsleistung), sondern insbesondere 

die Zuverlässigkeit der Systeme von -40 °C bis 

125 °C. 

Im Rahmen des Projektes soll nicht nur geprüft werden, 

ob die mit den Automobilzulieferern vereinbarten 

Spezifikationen erreicht werden. Wesentlich sind auch 

der Vergleich mit einer alternativen Technologieplattform 

(Infineon SiGe-Bipolar-Technologie) und die Untersuchung 

von Temperaturstabilität und Zuverlässigkeit 

der Halbleiterbauelemente und Schaltungen. 

Für die Technologie SG25H1 des IHP werden spannungsgesteuerte 

Oszillatoren entworfen, die sich an 

den Spezifikationen des Projektes orientieren. Die bisherigen 

differentiellen Schaltungen liefern Ausgangsleistungen 

bis zu +4 dBm (3 mW) und zusammen mit 

einem einstufigen Leistungsverstärker (Abb. 14) werden 

bis zu +9 dBm (9 mW) erreicht. 

Die Anforderungen der Automobilindustrie bezüglich 

Temperaturstabilität und Zuverlässigkeit verlangen 

einen großen Aussteuerbereich des VCO von 10 GHz 


Technologieplattform 

SiGe BiCMOS Technology for 

77/79 GHz Automotive Radar 

(KOKON Project) 



Within the framework of the BMBF funded project 

KOKON (“cocoon”) the IHP is going to develop voltage 

controlled oscillators (VCO) with power amplifier 

for 77/79 GHz radar signal generators within its SiGe 

BiCMOS technology. 

Radar sensors in modern cars enhance safety (“stopand-go” 

function, collision warning) and comfort (parking 

aid). Unfortunately, today’s systems are either 

very expensive or like the 24 GHz system just interim 

solutions (in the EU to be replaced from 2013). Promising 

alternative solutions are circuits in SiGe technology 

for two radar variants: 

• 77 GHz long range radar 

• 79 +/- 2 GHz short range ultra-wideband radar 

The challenging demands of the automotive industry do 

not just affect technical parameter (high output power) 

but also system reliability from -40 °C up to 125 °C. 

Besides meeting the specifications defined in the project 

the main target is the comparison of different technological 

platforms (IHP to Infineon’s SiGe bipolar process) 

and the investigation of temperature stability and 

reliability. 

Voltage controlled oscillators were designed for IHP’s 

SG25H1 technology according to the specifications of 

the project. Present differential circuits deliver output 

powers up to +4 dBm (3 mW) and combined with a single 

stage buffer up to +9 dBm (9 mW) (Fig. 14). 

The automotive suppliers demand sufficient temperature 

stability and reliability. For this a large tuning range 

of 10 GHz and low change of oscillator frequency 

and output power up to 125 °C are required. Fig. 15 

shows the oscillator characteristics with a tuning range 

of 9 GHz and an oscillator frequency drift of only 

-2 GHz per 100 K. These results were received mainly 

by the combination of SiGe HBT and the nMOS varactors 

of the CMOS module. 


zw. geringe Änderung der Oszillatorfrequenz und 

Ausgangsleistung bis 125 °C. Abb. 15 zeigt die Kennlinie 

eines IHP-VCO mit einem Aussteuerbereich von 

9 GHz und einer Drift der Oszillatorfrequenz von nur 

etwa -2 GHz/100 K Diese Werte konnten vor allem 

durch die Kombination von SiGe-HBT mit den nMOS- 

Varaktoren des CMOS-Moduls erreicht werden. 

42 





Abb. 14: Spannungsgesteuerter Oszillator mit einstufigem 

Leistungsverstärker für 77/79-GHz-Radarsignalgeneratoren. 

Fig. 14: Voltage controlled oscillator with power amplifier for 

77/79 GHz radar signal generators. 

Oscillator Frequency (GHz) 

78 

77 

76 

75 

74 

73 

72 

71 

70 

69 


2 

4 6 

Control Voltage (V) 

Abb. 15: Kennlinie eines VCO mit einem Aussteuerbereich von 9 GHz. 

Fig. 15: Characteristics of a VCO showing a tuning range of 9 GHz. 

8

0,13-µm-BiCMOS-Technologie 

Das IHP hat 2005 die Entwicklung einer 0,13-µm-SiGe- 

BiCMOS-Technologie begonnen. Diese Technologie 

zielt auf die Realisierung integrierter Kommunikations- 

systeme auf einem Siliziumchip (System-on-Chip) für 

höchste Datenraten und höchste Übertragungsfrequenzen. 

Der 0,13-µm-BiCMOS-Prozess wird die nächste 

Technologiegeneration für den Prototyping-Service des 

IHP und die Plattform für die Erforschung neuer Bauelemente-, 

Schaltungs- und Systemkonzepte sein. 

Skalierte CMOS-Technologien erlauben die Realisierung 

einer steigenden Anzahl von Schaltungsfunktionen im 

Hochfrequenzbereich. Für viele Anwendungen im mm- 

Wellenbereich und für Kommunikationssysteme mit 

großer Bandbreite bleiben jedoch Hochgeschwindigkeits-HBTs 

wegen ihrer größeren Spannungsfestigkeit, 

ihres großen Ausgangswiderstandes, ihres geringen 

1/f-Rauschens und der großen Zahl erprobter Schaltungskonzepte 

unverzichtbar. HBTs mit verbesserten 

Hochfrequenzeigenschaften sind der Schlüssel für 

neue Anwendungen wie drahtlose Kommunikation im 

60-GHz-Band mit Datenraten oberhalb 1 Gbps, lichtlei- 

terbasierte Kommunikationssysteme mit Datenraten 

oberhalb 40 Gbps und automobile Radarsysteme bei 

77 GHz. 

In der ersten Phase des Projektes wurden die Prozessmodule 

für Herstellung von Strukturen mit Abmessungen 

von 0,13 µm entwickelt. 

Heterobipolar- und MOS-Transistoren mit 0,13-µm-Design-regeln 

wurden hergestellt. CMOS-Transistoren 

mit Gateoxiddicken von 2,0 nm und 7,0 nm werden 

für digitale und analoge Anwendungen bei 1,2 V und 

1,5 V sowie für Ein- und Ausgangsschaltungen bei 

3,3 V entwickelt. Abb. 16 zeigt eine Speicherzelle in 

der Draufsicht. Typische Transferkennlinien von nMOS- 

und pMOS-Transistoren mit 0,13 µm Gatelängen sind 

in Abb. 17 gezeigt. Für Schaltungsanwendungen im 

oberen GHz-Bereich werden SiGe-HBTs mit Grenzfrequenzen 

f T und f max größer 250 GHz bereitgestellt. Konzepte 

für die Integration von LDMOS-Transistoren für 

Anwendungen bei Spannungen bis zu 12 V (Abb. 18) 

wurden demonstriert. 



0.13 µm BiCMOS Technology 



The IHP started the development of a 0.13 µm BiC- 

MOS technology in 2005. This technology targets 

system-on-a-chip solutions (SoC) for wireless and 

broadband communications at highest data rates 

and highest transmission frequencies. The 0.13 µm 

BiCMOS process will be the next technology generation 

for the IHP foundry service and a research platform 

for new device, circuit, and system concepts. 

Scaled CMOS technologies can facilitate the implementation 

of an increasing number of radio-frequency 

(RF) functions. However, high-speed HBTs remain 

indispensable for many mm-wave applications and 

high-bandwidth communication systems due to their 

high voltage capability, high output resistance, low 

1/f noise, and the large number of proven RF circuit 

concepts. HBTs with improved RF-performance are 

a key for new applications such as wireless links in 

the 60 GHz band with data rates above 1 Gbps, fiber 

optics communication systems with data rates above 

40 Gbps, and automotive radar at 77 GHz. 

In the first stage of the project, we have developed 

process modules for the fabrication of structures with 

0.13 µm dimensions. 

Abb. 16: Draufsicht eines SRAM-Speichers nach der Strukturierung der 

Transistorgates. 

Fig. 16: Top view of an SRAM after gate structuring. 


44 



Drain Current (A/µm) 

n-LDMOS 

p+ n+ n 

p 

10 -3 

10 -4 

10 -5 

10 -6 

10 -7 

10 -8 

10 -9 

10 -10 

10 

-1.2 

-11 

V d =-0.05 V 

pMOS 

-0.9 -0.6 

V d =-1.2 V V d =1.2 V 

-0.3 

Gate Voltage (V) 

p-LDD 

N-LDD 

p-Substrate 

0.3 

0.6 

Abb. 18: Schematischer Querschnitt von n- und p-Typ 

LDMOS Transistoren. 

Fig. 18: Schematic cross section of n- and p-type 

LDMOS transistors. 

0 

V d =0.05 V 

nMOS 

Abb. 17: Transferkennlinien von 0,13 µm nMOS- und 

pMOS-Transistoren. 

Fig. 17: Transfer characteristics of 0.13 µm nMOS and 

pMOS transistors. 



0.9 

1.2 


Heterojunction bipolar transistors and MOS transistors 

with 0.13 µm design rules were fabricated. CMOS 

transistors with gate oxide thicknesses of 2.0 nm and 

7.0 nm are being developed for digital and analog 

applications at 1.2 V and 1.5 V and for input/output 

circuits at 3.3 V, respectively. Fig. 16 shows a top 

view of a SRAM cell. Typical transfer characteristics 

of nMOS and pMOS devices with 0.13 µm gate lengths 

are shown in Fig. 17. SiGe HBTs with f T and f max values 

above 250 GHz will be provided for circuit applications 

in the higher GHz range. Integration concepts for 

LDMOS transistors (Fig. 18) for operating voltages up 

to 12 V have been demonstrated. 

p-LDMOS 

n+ p+ p+ 

n 

n-LDD 

p-LDD 

n-Buried Layer

Integration nichtflüchtiger 

Speicher in SiGe-BiCMOS 

Das Ziel dieses Projektes ist die Demonstration einer 

kostengünstigen Prozesstechnologie zur Integration 

eines verlustleistungsarmen „embedded-Flash“ Halbleiterspeichers 

in einen leistungsfähigen 0,25-µm-SiGe- 

HF-BiCMOS-Prozess. 

Eine modulare Technologie für nichtflüchtige Speicher, 

eingebettet in einen SiGe-HF-BiCMOS-Prozess, bietet 

herausragende Möglichkeiten für eine Reihe wichtiger 

Anwendungen auf Systemebene. Die meisten Silizium-Foundries 

bieten heute „embedded-Flash“ Optionen 

für ihre (HF-)CMOS-Prozesse an. Für SiGe basierte 

BiCMOS-Prozesse ist diese Kombination eine konsequente 

Weiterentwicklung, die aber noch nicht etabliert 

ist. Herausforderungen sind geringe Kosten und 

geringer Leistungsverbrauch, insbesondere zur Verwendung 

in Systemen der Mobilkommunikation. Es 

werden Speicher kleiner bis mittlerer Dichte benötigt 

(von einigen Byte, z.B. für nichtflüchtige Register, bis 

zu einigen Mbit, z.B. zur Speicherung von Betriebssystemen. 

Insgesamt liegen die Vorteile eines solchen integrierten 

Speichers in der zusätzlichen Systemfunktionalität 

und reduzierten Systemkosten. 

Shallow Trench Isolation 

High energy P-implant 

nMOS, pMOS wells 

5nm CMOS Gate-oxide 

Gate poly deposition 

1-Mask HBT-Module 

Gate structuring 

S/D implants 

Backend processing 

Abb. 19: Prinzipieller Prozessablauf. 

Fig. 19: Principle process flow. 

Dual-gate-oxide wet 

etch (Mask 1) 

Floating-gate and 

Flash-PWELL implant 

(Mask 2) 

Floating-gate etching 

and HV-NWELL implant 

(Mask 3) 

Control-gate etching 

and HV n-LDD implant 

(Mask 4) 



Integration of Non-Volatile 

Memory in SiGe BiCMOS 



A modular non-volatile-memory-technology, embed- 

ded into a SiGe RF-BiCMOS process, has significant 

potential for a range of important systemlevel applications. 

Most Si-foundries offer optional embedded flash 

modules in their CMOS or RF-CMOS processes. 

For SiGe BiCMOS this is a consequential development, 

but which is not yet established. Main requirements 

are cost-effectiveness and low power consumption, 

particularly for use in mobile communication systems. 

Memories are needed ranging from small to medium 

density (from a few byte, e.g. for non-volatile registers, 

up to a few Mbit, e.g. for operation system storage). 

Cell size and performance must be sufficient for 

these memory sizes. The overall advantages of such 

embedded memory integration are the added system 

functionality and a reduced total system cost. 

A process technology has been developed to integrate 

an embedded flash memory into IHP’s 0.25 µm SiGe 

RF-SoC technology platform. For CMOS compatibility 

a standard floating-gate approach was chosen. Fowler- 

Nordheim tunneling is used as cell-programming mechanism 

due to its intrinsic low power consumption. 

The principle process flow is shown in Fig. 19. The developed 

integration scheme needs four additional mask 

steps on top of the baseline BiCMOS flow to produce 

flash cells and high-voltage devices needed in the 

memory`s periphery. A first 1 Mbit demonstrator memory 

has already been developed in 2004 (Fig. 20), showing 

the feasibility of the technology for these memory 

densities. In 2005 the work was focused on further optimizing 

the process flow and individual steps, especially 

with respect to realize a memory based on 2-transistor 

cells (Fig. 21). These cells have an advantage for both, 

memory performance and reliability. 

A comparison of HBTs and CMOS transistors of the 

BiCMOS process with and without the additional process 

steps of the flash memory fabrication demonstrates 

the modular character of the integration concept. 

The yield of 4k-HBT arrays (Fig. 22) as well as the 

threshold voltage of nMOS and pMOS devices (Fig. 23) 

do not show any degradation due to the embedded 

flash memory integration. 




Es ist eine Prozesstechnologie zur Integration eines 

„embedded-Flash“ Speichers in die 0,25-µm-SiGe-HF 

SoC-Technologieplattform des IHP entwickelt worden. 

Aufgrund seiner CMOS-Kompatibilität wurde ein Standard-„Floating-gate“-Ansatz 

gewählt. Der Mechanismus 

zur Programmierung der Zelle basiert auf leistungsarmem 

Fowler-Nordheim-Tunneln. 

Der prinzipielle Prozessablauf zur Herstellung der Speicherzellen 

und für den Betrieb benötigter Hochvolttransistoren 

ist in Abb. 19 gezeigt. Zur Realisierung 

des Speichers werden vier zusätzliche Maskenebenen 

benötigt. Ein erster 1-Mbit-Demonstrator ist bereits 

2004 entwickelt worden (Chip-Foto siehe Abb. 20). Die 

Eignung der Technologie für diese Speicherdichten 

konnte somit gezeigt werden. 2005 sind der Prozessablauf 

und einzelne Prozessschritte optimiert worden, 

insbesondere im Hinblick auf die Verwendung von 

2-Transistor-Zellen (Abb. 21), die für den Betrieb eines 

integrierten Speichers vorteilhaft sind (Zuverlässigkeit, 

Performance). 

Der Vergleich von CMOS Transistoren und HBTs des 

BiCMOS-Prozesses mit und ohne integrierten Flash- 

Speicher zeigt die Modularität des Interationskonzeptes. 

Sowohl in der Ausbeute von 4k-HBT-Arrays 

(Abb. 22), als auch in der Schwellspannung von nMOS- 

und pMOS-Transistoren (Abb. 23) ist keine Beeinträchtigung 

durch die Speicherintegration zu erkennen. 

46 

Percentage of Good Devices 

100 

80 

60 

40 

20 

0 

0 



BiCMOS + Flash BiCMOS only 

Abb. 22: Vergleich der Ausbeute an 4k-HBT-Arrays auf Wafern mit und 

ohne integrierten Flash Speicher. 

Fig. 22: Comparison of the yield of 4k HBT arrays on wafers with and 

without flash memory. 

5 10 15 20 25 

Wafer ID 

Speichertransistor 

Memory transistor 


Abb. 20: Chip-Foto des 1-Mbit-Demonstrators. 

Fig. 20: Micrograph of the 1 Mbit demonstrator. 

Long Channel Device V T (V) 

0.62 

0.60 

0.58 

-0.62 

-0.64 

0 

BiCMOS 

+ Flash 

25 

50 

No. of Data Point 

Auswahltransistor 

Select transistor 

Abb. 21: TEM-Querschnitt einer 2-Transistor-Zelle mit Speicher- 

transistor und Auswahltransistor. 

Fig. 21: TEM cross section view of a 2-transistor memory cell, 

showing the memory transistor and the select transistor. 

100 

125 

150 

Abb. 23: Vergleich der Schwellspannungen (V T ) der nMOS- und pMOS- 

Transistoren auf Wafern mit und ohne integrierten Flash 

Speicher. 

Fig. 23: Comparison of nMOS and pMOS threshold voltages (V T ) on 

wafers with and without flash memory. 

75 

BiCMOS only

DUV-Scanner für die Entwicklung der 0,13-µm-BiCMOS-Technologie. 

DUV scanner for the development of the 0.13 µm BiCMOS technology. 








Schottkydioden für HF-Anwendungen Schottky Diodes for RF Applications 

Ziel des Projektes ist es, Schaltungsdesignern hochfrequenztaugliche 

Schottkydioden bereitzustellen, ohne 

die Prozessierung der Wafer ändern zu müssen. 

Schottkydioden werden durch einen Metall-Halbleiter- 

Übergang erzeugt. Sie weisen praktisch keine Sperrverzögerungszeit 

auf. D. h., Schottkydioden schalten 

vom Durchlassbereich ohne Zeitverzug in den Sperrbereich. 

Bei normalen Siliziumdioden dauert dieser Umschaltvorgang 

je nach Bauart mehrere Nanosekunden 

bis Mikrosekunden. Typische Anwendungsgebiete für 

Schottkydioden sind passive Mischer im Gigahertzbereich, 

Levelshifter und Hochfrequenzgleichrichter. Passive 

Mischer nutzen die nichtlineare Kennlinie der Dioden 

aus und kommen, wie der Name schon sagt, ohne Betriebsspannung 

aus. Solche Mischer eignen sich daher 

besonders gut für stromsparende Schaltungen. Abb. 24 

zeigt den Schaltplan eines passiven Diodenmischers. 

Maßgabe bei der Entwicklung der Schottkydioden war, 

dass die verwendeten Prozessierungsschritte nicht verändert 

werden durften. Die Dioden mussten aus vorhandenen 

Schichten erzeugt werden. Als Halbleiterschicht 

stehen eine n-Wanne sowie eine p-Wanne zur Verfügung. 

Die Polarität der Diode wird durch diese Schicht bestimmt. 

Die Metallelektrode wird durch ein Silizid realisiert. 

Die direkte Abscheidung von Aluminium auf der Siliziumoberfläche 

ist in den Prozessen nicht vorgesehen 

und daher nicht möglich. Es sind verschiedene Layoutvarianten 

umgesetzt worden, um deren Einfluss bestimmen 

und modellieren zu können. 

Die Schottkydioden wurden in zwei verschiedenen 

Technologien prozessiert, SG25H1 mit Transistoren bis 

200-GHz-Grenzfrequenz und SGB25VD mit Transistoren 

bis 120 GHz Grenzfrequenz. Nach der Messung der verschiedenen 

Dioden erfolgte deren Bewertung. Ein besonders 

kritischer Parameter ist dabei das Produkt von 

Serienwiderstand RS und Kapazität C0. Je kleiner dieses 

Produkt ist, desto höher ist die Grenzfrequenz der Diode. 

Die Dioden aus n-Well und Silizid erreichten dabei die 

höchsten Grenzfrequenzen. Der Querschnitt einer solchen 

n-Well Schottkydiode ist in Abb. 25 zu sehen. Sie 

erreicht eine Großsignal-Grenzfrequenz 1/(C0*RS) von 

165 GHz. Nach der Vorselektion des besten Diodentyps 

erfolgte dessen genaue elektrische Charakterisierung. 

Aus den Messdaten wurden Modellparameter extrahiert. 

Wie in Abb. 26 dargestellt wurde eine sehr gute Über- 

48 




The goal is to provide high frequency capable Schottky 

diodes to the circuit designers without needs of 

process changes. 

Schottky diodes are realized by a metal semiconductor 

interface. They do not have a reverse recovery 

time. It means that they can switch from forward direction 

to reverse direction without a time delay. Normal 

silicon diodes need several nanoseconds up to 

microseconds for such a switching action. Typical applications 

of Schottky diodes are passive mixers in 

the gigahertz range, level shifters and high frequency 

rectifiers. Passive mixers use the nonlinearities of 

the diodes. They do not need a power supply as the 

name implies. Such mixers are well suited for power 

saving circuits. Fig. 24 shows the schematic of a passive 

diode mixer. 

LO 

Abb. 24: Passiver Mischer. 

Fig. 24: Passive Mixer. 

A requirement for the development of the Schottky diodes 

was that the process remained unchanged. Only 

the currently available layers could be used. The semiconductor 

is formed by an n-well or a p-well. That layer 

defines the polarity of the diode. The metal electrode 

is realized by a silicide. The direct deposition of aluminum 

on the silicon surface is not intended and hence 

not possible. Different layout variants were fabricated. 

Their influences were identified and modeled. 

The Schottky diodes were manufactured in two different 

technologies. SG25H1 provides transistors with 

RF 

IF

einstimmung zwischen Messung und Simulation erreicht. 

Die n-Well-Schottkydiode wurde als neues Bauelement in 

das Designkit des IHP aufgenommen und steht ab sofort 

für Schaltungsdesign zur Verfügung. 

abs (Anode Current) (A) 

Anode Cathode 

10 -2 

10 -3 

10 -4 

10 -5 

10 -6 

10 -7 

10 -8 

10 -9 

-4 

n-well 

-3 

-2 

NSD 

Si substrate 

Abb. 25: Querschnitt einer n-Well-Schottkydiode. 

Fig. 25: Cross section of an n-well Schottky diode. 

Simulation 

Measurement data 

-1 

Anode Voltage (V) 

Silicide 

Abb. 26: Gleichspannungs-Kennlinie und Hochfrequenz-Übertragungsfunktion 

einer n-Well-Schottkydiode. 

Fig. 26: DC characteristic and RF forward transfer function of an 

n-well Schottky diode. 

0 

-1 





transit frequencies up to 200 GHz and SGB25VD transistors 

with 120 GHz transit frequency. The diodes 

were evaluated after the electrical measurements. 

A critical parameter is the product of the series resistance 

RS and capacitance C0. The lower the product, 

the higher is the cut-off frequency of the diode. The nwell 

diodes achieved the highest cut-off frequencies. 

The cross-section of such an n-well Schottky diode is 

displayed in Fig. 25. The large-signal cut-off frequency 

1/(C0*RS) of that diode is 165 GHz. After preselection 

of the best diode type a precise electrical characterization 

of that type was performed. Model parameters 

were extracted from measurement data. A very good 

agreement between measurement and simulation was 

achieved as shown in Fig. 26. The n-well Schottky diode 

was included in the IHP design kit and is available 

for circuit applications from now on. 

Magnitude (S21) (dB) 

0 

-10 

-20 

-30 

-40 

-50 

-60 

100M 

1G 

Frequency (Hz) 

Anode Voltage: 

0.1 V – 0.5 V 

step 0.1 V 

Simulation 

Measurement data 

10G 

100G 




Pilotlinie 

Das IHP betreibt eine Pilotlinie, die sowohl techno- 

logische Entwicklungen als auch den Zugriff auf sehr 

leistungsfähige und stabile Technologien für interne 

und externe Designer ermöglicht. 

Innovationen bei Technologien und Schaltkreisen erfordern 

eine hohe Stabilität der Pilotlinie sowie kurze Präparationszeiten 

bei hoher Qualität und Ausbeute. 

Für Standardlose wird eine Durchlaufzeit von 4,2 Tagen 

und für priorisierte Lose 1,8 Tagen pro Maske erreicht, 

die sich lediglich um den Faktor 1,4 von der 

physikalischen Prozesszeit unterscheidet. 

Die hohe Qualität der Pilotlinie wird durch die jährliche 

erfolgreiche ISO-Zertifizierung 9001:2000 dokumentiert 

(Abb. 27). 

50 



Abb. 27: DIN EN ISO9001:2000 Zertifikat der DQS GmbH. 

Fig. 27: DIN EN ISO9001:2000 certificate from the German DQS 

society. 

Pilot Line 


IHP is running a pilot line, enabling technological developments 

as well as access to very powerful and stable 

technologies for internal and external designers. 

Innovations in technologies and circuits need a high 

stability of the pilot line as well as short preparation 

times of high quality and yield. 

The cycle time for standard lots is 4.2 days and for 

expedited lots 1.8 days per mask, so the cycle time 

can be improved to a flow factor of 1.4. The flow 

factor is defined as the actual processing time divided 

by the minimum possible processing time for full 

BiCMOS flows. 

The high quality of the pilot line is documented by the 

annual reservice of the ISO9001:2000 certification of 

all technology departments without deviations. Fig. 27 

shows the certificate granted by the German quality 

society DQS. 

Currently, there are several 0.25 µm SiGe BiCMOS 

technologies available. They offer integrated HBTs 

with cut-off frequencies up to 230 GHz and RF LDMOS 

devices with breakdown voltages up to 26 V, including 

complementary devices. The technologies are described 

precisely in the chapter “Deliverables and Services“ 

of this report. A 0.13 µm BiCMOS technology is 

currently under development. 

In addition to the use for the development of circuits 

and systems at the IHP, the technologies are offered 

as MPW & Prototyping service to external partners 

and customers. 

In 2005, 13 new mask sets were processed, serving 

27 internal IHP projects and 18 external customers. 

The workflow in the pilot line is managed by a fully automated 

Manufacturing Execution System. All required 

data from WIP (work in process) are stored in a database 

(Fig. 28). These data are available for management 

and customers. 

Please come and visit our cleanroom.

Gegenwärtig sind mehrere 0,25-µm-SiGe-BiCMOS-Technologien 

verfügbar. Sie enthalten integrierte Hetero-Bipolartransistoren 

mit Grenzfrequenzen bis 230 GHz 

und HF-LDMOS-Bauelemente mit Durchbruchspan- 

nungen bis zu 26 V, einschließlich komplementärer 

Bauelemente. Die Technologien sind im Kapitel 

„Angebote und Leistungen“ dieses Berichtes genauer 

beschrieben. Eine 0,13-µm-BiCMOS-Technologie wird 

derzeit entwickelt. 

Neben der Nutzung für Schaltkreis- und Systementwicklungen 

am IHP werden die Technologien als MPW 

& Prototyping Service auch externen Partnern und Kunden 

angeboten. Dabei sind 2005 insgesamt 13 neue 

Testfelder innerhalb von 27 internen Projekten und für 

18 externe Kunden bearbeitet worden. 

Abb. 28: Schema des Systems zur Prozess-Steuerung. 

Fig. 28: Schematic of the Manufacturing Execution System. 

Die Steuerung in der Pilotlinie basiert auf einem vollständig 

automatisierten System. Alle wesentlichen Prozessdaten 

werden in einer Datenbank bereitgestellt, 

auf die sowohl das Management als auch die Nutzer 

Zugriff haben (Abb. 28). 

Gern laden wir Sie zu einer Besichtigung unseres Reinraumes 

ein. 



Abb. 29: Im Reinraum des IHP. 

Fig. 29: Inside IHP’s cleanroom. 





Materialien 

Ziel dieses Projektes ist die Evaluierung des Hoch-k- 

Dielektrikums Pr-Silikat als potenzieller Ersatz für 

nitridiertes SiO 2 in zukünftigen CMOS-Transistor-Generationen. 

Das Gatedielektrikum ist ein zentraler Bestandteil des 

CMOS-Transistors. Infolge der fortschreitenden Miniaturisierung 

von mikroelektronischen Bauelementen wird 

die Schichtdicke des Gatedielektrikums reduziert und 

beträgt bereits heute in CMOS-Transistoren ca. 1 nm. 

Für zukünftige CMOS-Transistor-Generationen werden 

noch dünnere Gateoxidschichten benötigt. Die weitere 

Skalierung des etablierten Siliziumoxynitrids ist 

aber aufgrund des starken Anstiegs des Leckstroms 

und der zunehmenden Bordiffusion aus der Poly-Silizium-Gateelektrode 

ausgeschlossen. Zur Lösung dieses 

Problems und um eine weitere Skalierung von herkömmlichen 

Planar-CMOS-Transistoren zu ermöglichen, 

müssen neuartige dielektrische Schichten mit höherer 

Dielektrizitätskonstante eingeführt werden. 

Gegenstand der Forschung sind deshalb Praseodymsilikat-Schichten. 

Erste grundlegende materialbasierte 

Untersuchungen zeigen, dass Praseodymsilikat geeignet 

sein kann, um SiO 2 zu ersetzen. Abb. 30 zeigt eine 

Querschnitts-TEM Aufnahme einer isolierenden Pra- 

seodymsilikat-Schicht auf Si(001). Das Dielektrikum 

besteht typischerweise aus zwei amorphen Schichten: 

einer SiO 2 -reichen Praseodymsilikat-Schicht an der 

Grenze zum Silizium und einer zweiten SiO 2 -armen Praseodymsilikat-Schicht. 

Der Vorteil dieser Struktur ist, 

dass sie eine signifikante Verringerung des Leckstromes 

und gleichzeitig eine hohe Qualität der SiO 2 /Si 

Grenzfläche ermöglicht. Praseodymsilikat-basierte 

Gate-Schichtstapel weisen eine effektive Dielektrizitätskonstante 

von 12 und einen um ungefähr 3 Größenordnungen 

reduzierten Leckstrom im Vergleich zu 

nitridierten SiO 2 -Schichten mit gleicher äquivalenten 

Oxidschichtdicke auf. Pr-Silikate sind zudem thermisch 

stabil gegenüber Kristallisation und Phasenseparation 

bei typischen Dotieraktivierungs-Temperaturen. 

52 


Materials 

Materialien für die Mikroelektronik/ 

Materials for Microelectronics 

Pr-Silikat als Hoch-k-Dielektrikum 

auf Si(001) für Anwendungen als 

Gateisolator 


Pr Silicate High-k Layers on Si(001) 

for Gate Dielectric Applications 

The goal of this project is to evaluate the potential of a 

Pr silicate high-k dielectric to replace the traditionally 

used nitrided SiO 2 gate insulator in future CMOS technology 

generations. 

Gate dielectric is a key building block of a CMOS transistor. 

As a direct consequence of the miniaturization 

of Si-based microelectronic devices, the thickness of 

the gate dielectric in the state-of-the-art CMOS devices 

has been reduced to a value of about 1 nm. Future 

CMOS generations will require ever thinner gate 

dielectrics. However, further scaling of silicon oxynitride 

dielectrics (below 1 nm) does not provide further 

gain in the performance, due to unacceptably high leakage 

currents and boron penetration from the polysilicon 

gate electrode. To overcome these problems and 

to enable further planar CMOS scaling, an alternative 

gate insulator with a higher permittivity must be introduced. 

Au 

Pr silicate 

Si 

5 nm 

Abb. 30: Querschnitts-TEM-Aufnahme einer isolierenden Praseodymiumsilikat-Schicht 

auf Si(001). 

Fig. 30: Cross-section TEM image of a Pr silicate high-k dielectric 

layer on Si(001).

Die grundlegende Materialcharakterisierung wurde 

durch die Entwicklung einer geeigneten CMOS-kompatiblen 

Ätzprozedur für den Poly-Si/Pr-Silikat-Gate- 

Stapel abgerundet. Pr-basierte dielektrische Schichten 

lassen sich mit guter Selektivität in verdünnter 

H 2 SO 4 lösen, wobei die Ätzrate entweder durch die 

Temperatur oder durch die Konzentration des Ätzmittels 

kontrolliert werden kann. Die Strukturierung der 

PolySi-Gate-Elektrode erfolgt durch RIE mittels einer 

Mischung aus CF 4 und O 2 . Die kombinierte Nass/Trocken-Ätztechnik 

wurde zur Präparation eines nMOS- 

Transistors im konventionellen CMOS-Prozessablauf 

angewendet. Abb. 31 zeigt ein REM-Bild des Transistors 

mit einem Dielektrikum, bestehend aus Pr-Silikat. 

Substrate 

Source 

Gate 

Drain 

Abb. 31: REM-Aufnahme eines nMOS-Transistors mit Pr-Silikat als 

Gatedielektrikum. 

Fig. 31: SEM image of an NMOS transistor with integrated 

Pr silicate. 


Materialien 


Materials 

This study of alternative gate dielectrics is focused on 

Praseodymium (Pr) silicate layers. Primary evaluation 

of basic material characteristics indicates that Pr silicate 

may be suitable to replace SiO 2 . Fig. 30 shows 

a cross-section TEM image of a Pr silicate insulating 

layer deposited on Si(001). The silicate films are 

typically composed of two amorphous layers: an 

SiO 2 -rich Pr silicate layer at the interface with Si 

and a SiO 2 poor Pr silicate layer on top of it. The advantage 

of such a structure is that it provides a significant 

reduction of the leakage current and at 

the same time it may preserve the high electrical 

and structural quality of the SiO 2 /Si interface. 

Pr silicate-based gate stacks exhibit an effective dielectric 

constant of 12 and approximately 3 orders of 

magnitude lower leakage current density as compared 

with nitrided SiO 2 samples of the same equivalent 

oxide thickness. Pr silicates are also thermally stable 

against crystallization and phase separation under typical 

dopant activation annealing conditions. 

Completion of the basic material characterization has 

been followed by development of a suitable CMOS 

compatible etching procedure for a poly-Si/Pr silicate 

gate stack. We found that Pr-based dielectric layers 

can be dissolved with a good selectivity in diluted 

H 2 SO 4 and the etching rates can be controlled either 

by changing the temperature or the concentration of 

the etchant. The poly-Si gate electrode patterning can 

be accomplished by RIE using a mixture of CF 4 and O 2 . 

This combined dry/wet etching technique was applied 

for preparation of an nMOS transistor in the conven- 

tional CMOS process flow. Fig. 31 shows an SEM image 

of the transistor with integrated Pr silicate dielectric. 


54 


Materialien 


Materials 

Laminare MIM-Kondensatoren für 

HF- und Mixed-Signal Anwendungen 

Die Metall-Isolator-Metall-(MIM)-Kondensatoren haben 

als passive Bauelemente in Hochfrequenz (HF)- und 

integrierten Schaltungen (IC) Aufmerksamkeit erregt. 

Der Ersatz der konventionellen Materialien SiO 2 und 

Si 3 N 4 durch Hoch-k-Dielektrika ist notwendig, um die 

Kondensatorfläche zu reduzieren. 

MIM-Kondensatoren mit Pr 2 O 3 als Dielektrikum zeigen 

große Hoch-k-Werte (~15), aber die Leckstromdichte 

ist nicht geeignet für HF-Anwendungen. Deshalb wurde 

folgender Ansatz gewählt: Der Pr 2 O 3 -Film wird zwischen 

zwei Schichten des Weitband-Isolators Al 2 O 3 

eingebettet. Neben der Erhöhung der elektrischen Barrierehöhe 

soll der obere Al 2 O 3 -Film als Schutzschicht 

wirken, um das Pr 2 O 3 gegenüber Luftfeuchtigkeit zu 

schützen. Die geschichteten Al 2 O 3 /Pr 2 O 3 /Al 2 O 3 MIM- 

Kondensatoren sind viel versprechende Kandidaten, 

um die Anforderungen der aktuellen ITRS zu erfüllen 

(Abb. 32). Wir präsentieren einen neuen Hoch-k MIM- 

Stapel mit einer großen Kapazitätsdichte von 5,7 fF/µm 2 , 

einer geringen Leckstromdichte von 5x10 -9 A/cm 2 bei 

1 V und minimalen dielektrischen Verlusten im untersuchten 

Frequenzbereich. 

MIM-Kondensatoren mit Pr 2 Ti 2 O 7 als Dielektrikum zeigen 

parabolische C(V) Kurven mit positiven Vorzeichen. 

Der quadratische Spannungskoeffizient der Kapazität 

kann durch die Kombination von Pr 2 Ti 2 O 7 und SiO 2 zu 

einer geschichteten MIM-Struktur gesteuert werden 

(Abb. 33). Der SiO 2 -Film beeinflusst sowohl die Leckstrom-Charakteristik 

als auch das dielektrische Durchbruchverhalten. 

Aufgrund des kleinen k-Wertes von 

SiO 2 ist die resultierende Kapazität reduziert. Deshalb 

sollte die Schichtdicke des Oxidfilmes so dünn wie 

möglich gehalten werden. 

Die geschichteten SiO 2 /Pr 2 Ti 2 O 7 -MIM-Kondensatoren 

zeigen hervorragende elektrische Eigenschaften. Der 

quadratische Spannungskoeffizient der Kapazität und 

der Leckstromparameter erfüllen die Anforderungen der 

aktuellen ITRS. Die extrapolierte Betriebsspannung für 

eine Lebensdauer von 10 Jahren beträgt 3 V für MIM-Kon- 

densatoren mit einer Kapazitätsdichte von 3,2 fF/µm 2 . 


Laminated MIM Capacitors for RF 

and Mixed-Signal Applications 

The Metal-Insulator-Metal (MIM) capacitors have attracted 

much attention as passive devices for Radio-Frequency 

(RF) and mixed-signal Integrated Circuit (IC) applications. 

The replacement of conventional SiO 2 and 

Si 3 N 4 by high-k dielectric materials is essential to reduce 

the capacitor area. 

Glue 

Al 2 O 3 

Pr 2 O 3 

Al 2 O 3 

TiN 

Abb. 32: TEM-Bild eines Al 2 O 3 /Pr 2 O 3 /Al 2 O 3 -MIM-Kondensators. 

Fig. 32: TEM picture of the Al 2 O 3 /Pr 2 O 3 /Al 2 O 3 MIM capacitor. 

MIM capacitors with Pr 2 O 3 as the dielectric have large 

high-k values (~15), but the leakage current density is 

too high for RF applications. For this reason, we use 

the band offset engineering approach by sandwiching 

the Pr 2 O 3 film between two layers of the wide band gap 

insulator Al 2 O 3 . Besides the increase of the electric 

barrier height, the top Al 2 O 3 layer also acts as a cap 

to protect the Pr 2 O 3 film against humidity. The layered 

Al 2 O 3 /Pr 2 O 3 /Al 2 O 3 MIM capacitors are promising candidates 

to meet the requirements of the current ITRS 

(Fig. 32). We present a new high-k MIM stack with a 

high capacitance density of 5.7 fF/µm 2 , a low leakage 

current density of 5x10 -9 A/cm 2 at 1 V and excellent 

dielectric loss behaviour over the studied frequency 

range.

Glue 

Pr 2 Ti 2 O 7 

SiO 2 

TiN 

Abb. 33: TEM-Bild eines SiO 2 /Pr 2 Ti 2 O 7 MIM- Kondensators. 

Fig. 33: TEM picture of the SiO 2 /Pr 2 Ti 2 O 7 MIM capacitor. 


Materialien 


Materials 

MIM capacitors with Pr 2 Ti 2 O 7 as the dielectric exhibit a 

positive quadratic C(V) curve. The quadratic voltage capacitance 

coefficients can be engineered by combining 

Pr 2 Ti 2 O 7 and SiO 2 to a stacked MIM structure (Fig. 33). 

The SiO 2 layer affects both the leakage current characteristics 

and the dielectric breakdown values. Due to 

the low value of SiO 2 , the resulting capacitance will be 

reduced. Therefore, this oxide layer thickness must be 

kept as thin as possible. 

The stacked SiO 2 /Pr 2 Ti 2 O 7 MIM capacitors show 

excellent electrical performances. The quadratic vol- 

tage coefficient of capacitance and the leakage parameter 

fulfill the requirements of the current ITRS. The 

extrapolated operating voltage to 10 years lifetime is 

3 V for MIM capacitors with a capacitance density of 

3.2 fF/µm 2 . 



Materialien 

Einkristalline Halbleiter-Isolator- 

Systeme auf Silizium 

Ziel des Projektes ist die Züchtung einkristalliner Halbleiter-Isolator-Systeme 

hoher elektrischer Qualität auf 

Silizium (Si). Diese Systeme können mittels lokaler 

oder globaler Epitaxie-Ansätze in moderne, Si-basierte 

Schaltkreise integriert werden, um Leistung und Funktionalität 

zu steigern. 

Heteroepitaktische Halbleiter-Isolator-Stapel auf Si 

sind von besonderem Interesse für die Weiterentwicklung 

der Si-basierten Mikroelektronik, denn gitterangepasste 

Systeme kombinieren Funktionalität mit hoher 

struktureller Stabilität. Zum Beispiel werden derzeit 

sowohl lokale als auch globale Epitaxie-Ansätze gestresster 

Si-Filme studiert, um die Beweglichkeiten 

von Löchern und Elektronen in dünnen Halbleiterfilmen 

maßzuschneidern. Natürlich erfordert die kosteneffektive 

Herstellung von Halbleiter-Isolator-Strukturen mittels 

zweier aufeinanderfolgender Epi-Schritte zunächst 

die Herstellung eines einkristallinen Oxidfilmes auf Si. 

In diesem Projekt gelang die Herstellung einkristalliner 

Praseodymium-Sesquioxid-(Pr 2 O 3 )-Filme auf Si(111). 

Interessanterweise erfolgte die Herstellung epitak- 

tischer, kubischer (111)-Pr 2 O 3 -Filme ohne Stapelzwillinge 

auf Si(111) nicht durch direkte Filmdeposition, sondern 

mittels einer induzierten hexagonal-kubischen 

Phasenumwandlung des aufgewachsenen Oxidfilmes. 

Synchrotronbasierte Röntgenbeugung unter streifendem 

Einfall (SR-GIXRD) an der European Synchrotron 

Radiation Facility (ESRF) in Grenoble (Frankreich) und 

Transmissionselektronen-Mikroskopie (TEM) am IHP 

wurden zum Studium der Phasenumwandlung und der 

Filmstruktur verwandt. Aufgedampfte Filme wachsen 

einkristallin in der hexagonalen Hochtemperatur-Phase 

mit (0001) Orientierung. In-situ Röntgenbeugungsmessungen 

erlauben, eine Aktivierungsenergie von 

2,2 eV für die hexagonal-kubische Phasenumwandlung 

abzuleiten. TEM-Studien zeigen, dass die Phasenumwandlung 

von einer Grenzflächenreaktion an der Oxid/ 

Si(111) Grenzschicht begleitet ist. Die resultierende, 

kubische (111)-Tieftemperaturphase des Pr 2 O 3 -Filmes 

ist einkristallin und besitzt exklusiv eine Typ-B-Orientierung, 

d.h. der Oxidfilm übernimmt nicht die Stapelorientierung 

des Si(111)-Substrates (Typ-A-Orientierung), 

sondern kehrt diese um und die epitaktische 

Orientierung des Oxidgitters gegenüber dem Si(111)- 

Substrat ist durch eine 180 °-Drehung um die Ober- 

56 


Materials 


Single Crystalline Semiconductor- 

Insulator-Systems on Silicon 

The goal of the project is to prepare single crystalline 

semiconductor-insulator systems of high electric quality 

on silicon (Si). Such systems can be integrated either 

by local or global epitaxy approaches to improve 

the performance and functionality of modern Si-based 

microelectronic circuits. 

Heteroepitaxial semiconductor-insulator stacks on Si 

are of special interest to further develop Si-based microelectronics 

because lattice matched systems combine 

functionality with high structural stability. For example, 

global and local epitaxy approaches of strained 

Si layers are currently studied to engineer the mobility 

of holes and electrons in thin semiconductor films. 

Certainly, the cost-effective growth of a high quality 

semiconductor-insulator stack on Si by two simple 

subsequent epi-steps requires first the preparation of 

a truly single crystalline oxide film on Si. 

In this project we achieved the preparation of truly 

single crystalline praseodymium sesquioxide (Pr 2 O 3 ) 

films on Si(111). Interestingly, the preparation of twinfree 

epitaxial cubic (111) Pr 2 O 3 films on Si(111) did not 

result from direct film deposition techniques but by 

inducing a hexagonal to cubic phase transition of the 

as-deposited Pr 2 O 3 film on Si(111). Synchrotron radiation 

grazing incidence X-ray diffraction (GI-XRD) at 

the European Synchrotron Radiation Facility (ESRF) in 

Grenoble (France) and transmission electron microscopy 

(TEM) at IHP were applied to characterize the phase 

transition and the film structure. As-deposited films 

grow single crystalline in the (0001) oriented hexagonal 

high-temperature phase of Pr 2 O 3 . In-situ X-ray diffraction 

studies deduce an activation energy of 2.2 eV for 

the hexagonal to cubic phase transition. Transmission 

electron microscopy shows that the phase transition 

is accompanied by an interface reaction at the oxide/ 

Si(111) boundary. The resulting cubic (111) low-temperature 

Pr 2 O 3 film is single crystalline and exclusively 

shows B-type stacking. This means that the oxide 

layer does not adopt the stacking configuration of 

the Si(111) substrate but reverses it so that the epitaxial 

relation of the oxide with respect to the Si(111) 

substrate is characterized by a 180 ° rotation around 

the Si(111) surface normal. The 180 ° rotation of the 

cubic oxide lattice with respect to the Si substrate 

results microscopically from a stacking fault at the

flächennormale gekennzeichnet. Diese 180 °-Rotation 

des kubischen Oxidgitters in Bezug auf das Si-Substrat 

resultiert mikroskopisch von einem Stapelfehler an der 

Oxid/Substrat-Grenzfläche. Der Strukturbeweis wurde 

mittels SR-GIXRD erbracht und ist in Abb. 34 zusammengefasst. 

Die Zeichnung im linken Teil der Abbildung 

verdeutlicht die Intensitätsverteilung, die bei gleichzeitiger 

Anwesenheit von Typ-A (gefüllte Kreise) und Typ-B 

(offene Kreise) -Domänen im Oxidfilm zu erwarten ist. 

Die im Folgenden diskutierten experimentellen Ergebnisse 

wurden durch Messungen entlang der [01L]-Richtung 

(grau unterlegt) gewonnen. Die volumensensitive 

Messung im rechten Teil der Abbildung bei einem Einfallswinkel 

von 1 ° (oberhalb des kritischen Winkels) 

zeigt, dass die Verteilung der Oxidreflexe (gestrichelte 

Pfeile) charakteristisch für eine Typ-B-Orientierung ist. 

Im Grunde genommen kann die Anwesenheit von Typ- 

A-Domänen in dieser Messung aber nicht ausgeschlossen 

werden, da die entsprechenden Oxidreflexe durch 

die Si-Substrat Bragg- Peaks (durchgezogene Pfeile) 

überstrahlt werden könnten. Um dieses auszuschließen, 

wurde eine Oberflächen-sensitive Messung bei 

0,2 ° (unterhalb des kritischen Einfallswinkels) ausgeführt, 

die es erlaubt, den Film ohne Substrateinfluss 

zu vermessen. Das Ergebnis ist im mittleren Teil der 

Abbildung dargestellt und es ist ersichtlich, dass ausschließlich 

Typ-B-Oxidreflexe existieren. Dies ist der 

Strukturbeweis für die zwillingsfreie, einkristalline Natur 

des kubischen Pr 2 O 3 (111)-Filmes auf Si(111). 

Abb. 34: Strukturbeweis der einkristallinen Typ-B-Epitaxie des 

(111)-orientierten kubischen Pr 2 O 3 -Filmes auf Si(111). 


Materialien 


Materials 

substrate/oxide boundary. The structure prove was 

provided by SR-GIXRD measurements and is shown 

in Fig. 34. The sketch on the left side of the Figure 

shows the Bragg peak intensity distribution in case 

of the simultaneous presence of Type A (filled circles) 

and Type B (open circles) domains in the oxide layer. 

The experimental results discussed in the following 

are collected by measurements along the [01L] rod 

(gray panel). The bulk sensitive measurement on the 

right side of the figure at 1 ° (above the critical angle) 

shows that the distribution of the oxide reflections 

(dotted arrows) is characteristic for a type B orientation. 

In this measurement, however, the presence of 

type A domains in the oxide film can not be excluded. 

This is due to the fact that the Si substrate peaks 

(solid arrows) could in principle be superimposed in 

this measurement on the oxide type A reflections. 

For this purpose, a surface sensitive measurement 

at 0.2 ° (below the critical angle) was carried out 

to measure exclusively the film without any substrate 

contribution. The result is shown in the middle 

of the figure and it is seen that only type B oxide reflections 

are present. This is the structure prove for 

the twin-free, single crystalline nature of the type B 

oriented cubic Pr 2 O 3 (111) film on Si(111). 

Fig. 34: Structure prove of single crystalline type B epitaxy of 

(111) oriented cubic Pr 2 O 3 films on Si(111). 



Materialien 

Kohärente Nukleation von Sauerstoffpräzipitaten 

in Silizium 

Ziel der Arbeiten war es, den Einfluss einer RTA- 

induzierten Vakanzenübersättigung auf die Sauerstoffpräzipitation 

auf einer breiten experimentellen Basis 

durch Variation der RTA-Temperatur, der Abkühlrate, 

der Vakanzenkonzentration, der Interstitialkonzentration 

und der Kristallziehbedingungen zu untersuchen, um so 

einen umfassenden Überblick über die verschiedenen 

parametrischen Abhängigkeiten der Sauerstoffpräzipitation 

zu erhalten. Auf der Basis dieser Korrelationen wurde 

ein analytisches Modell erarbeitet, das die Abnahme 

des interstitiellen Sauerstoffs während eines Prozesses 

bestehend aus einer RTA-Behandlung und einer zweistufigen 

Temperung bei 780 °C für 3 h und bei 1000 °C für 

16 h beschreibt. Auf der Basis der gefundenen experimentellen 

Zusammenhänge wurde ein atomistisches 

Modell entwickelt, das einen kohärenten Nukleationsprozess 

für Sauerstoffpräzipitate beschreibt. 

Es wurde gefunden, dass die Sauerstoffpräzipitation 

nach der RTA-Behandlung von der Sauerstoffkonzentration 

in der sechsten Potenz abhängt und von der 

eingefrorenen Vakanzenkonzentration nur in der dritten 

Potenz. Der bevorzugte Nukleationsprozess für 

Sauerstoffpräzipitate ist die Agglomeration von VO 2 - 

Komplexen und die Dichte der Sauerstoffpräzipitate 

ist proportional der dritten Potenz der VO 2 -Komplexe, 

die während der Abkühlung nach dem RTA-Prozess gebildet 

werden (Abb. 35). Die Abnahme des interstitiellen 

Sauerstoffs während eines Prozesses, der aus der 

oben beschriebenen RTA-Behandlung mit zweistufiger 

Temperung besteht, kann im Temperaturbereich von 

1150 °C bis 1250 °C mit Hilfe der Ham’schen Theorie 

für das Präzipitatwachstum und eines empirischen Zusammenhangs 

der auf der Nukleation von Sauerstoffpräzipitaten 

durch VO 2 -Agglomeration beruht mit hoher 

Genauigkeit modelliert werden. 

Ausgehend von den gefundenen Zusammenhängen haben 

wir mit Hilfe von ab-initio Berechnungen der Gesamtenergie 

und der atomistischen Strukturen der 

Punktdefekte und Punktdefektcluster ein atomistisches 

Modell entwickelt, das die kohärente Nukleation 

von Sauerstoffpräzipitaten über VO 2 -Cluster in 

vakanzenreicher Umgebung beschreibt. Das Modell 

kann folgendermaßen zusammengefasst werden: 

VO 2 -Komplexe neigen dazu, nVO 2 -Cluster zu bilden, 

weil im Gegensatz zu isoliertem VO 2 die Si-Atome, die 

58 


Materials 


Coherent Nucleation of Oxygen 

Precipitates in Silicon 

The aim of this work was to investigate the impact of 

RTA induced vacancy supersaturation on oxide precipitation. 

As an experimental basis we have a broad 

set of experimental values obtained from variations of 

RTA temperature, cooling rate, vacancy concentration, 

interstitial oxygen concentration, and crystal pulling 

conditions in order to gain a most comprehensive 

overview on the various parameter dependencies of 

the oxygen precipitation. Given these correlations, an 

analytical model was developed which can describe 

the reduction of interstitial oxygen during a process 

consisting of an RTA treatment and a two-step anneal 

at 780 °C for 3 h and at 1000 °C for 16 h. An atomistic 

model was proposed that describes a coherent nucleation 

process for oxide precipitates in agreement 

with the results of the analytical model. 

Density of Oxide Precipitates (1/cm³) 

10 11 

10 10 

10 9 

10 8 

10 11 

10 12 

10 13 

Concentration of VO 2 Complexes (1/cm³) 

10 14 

Abb. 35: Dichte der Sauerstoffpräzipitate nach einem thermischen 

Prozess bestehend aus RTA + 780 °C 3 h + 1000 °C 16 h 

als Funktion der Konzentration der VO 2 -Komplexe für RTA- 

Behandlungen bei Temperaturen zwischen 1150 °C und 1250 °C. 

Fig. 35: Oxygen precipitate density after a thermal cycle consisting 

of RTA + 780 °C 3 h + 1000 °C 16 h shown as a function of 

the concentration of VO 2 complexes for RTA treatments at 

temperatures between 1150 °C and 1250 °C. 

Oxygen precipitation after RTA processing was found 

to be controlled by the initial concentration of interstitial 

oxygen in the sixth power dependency and of frozen 

vacancies in just a cubic dependency. The favored 

process for nucleation of oxide precipitates after RTA 

treatments is the agglomeration of VO 2 complexes. 

The density of oxide precipitate nuclei was found to be 

proportional to the cube of VO 2 complexes formed du-

von 4VO 2 umgeben sind, ihre Bindungswinkel zu ihren 

Nachbarn voll relaxieren können (Abb. 36). Die lokale 

Geometrie dieser winzigen nVO 2 -Cluster erhält man 

durch eine periodische Wiederholung des 4VO 2 -Clusters. 

Die Cluster sind kohärent in Bezug auf das Sili- 

ziumgitter. Das Molekularvolumen dieses so genannten 

„seed“-SiO 2 ist kleiner als das Molekularvolumen von Silizium. 

Im Gegensatz zu allen anderen SiO 2 -Phasen, die 

bisher für die Nukleation von Sauerstoffpräzipitaten 

in Betracht gezogen wurden, sind diese kohärenten 

Keime mit einem Gittermisfit von 10 % unter Zugspannung. 

Unendliches kohärentes Wachstum der Keime 

durch Anlagerung von VO 2 ist nicht möglich wegen 

der durch den Gittermisfit wachsenden Verzerrungs- 

energie und weil die Konzentration der VO 2 -Komplexe 

mehrere Grössenordnungen kleiner ist als die Konzentration 

des interstitiellen Sauerstoffs. Der interstitielle 

Sauerstoff wird jedoch durch das Zugspannungsfeld 

des Keims angezogen und oxydiert die Si-Si-Bindungen 

in der unmittelbaren Umgebung des nVO 2 -Clusters, wobei 

sich ein cristobalitähnlicher Mantel bildet. In der 

Anfangsphase kann die Druckspannung im Cristobalit- 

Mantel durch die Zugspannung im „seed“-SiO 2 -Kern annihiliert 

werden. Bei fortschreitendem Wachstum und 

wenn die Temperatur hoch genug ist, kann die Struktur 

des Präzipitats amorph werden. 

Abb. 36: Kugelmodell eines 4VO 2 -Clusters, das den kleinsten SiO 2 -Keim 

darstellt (kleine Kugeln: Sauerstoff). 

Fig. 36: Ball-and-stick model of a 4VO 2 cluster comprising the 

smallest SiO 2 nucleus (small bullets: oxygen). 


Materialien 


Materials 

ring cooling after RTA (Fig. 35). The reduction of interstitial 

oxygen during the RTA treatment followed by the 

two-step anneal as described above can be accurately 

modeled for the temperature range from 1150 °C to 

1250 °C using Ham’s theory for precipitate growth and 

an empirical connection based on nucleation of oxide 

precipitates by agglomeration of VO 2 complexes. 

Given these results, we developed an atomistic model 

that describes the coherent nucleation process of oxygen 

precipitates via VO 2 clustering in a vacancy-rich 

environment. The model is based on ab initio calculations 

for total energies and atomic structures of point 

defects and point defect clusters, and can be summarized 

as follows: 

VO 2 point defect complexes tend to form nVO 2 clusters 

because in contrast to isolated VO 2 , the Si atoms surrounded 

by 4VO 2 can fully relax its bond angles with 

its neighbors (Fig. 36). These tiny nVO 2 clusters have 

locally the geometry which is obtained by the periodic 

repetition of the 4VO 2 cluster. They are coherent 

with the lattice of bulk silicon. The molecular volume 

of this “seed”-SiO 2 is lower than the molecular volume 

of silicon. In contrast to any other SiO 2 phase considered 

for oxide precipitate nucleation, these coherent 

nuclei are tensile strained with a lattice mismatch of 

10 %. Unlimited coherent growth of nuclei by attachment 

of VO 2 is not possible because of the increasing 

strain energy due to the misfit and because the concentration 

of VO 2 complexes is orders of magnitude 

smaller than the concentration of interstitial oxygen. 

However, interstitial oxygen is attracted by the tensile 

strain field of the nucleus and oxidizes the Si-Si bonds 

in the immediate vicinity of the nVO 2 cluster thus forming 

a cristobalite-like mantle. In the initial phase, 

the compressive strain in the cristobalite mantle can 

be annihilated by the tensile strain in the “seed”-SiO 2 

core. During further growth and at high enough temperature, 

the structure of the precipitate may change 

to amorphous. 



Materialien 

Lichtemitter auf der Basis von 

Si-Nanostrukturen 

Si-basierte Lichtemitter mit effizienter Strahlung 

bei 1,55 µm oder bei 1,3 µm werden für eine zukünf- 

tige optische Datenübertragung auf dem Chip benötigt. 

Licht emittierende Dioden (LED) aus kristallinen 

Si-Nanopartikeln, die in Si-Oxidschichten eingebettet 

sind, wurden in der Literatur als intensive Emitter bei 

1,55 µm beschrieben. Allerdings ist dazu eine Erbium- 

Dotierung erforderlich und die LED muss mit Spannungen 

von mindestens 20 V betrieben werden. Hier 

berichten wir über grundlegende Untersuchungen für 

Lichtemitter, die keine Er-Dotierung erfordern. Sie nutzen 

Effekte die von Nanostrukturen ausgelöst werden, 

und zwar entweder von Si-Nanodrähten oder von Versetzungen 

in Si, die sozusagen natürliche Nanostrukturen 

bilden. 

60 

Si-Nanodrähte 

Für konventionelle großflächige LED wird die Lichtausbeute 

durch Totalreflexion an der inneren Oberfläche 

erheblich verringert. Kürzlich wurde in der Literatur 

beschrieben, dass die Lichtextraktion durch Nutzung 

von Nanodrähten erheblich verbessert werden konnte, 

und zwar im Falle von InGaN/GaN-LED. Um dieses 

Prinzip auf Si übertragen zu können, braucht man Si- 

Nanodrähte, die bei 1,55 µm effizient strahlen. In der 

Zusammenarbeit mit der Zhejiang Universität (VR China), 

wo Si-Nanodrähte auf verschiedene Weise hergestellt 

werden, konnten wir solche Spezies separieren, 

die die gewünschte 1,55-µm-Emission mit hoher Effizienz 

aufweisen. Die Abb. 37 zeigt ein Spektrum, das 

bei 300 K mittels Kathodolumineszenz aufgenommen 

wurde. Nach unserem Wissen wurde erstmalig ein derartiges 

Verhalten an Si-Nanodrähten beobachtet. Die 

Nanodrähte wurden durch thermische Verdampfung 

von SiO auf einem Si-Wafer abgeschieden. Sie weisen 

eine kristalline Struktur auf und haben einen Durchmesser 

von 20-30 nm. Wir vermuten, dass Sauerstoff 

in Verbindung mit Kristalldefekten in den Drähten für 

die Ausbildung der markanten 1,55-µm-Lumineszenz 

verantwortlich ist. 

Versetzungen in Si 


Materials 

Versetzungen – als natürliche Nanostrukturen – verursachen 

in Si das Quartett der D1-D4-Linien, wobei D1 

und D3 bei den benötigten Wellenlängen von 1,55 µm 


Light Emitters Based on Silicon 

Nanostructures 

Si-based light emitters with efficient emission at 1.55 

or 1.3 µm, respectively are required for future on-chip 

optical interconnection. Light emitting diodes (LED) 

which consist of crystalline Si nanoparticles, embedded 

in Si-oxide or in Si-nitride layers, are found to exhibit 

efficient emission at 1.55 µm. They operate at a 

rather large voltage > 20 V and have to be doped with 

erbium (Er). Here we describe novel concepts for light 

emitters based on Si nanostructures that do not need 

Er. They are based on Si nanowires or on dislocations 

in Si (i.e. native nanostructures), respectively. 

Si Nanowires 

For conventional broad area LED the light extraction 

is reduced by the total internal reflection occurring 

at the LED surface. Recently, it was shown in the literature 

that the light extraction from a LED (based on 

InGaN/GaN) was markedly enhanced by using nanorod/nanowire 

arrays. This approach could also be 

used for silicon if Si nanowires (SiNWs) with appropriate 

luminescence behaviour would be available. The 

Zhejiang University (P.R. China) provided SiNWs. Here 

we report species of Si nanowires emitting efficiently 

around 1.55 µm. Fig. 37 shows a spectrum measured 

at RT with cathodoluminescence. To our knowledge, 

this is the first observation of such an NW behaviour. 

The SiNWs were fabricated on top of a Si wafer by 

thermal evaporation of Si monoxide. The NWs have 

a crystalline structure with a diameter of about 20- 

30 nm. Oxygen in conjunction with crystal defects in 

the NW is supposed to cause the observed luminescence. 

Dislocations in Si 

Dislocations in Si form a quartet of D1-D4 lines in 

the luminescence spectrum with D1/D3 appearing at 

about 1.55 or 1.3 µm, respectively. Their use as active 

components in the LED requires a well-controlled formation 

of the dislocations. A regular dislocation network 

can be formed by Si wafer direct bonding with a 

misorientation between the bonded wafers. It consists 

of screw and 60 º dislocations at the boundary and remains 

stable under thermal treatments. The density 

of the dislocations is determined by the angle(s) of 

misorientation. Recently, we demonstrated in collabo-

zw. 1,3 µm auftreten. Um Versetzungen allerdings 

als aktive Komponente in Bauelementen verwenden zu 

können, müssen sie reproduzierbar herstellbar sein. In 

Zusammenarbeit mit dem MPI für Mikrostrukturphysik 

Halle haben wir bereits gezeigt, dass durch Direktbonden 

von Si-Wafern unter Fehlorientierung ein reguläres 

Versetzungsnetzwerk an der Grenzfläche gebildet 

wird. Das Netzwerk besteht aus Schrauben- und 60 °- 

Versetzungen und verhält sich bei nachträglichen thermischen 

Behandlungen stabil. Die Versetzungsdichte 

CL Signal (a. u.) 

1.55 µm 

Si nanowires @ 300 K 

0.7 0.8 0.9 1.0 1.1 1.2 

Energy (eV) 

Abb. 37: CL-Spektrum von Silizium-Nanodrähten mit effizienter Lichtemission 

um 1,55 µm. 

Fig. 37: CL spectrum of Si nanowires at RT demonstrating efficient 

emission around 1.55 µm. 

hängt von den Winkeln der Fehlorientierung zwischen 

beiden Wafern ab. Kürzlich haben wir z. B. bereits gezeigt, 

dass bei bestimmter Fehlorientierung nur die D1- 

Strahlung vom Versetzungs-Netzwerk ausgeht und dabei 

eine Effizienz von einigen Prozent aufweist (IEDM 

Techn. Digest 2005). Nun haben wir eine weitere 

Netzwerkstruktur gefunden, bei der die Strahlung bei 

1,3 µm dominiert. Abb. 38 zeigt ein entsprechendes 

Spektrum, das mittels Kathodolumineszenz aufgenommen 

wurde. Eine LED-Struktur mit einem pn-Übergang 

oberhalb des Netzwerkes lässt bei Flusspolung von 

1-1,5 V eine Versetzungsstrahlung bei 1,55 µm bzw. 

1,3 µm erwarten. 


Materialien 

ration with the MPI for Microstructure Physics, Halle 

that a specific misorientation allows the formation of 

a network at which only the D1 radiation appears with 

an efficiency of a few percent (IEDM Techn. Digest 

2005). Here, we demonstrate the dominance of D3 

radiation (1.3 µm) from another network, see Fig. 38. 

A LED emitting efficiently at RT could be produced if a 

proper dislocation network is closely located to a p-n 

junction, with a forward bias of 1-1.5 V. 

Intensity (a.u.) 

0.7 0.8 0.9 1.0 1.1 1.2 

Energy (eV) 


D3 @ 1.3 µm 

Materials 

Abb. 38: Das Spektrum zeigt die dominierende D3-Emission eines 

durch Direktbonden von Silizium-Wafer geschaffenen Versetzungsnetzwerkes 

Fig. 38: Spectrum with dominating D3 emission of a dislocation 

network formed by Si wafer direct bonding. 


Gemeinsames Labor IHP/BTU 

IHP/BTU Joint Lab

Das Gemeinsame Labor IHP/BTU auf dem Campus 

der Brandenburgischen Technischen Universität (BTU) 

Cottbus besteht seit 2000. Es bündelt die Forschungspotentiale 

beider Partner und leistet – unter massgeblicher 

Einbeziehung von Studenten – interdisziplinäre 

Forschung auf den Gebieten Halbleitermaterialien, 

Theoretische Physik, Physikalische Chemie, Systeme, 

Schaltungen und Mikroelektronik. Seit 2005 ist auch 

die Fachhochschule Senftenberg mit dem Gemein- 

samen Labor assoziiert. Weiter wurde die BTU über 

das Gemeinsame Labor als Mitglied in das internationale 

Konsortium SiWEDS (Silicon Wafer Engineering 

& Defect Science Center, siehe www.mse.ncsu.edu/ 

siweds/) aufgenommen, dem renommierte Halbleiterfirmen, 

wie z.B. Texas Instr., Toshiba, Samsung, Siltronic 

AG, Centrotherm GmbH, und namhafte Universitäten, 

wie z.B. MIT, Stanford, UC Berkeley, angehören. 

Der Bund und das Land Brandenburg fördern im Rahmen 

des Hochschul- und Wissenschaftsprogramms 

HWP im Gemeinsamen Labor den Aufbau eines Kompetenzzentrums 

für Halbleitermaterialien und -technologien. 

In diesem Zusammenhang wird die Kernkompetenz 

des Gemeinsamen Labors „Maßschneidern der 

Eigenschaften des Silizium-Materials“ durch grund- 

lagenorientierte Vorlaufforschung weiter ausgebaut. 

Im Bewusstsein, dass die entwickelte Si-Technologie 

heute über breite Möglichkeiten verfügt und nach neuen 

Anwendungen sucht, beteiligt sich das Gemeinsame 

Labor an Arbeiten, dem Silizium Eigenschaften „anzutrainieren“, 

die seinen künftigen Einsatz auf neuen zusätzlichen 

Einsatzfeldern gestatten soll. Basierend auf 

den Ergebnissen dieser Vorlaufforschung – zu der z.B. 

Si-basierte Lichtemitter, Si-basierte Nanostrukturen 

wie Schichtstapel c-Si/SiO 2 oder Si-Nanodrähte oder 

die kontrollierte Platzierung von Biomolekülen auf Si 

für Biochips zählen – werden für das IHP Entscheidungen 

für seine zukünftige inhaltliche Ausrichtung mit 

vorbereitet. 

Die langfristigen Forschungsschwerpunkte des Gemeinsamen 

Labors zum Komplex „Silizium“ sollen Beiträge 

liefern zur Weiterentwicklung der Mikroelektronik, 

zur Einführung einer Si-basierten Nanoelekronik, 

zur Einführung einer Si-basierten Photonik, zur Verknüpfung 

von Si mit der Biologie und zur Unterstützung 

der Si-basierten Photovoltaik. Auf dem letztgenannten 

Gebiet ist das Gemeinsame Labor in der 

BTU-Forschungeinrichtung CeBra (Centrum für Energietechnologie 

Brandenburg, siehe www.tu-cottbus. 

de/cebra/) verankert. 

Gemeinsames Labor 

IHP/BTU 


IHP/BTU Joint Lab 

The IHP/BTU Joint Lab located at the campus of the 

Technical University of Brandenburg Cottbus (BTU) 

was founded in the year 2000. It pools the research 

potentials of both partners and conducts interdisciplinary 

research – with substantial involvement of students 

– in the fields of semiconductor materials, theoretical 

physics, physical chemistry, systems, circuits 

and microelectronics. Since 2005, the nearby University 

of Applied Sciences Senftenberg is also an associated 

partner of the Joint Lab. Moreover, the BTU 

Cottbus was accepted via the IHP/BTU Joint Lab as a 

member of the international consortium SiWEDS (Silicon 

Wafer Engineering & Defect Science Center, see 

www.mse.ncsu.edu/siweds) associating noted semiconductor 

companies, e.g. Texas Instruments, Toshiba, 

Samsung, Siltronic AG, Centrotherm GmbH, and 

well-known universities such as MIT, Stanford and UC 

Berkeley. 

Within the framework of their university and science 

programs, the Federal Republic of Germany and the 

State of Brandenburg support the formation of a centre 

of expertise for semiconductor materials and technology 

at the Joint Lab. The work of the Joint Lab is 

directed towards strengthening its core competencies 

in the area of tailoring the properties of the Si material 

by conducting a fundamental cutting-edge research. 

Aware of the high capabilities of advanced Si technology 

and the constant search for new applications, the 

Joint Lab participates in research aimed at “training” 

the silicon material new properties that will enable its 

use in new application areas. The topics comprise e.g. 

Si-based light emitters, Si-based nanostructures such 

as c-Si/SiO 2 stacks or Si nanowires, and controlled 

placement of biomolecules on Si for future biochips. 

The results of this cutting-edge research will serve as 

a basis for decisions regarding the future research directions 

at the IHP. 

The long-term research topics of the Joint Lab in the 

field of silicon contribute to future trends in microelectronics, 

implementation of Si-based photonics, implementation 

of Si-based nanoelectronics, interfacing Si 

microelectronics with biology, and support for Si-based 

photovoltaics. With the latter research area, the Joint Lab 

is connected to the BTU research facility CeBra (Center 

for Energy Technology Brandenburg, see www.tu-cottbus.de/cebra/). 

63




Die Arbeiten zum Komplex „Silicium“ sind inhaltlich wie 

folgt strukturiert und werden im Rahmen von Projekten, 

großteils in Arbeitsteilung mit externen Partnern, 

verfolgt 

- Mikroelektronik 

Si für zukünftige Halbleitertechnologien 

(Forschungsvertrag mit Siltronic AG) 

Si-basierte Lichtemitter (Kooperation mit MPI Halle) 

Diagnostik für die Si-Material- und Technologieentwicklung 

- Nanoelektronik 

Bandstrukturdesign unter Nutzung von Si/SiO 2 – 

Schichtstapeln (BMBF-Projekt mit RWTH Aachen, 

HMI Berlin u.a.) 

Si-Nanodrähte (Kooperation mit Zhejiang Universität, 

Hangzhou, VR China) 

- Verknüpfung Si mit Biomolekülen 

Kontrollierte Platzierung von Biomolekülen auf Si 

(VW-Projekt mit MPI Halle, IPHT Jena, Universität 

Göttingen) 

- Photovoltaik 

Einfluß von Verunreinigungen auf die elektrische 

Wirkung von Kristalldefekten in Si (BMU-Projekt mit 

Deutsche Solar, Shell Solar, RWE Schott Solar, FhG 

ISE Freiburg u.a.) 

- Transport in Si-basierten Quantenstrukturen 

- Pulsed Laser Deposition 

Erzeugung von Nanostrukturen und Hoch-k-Mate- 

rialien 

Allein zu den den Halbleitermaterialien und -technologien 

sind im laufenden Jahr im Joint Lab gemeinsam 

mit der BTU 37 Publikationen veröffentlicht oder akzeptiert, 

60 Vorträge, darunter 13 eingeladene, gehalten 

worden und drei Patente angemeldet worden. Ein 

Vortrag auf der Internationalen DRIP-Konferenz in Beijing 

wurde mit dem ‚Best paper award for young scientist’ 

ausgezeichnet. 

Für die laufenden Projekte wurden im Jahr 2005 mehr 

als 500.000 Euro Drittmittel eingeworben. 

Eine wichtige Aufgabe stellt auch der Ausbau der internationalen 

Vernetzung des Gemeinsamen Labors dar. 

64 


The research activities within the complex ˝Silicon˝ 

are organized in the form of projects as stated below. 

Often, they are carried out in collaboration with external 

partners. 

- Microelectronics 

Si for future semiconductor technologies (research 

contract with Siltronic AG) 

Si-based light emitters (collaboration with MPI Halle) 

Diagnostics for Si materials and technology 

- Nanoelectronics 

Band structure design utilizing Si/SiO 2 stacks (joint 

project with RWTH Aachen, HMI Berlin and others, 

funding by Federal Ministry of Education and Research) 

Si nanowires (cooperation with Zhejiang University, 

Hangzhou, PR China) 

- Interfacing Si with biomolecules 

Controlled placement of biomolecules on Si (project 

together with MPI Halle, IPHT Jena, University 

Göttingen, funding by VW foundation) 

- Photovoltaics 

Influence of impurities on the electrical activity of 

crystal defects in Si (joint project with Deutsche 

Solar, Shell Solar, RWE Schott Solar, FhG ISE Freiburg 

and others, funding by Federal Ministry for 

the Environment, Nature Conservation and Nuclear 

Safety) 

- Transport in Si-based quantum structures 

- Pulsed Laser Deposition 

Fabrication of nanostructures and high-k materials 

In the year 2005, 37 joint publications, 43 oral contributions 

and posters, among them 12 invited presentations, 

and 3 patents originated from research on 

semiconductor materials and technologies in the Joint 

Lab together with the BTU. A contribution at the international 

conference DRIP 2005 in Beijing received the 

‚Best paper award for young scientists’. 

Third party funding of more than 500,000 Euro was 

obtained in 2005 for the current projects. 

The development of the international networking is 

an important task of the Joint Lab. Besides the membership 

in the SiWEDS consortium, the Joint Lab is

Neben der o.g. Mitgliedschaft im SiWEDS-Konsortium 

arbeitet das Joint Lab aktiv im Europäischen Netzwerk 

CADRES (Coordinated Action on Defects Related to Engineering 

Advanced Silicon Based Devices) mit. Hervorzuheben 

ist auch die Ausrichtung des 2nd Sino-German 

Symposium „The Silicon Age“ in Cottbus oder die 

Mitwirkung in internationalen Konferenzkomitees (z. B. 

für die Internationale GADEST 2005 in Frankreich). 

Das Gemeinsame Labor unterstützt das Lehrangebot 

der BTU mit Vorlesungen, Übungen und Praktika. Im 

Jahr 2005 wurden je eine Habilitations- und Doktorarbeit 

von Mitgliedern des Gemeinsamen Labors verteidigt 

sowie zwei Diplomarbeiten und eine Bachelorarbeit 

abgeschlossen. Die Doktorarbeit wurde in 2005 

mit dem Förderpreis 2005 der Deutschen Gesellschaft 

für Elektronenmikroskopie geehrt. 

Weiterführende Informationen über das Gemeinsame 

Labor sind unter www.jointlab.de abrufbar. 




actively working in the European networking action 

CADRES (Coordinated Action on Defects Related to 

Engineering Advanced Silicon Based Devices). The organization 

of the 2nd Sino-German Symposium ˝The 

Silicon Age˝ in Cottbus and the participation in international 

conference committees (e.g. GADEST 2005 

in France) have to be pointed out as well. 

The Joint Lab supports the education at the BTU Cottbus 

by lectures, exercises and practical courses. In 

2005, a state doctorate and a PhD thesis were defended 

by members of the Joint Lab and two diploma theses 

and one bachelor thesis were finished. The PhD 

thesis was awarded the Prize 2005 of the Deutsche 

Gesellschaft für Elektronenmikroskopie. 

For further information about the Joint Lab please visit 

the website www.jointlab.de. 


Konferenzen und Workshops 

Conferences and Workshops

Fachsymposium „Anorganische Dielektrika für 

die künftige Mikro- und Nanotechnologie“ des 

DPG-Fachverbandes „Dünne Schichten“ im Rahmen 

der 69. Jahrestagung der Deutschen Physikalischen 

Gesellschaft, 5. März 2005, Berlin. 

In dem Symposium wurden neue dielektrische Materialien 

für die Integration in bestehende Technologien diskutiert. 

Im Zentrum standen Hoch-k-Dielektrika, die aufgrund 

ihrer Eigenschaften z. B. größere Schichtdicken 

für hochskalierte Transistoren zulassen und somit die bei 

Nutzung herkömmlicher Dielektrika sehr geringer Dicke 

entstehenden hohen Leckströme verringern. 

Das Fachsymposium wurde gemeinsam von Mitarbeitern 

des IHP und der BTU Cottbus organisiert. 

Vierter Internationaler Sommerstudiengang 

zur Mikroelektronik, 25. Juli – 5. August 2005, 

Frankfurt (Oder). 

Inhaltlicher Schwerpunkt der Veranstaltung war auch 

im Jahr 2005 die drahtlose Kommunikation. Das Spektrum 

der Vorträge reichte von Mikrosystemtechnologien 

über Architekturen für Hochfrequenzschaltungen bis zu 

drahtlosen Internetanwendungen. Zu der Veranstaltung 

wurden zwanzig Studenten der Mikroelektronik aus ganz 

Mittel- und Osteuropa nach Frankfurt (Oder) eingeladen. 

Hier trafen sie auf zwanzig Mitarbeiter regionaler Unternehmen 

und zehn Experten, die zu den neuesten Trends 

in der Mikroelektronik referierten. 

Der Sommerstudiengang wurde gemeinsam veranstaltet 

vom Kompetenzzentrum Mikroelektronik Frankfurt 

(Oder), der Europa-Universität Viadrina und dem IHP. 

Zweites Chinesisch-deutsches Symposium „The 

Silicon Age”, 19. – 24. September 2005, Cottbus. 

Die Themen des Symposiums waren mit der Mikroelektronik, 

Photovoltaik, Optoelektronik und Bioelektronik aktuelle 

Gebiete, auf denen die beteiligten deutschen und 

chinesischen Partner auch wissenschaftlich zusammenarbeiten. 

Das Symposium wurde vom chinesisch-deutschen 

Zentrum für Wissenschaftsförderung in Peking gefördert, 

das von der NSF China und der DFG betrieben wird. Die 

Ausrichtung erfolgte durch das IHP und das IHP/BTU Joint 

Lab. Das erste Symposium fand vor drei Jahren in Hangzhou 

statt. 

Konferenzen 

und Workshops 


Conferences 

and Workshops 

Specialized Symposium “Inorganic Dielectrics 

for the Future Micro- and Nanotechnology” of 

the DPG Scientific Section “Thin Layers” in the 

framework of the 69 th Annual Meeting of the 

Deutsche Physikalische Gesellschaft, March 5, 

2005, Berlin. 

In the symposium, new dielectric materials for the integration 

in existing technologies were discussed. The focus 

was based on high-k-dielectrics, which, due to their 

characteristics, permit for example big layer thickness 

for high-scaled transistors and thus, they reduce the 

high leakage currents produced by the use of usual dielectrics 

of very low thickness. 

The specialized symposium was jointly organized by employees 

of the IHP and the BTU Cottbus. 

Fourth International Summer School for Microelectronics, 

July 25 – August 5, 2005, Frankfurt 

(Oder). 

Content wise, the focus of the meeting was also in 2005 

Wireless Communication. The spectrum of the lectures 

included Micro System Technologies across architectures 

for high frequency circuits up to wireless Internet 

applications. Twenty Microelectronics students from the 

whole of Central and Eastern Europe were invited for the 

meeting in Frankfurt (Oder). Here, they met with twenty 

employees of regional firms and ten experts, who referred 

them to the latest trends in microelectronics. 

The summer school was jointly organized by the Competence 

Centre Microelectronics Frankfurt (Oder), the 

European University Viadrina and the IHP. 

Second Sino-German Symposium “The Silicon 

Age”, September 19 – 24, 2005, Cottbus. 

Themes of the symposium were microelectronics, photovoltaics, 

optoelectronics and bioelectronics. The participating 

German and Chinese partners also collaborate 

scientifically in these fields. 

The Symposium was sponsored by the Sino-German 

Center for Promotion of Sciences in Peking, operated 

by the NSF China and the DFG. The IHP and the IHP/BTU 

Joint Lab orientated the symposium. The first symposium 

was organized three years ago in Hangzhou. 

67

Konferenzen 

und Workshops 

68 

Conferences 

and Workshops 

Das Symposium wurde von Mitarbeitern des IHP und der 

Zhejiang Universität Hangzhou (China) organisiert. 

Vierter IHP-Workshop „High-Performance SiGe:C 

BiCMOS for Wireless and Broadband Communication”, 

21. September 2005, Frankfurt (Oder). 

Auf diesem Kundenworkshop informierte das IHP über 

seine neuesten Forschungsergebnisse. Schwerpunkte 

waren die BiCMOS-Technologien und deren Verfügbarkeit 

für MPW & Prototyping sowie neueste Hochfrequenzschaltungen. 

Sechzig Vertreter von 25 Firmen und wissenschaftlichen 

Einrichtungen, insbesondere aus Deutschland und Europa, 

nutzten das Treffen, um sich über die aktuellen Forschungsarbeiten 

des IHP zu informieren. 

Der Workshop wurde durch das IHP organisiert und 

durchgeführt. 

Tutorial „IHP Design Kits“, 22. – 23. September 

2005, Frankfurt (Oder). 

Im Anschluß an den Workshop vom 21. September fand 

ein zweitägiges Tutorial statt, bei dem die Teilnehmer 

die für die Nutzung der IHP-Technologien notwendigen 

Spezialkenntnisse erlernen bzw. vertiefen konnten. 

Die Veranstaltung wurde vom IHP organisiert und durch 

die advICo GmbH durchgeführt. 

Workshop „Drahtlose Kommunikationstechnologien“, 

29. Juni 2005, Frankfurt (Oder). 

Auf diesem Workshop wurden aktuelle Forschungsprojekte 

des IHP und der TFH Wildau zum Thema drahtlose 

Kommunikationstechnologien vorgestellt. Teilnehmer 

waren vorrangig Vertreter der regionalen Industrie sowie 

regionaler Hoch- und Fachhochschulen. 

Der Workshop wurde zusammen vom IHP und der Wissens- 

und Technologietransferstelle in Frankfurt (Oder) 

organisiert. 


The symposium was jointly organized by employees of 

the IHP and the Zhejiang University Hangzhou (China). 

IHP‘s 4 th Workshop “High-Performance SiGe:C 

BiCMOS for Wireless and Broadband Communication”, 

September 21, 2005, Frankfurt (Oder). 

In this customer workshop, the IHP informed about its 

latest research results. Main topics were the BiCMOS- 

Technologies of the IHP and their availability for MPW & 

Prototyping as well as latest RF circuits. 

60 representatives from 25 firms and scientific institutions, 

especially from Germany and Europe, used in this 

occasion the opportunity to inform themselves about 

most up-to-date research works of the IHP. 

The workshop was organized and realized by the IHP. 

Tutorial “IHP Design Kits“, September 22 – 23, 

2005, Frankfurt (Oder). 

A two days tutorial took place as a continuation of the 

workshop on September 21st, in which the participants 

learned and reinforced the special knowledge necessary 

for the utilization of the IHP Technologies. 

The meeting was organized by the IHP and realized by 

the advICo GmbH. 

Workshop “Wireless Communication Technologies“, 

June 29, 2005, Frankfurt (Oder). 

In this workshop, actual research projects of the IHP and 

the TFH Wildau with main theme “Wireless communication 

technologies” were introduced. Participants were 

mainly representatives of regional industries as well as 

from Universities and Technical colleges. 

The workshop was organized together by the IHP and 

the Science and Technology Transfer Position in Frankfurt 

(Oder).

11. GADEST Konferenz, 25. – 30. September 2005, 

Giens, Frankreich. 

Diese internationale Konferenz ist ein Forum für die 

Wechselwirkung zwischen Halbleiter-Defektphysik, Materialforschung 

und Technologie. Ein besonderer Schwerpunkt 

der Tagung in diesem Jahr waren Probleme des 

Siliziums, von der Mikroelektronik bis zur Photovoltaik. 

Diese Tagung wurde vor zwanzig Jahren durch das IHP 

ins Leben gerufen und findet seit dem im Abstand von 

zwei Jahren statt, seit 1997 in verschiedenen europäischen 

Ländern. 

1 st Leibniz-Conference of Advanced Science (Nanoscience 

2005), 06. – 08. Oktober 2005, Lichtenwalde. 

Die Konferenz lud zum Dialog unter dem Begriff „Nanoscience“ 

ein. Schwerpunkte waren Nanoeffekte (vorrangig 

bezogen auf Elektronik, Photonik und Biologie), Nanomaterialien 

und Nanosysteme. 

Veranstalter dieser Konferenz waren das Leibniz-Institut 

für interdisziplinäre Studien e.V. (LIFIS), das IHP Frankfurt 

(Oder) und die Leibniz-Sozietät Berlin e.V. 

Workshop „SiGe Technologies for Radio Frequency 

Applications”, 24. November 2005, Moskau. 

Auf dem Workshop wurden die neuesten Ergebnisse der 

technologischen Forschungen des IHP sowie Hochfrequenzschaltungen 

unter Nutzung von IHP-Technologien 

vorgestellt. Teilnehmer waren zahlreiche Mitarbeiter russischer 

Firmen, Hochschulen und Forschungseinrichtungen 

auf dem Gebiet der Elektronik. 

Die Veranstaltung wurde gemeinsam vom Moskauer Forschungsinstitut 

„Progress“ und dem IHP organisiert. 

60-GHz-Workshop, 13. Dezember 2005, Berlin. 

Gegenstand des im Fraunhofer HHI durchgeführten 

Workshops waren Forschungsvorhaben zum Hochfrequenz-Design 

und zu verschiedenen Applikationen im 

Frequenzbereich 60 GHz. 

Der Workshop wurde gemeinsam vom Fraunhofer HHI, 

der TU Berlin und dem IHP organisiert und durchgeführt. 

Konferenzen 

und Workshops 

Conferences 

and Workshops 

11 th GADEST Conference, September 25 – 29, 

2005, Giens, France. 

This international conference is a forum for the interaction 

between semiconductor defect physics, materials 

research and technology. The conference in this year 

focused especially on silicon problems, from microelectronics 

to photovoltaics. 

This conference was initiated 20 years ago by the IHP 

and takes place every two years, since 1997 in different 

European countries. 

1 st Leibniz Conference of Advanced Science (Nanoscience 

2005), October 6 – 8, 2005, Lichtenwalde. 

The participants of the conference were invited to dialogue 

on the notion “Nanoscience“. Main topics were 

nano effects (priority drawn from electronics, photonics 

and biology), nano materials and nano systems. 

Organizers of this conference were the Leibniz Institute 

for Interdisciplinary Studies e.V. (LIFIS), the IHP Frankfurt 

(Oder) and the Leibniz Society, Berlin e.V. 

Workshop “SiGe Technologies for Radio Frequency 

Applications”, November 24, 2005, Moscow. 

Latest results of the technological researches of the IHP 

as well as RF circuits under utilization of IHP-Technologies 

were discussed in this workshop. Participants were 

numerous employees from Russian firms, universities 

and research institutes in the field of electronics. 

The workshop was jointly organized and realized by the 

Moscow Research Institute “Progress” and the IHP. 

60 GHz Workshop, December 13, 2005, Berlin. 

Subject of the workshop organized in the Fraunhofer 

HHI were research projects of the high frequency design 

and the different applications in the frequency range 

60 GHz. 

The workshop was jointly organized and realized by the 

Fraunhofer HHI, the TU Berlin and the IHP. 


Zusammenarbeit und Partner 

Collaboration and Partners

Industrie/Industry * 

ABS GmbH, Germany 

ACCESS e.V. Aachen, Germany 

AdMOS GmbH, Germany 

advICO microelectronics GmbH, Germany 

Airbus Deutschland GmbH, Germany 

AIXTRON AG Germany 

Alcatel SEL AG, Germany 

Applied Wave Research, USA 

Ascom Systec AG, Switzerland 

Astron, The Netherlands 

Atmel Germany GmbH, Germany 

Baolab Microsystems, S.L., Spain 

Centellax Inc., USA 

centrotherm GmbH & Co. KG, Germany 

CoreOptics GmbH, Germany 

DaimlerChrysler Research Centre, Germany 

Deutsche Solar AG, Germany 

EADS Radio Communication Systems GmbH & Co. KG, 

Germany 

EDA Solutions, UK 

Enpirion Inc., USA 

European Space Research & Technology Centre, The 

Netherlands 

Freescale Semiconductor Germany GmbH, Germany 

Gaisler Research, Sweden 

Genesys Ltd., Ukraina 

GWT-TUD GmbH, Germany 

IMST GmbH, Germany 

Infineon Technologies AG, Germany 

InnoSenT GmbH, Germany 

Institute for Solar Energy Research GmbH, Germany 

* Ausgewählte Partner/ Selected partners 

Zusammenarbeit 

und Partner 

Kayser Threde GmbH, Germany 

KMSD, Lithuania 

KOTURA Inc., USA 

Leica Camera AG, Germany 

lesswire AG, Germany 

MEDAV GmbH, Germany 

MergeOptics, Germany 


Mikroelectronic Arastirma, Turkey 

Collaboration 

and Partners 

Nokia Research Centre, GermanyNTLab, Belarus 

Phasor Solutions, UK 

Philips Electronics Nederland B.V., The Netherlands 

Philips Electronics Ltd., UK 

Philips Research Laboratories Aachen, Germany 

Robert Bosch GmbH, Germany 

RWE Schott Solar GmbH, Germany 

Sennheiser electronic GmbH & Co. KG, Germany 

Siemens AG, Austria 

Siemens AG, Germany 

Signalion GmbH, Germany 

Siltronic AG, Germany 

StrataLight Communications, USA 

STMicroelectronics N.V., The Netherlands 

Tanner Research Inc., USA 

Telefunken Radio Communication Systems GmbH & 

Co. KG, Germany 

TES Electronic Solutions GmbH, Germany 

TES Electronic Engineering GmbH, Germany 

Texas Instruments GmbH, Germany 

T-Systems Nova GmbH, Germany 

Winfinity GmbH, Germany 

X-FAB Semiconductor Foundries AG, Germany 

71


und Partner 

72 

Collaboration 

and Partners 

Forschungsinstitute und Universitäten/Research Institutes and Universities 

Australia Telescope National Facility, Australia 

CSEM Centre Suisse d’Electronique et de Microtechnique, 

Switzerland 

Delft University of Technology, The Netherlands 

ETH Zurich, Switzerland 

European Synchrotron Radiation Facility, France 

European University Viadrina of Frankfurt (Oder), 

Germany 

Fraunhofer IIS, Germany 

Fraunhofer IPMS, Germany 

Fraunhofer ISE, Germany 

Fraunhofer HHI, Germany 

Freie Universität Berlin, Germany 

Friedrich-Alexander-University Erlangen-Nuremberg, 

Germany 

Georg-August-University of Göttingen, Germany 

Georgia Institute of Technology, USA 

Hangzhou Dianzi University, China 

Humboldt University of Berlin, Germany 

Imperial Collage of London, UK 

Indian Institute of Technology, Kharagpur, India 

Institute of Computer Science, ICS-FORTH, Greece 

Institute for Physical High Technology, Germany 

Institute for System Level Integration, UK 

Instituto de Telecomunicacoes, Portugal 

John von Neumann Institute for Computing, Germany 

KTH Stockholm, Sweden 

London South Bank University, UK 

Ludwig-Maximilians-University of Munich, Germany 

Max Planck Institute of Microstructure Physics, Germany 

Moscow Engineering Physics Institute (State University), 

Russia 

National Electronics and Computer Technology Centre, 

Thailand 

Paul Drude Institute for Solid State Electronics, Germany 

Politecnico di Torina, Italy 

Progress Microelectronics Research Institute, Russia 

RadioLabs, Italy 

RWTH Aachen, Germany 

Saint-Petersburg State University, Russia 

* Ausgewählte Partner/Selected partners 

Sino German Science Centre, China 


Technical University Bergakademie Freiberg, Germany 

Technical University of Berlin, Germany 

Technical University of Brandenburg, Germany 

Technical University of Braunschweig, Germany 

Technical University of Chemnitz, Germany 

Technical University of Dresden, Germany 

Technical University of Ilmenau, Germany 

Technical University of Istanbul, Turkey 

Technical University of Munich, Germany 

Technical University of Ukraina, Ukraina 

TIMA Laboratory, France 

Tohoku University Sendai, Japan 

Universidade de Aveiro, Portugal 

Universidade de Las Palmas de Gran Canaria, Spain 

University of Applied Sciences Aalen, Germany 

University of Applied Sciences Wildau, Germany 

University of Bergen, Norway 

University of Bremen, Germany 

University of Bristol, UK 

University of California, USA 

University of Cantabria, Spain 

University of Chicago, USA 

University of Florence, Italy 

University of Glasgow, UK 

University of Karlsruhe, Germany 

University of Kassel, Germany 

University of Konstanz, Germany 

University of Limerick, Ireland 

University of Malta, Malta 

University of Manchester, UK 

University of Nottingham, UK 

University of Osnabrück, Germany 

University of Oulu, Finland 

University of Paderborn, Germany 

University of Potsdam, Germany 

University of Rome, Italy 

University of Stuttgart, Germany 

University of Toronto, Canada 

University of Ulm, Germany 

Zhejiang University, Zhedalu, China 

*


und Partner 

Professor Dr. Wolfgang Mehr mit Studenten der Technischen Fachhochschule Wildau während des Praktikums am IHP. 

Professor Wolfgang Mehr with students of the University of Applied Sciences Wildau during the practical course at the IHP. 

Collaboration 

and Partners 


Gastwissenschaftler und Seminare 

Guest Scientists and Seminars

Gastwissenschaftler 

und Seminare 

Gastwissenschaftler/ Institution/Institution Forschungsgebiet/ 

Guest Scientist Research Area 

1. Mr. A. Chakravorty Indian Institute of Technology Materials Research 

Kharagpur, India 

2. Dr. I. Costina Max Planck Institute for Metals Research, Process Technology 

Stuttgart, Germany 

3. Dr. C. Dubourdieu Laboratory of Materials and the Physical Materials Research 

Genius (LMGP/ENSPG), France 

4. Mr. O. Dudnyk Genesis Ltd., Kiev, Ukraina Systems 

5. Prof. B. Glück University of Apllied Sciences Lausitz, Materials Research 

Senftenberg, Germany (Joint Lab) 

6. Mr. O. Gromovyy Institute of Semiconductor Physics, Process Technology 

Kiev, Ukraina 

7. Mr. M. Grudanov Genesis Ltd., Kiev, Ukraina Systems 

8. Mr. S. Mahapatra Indian Institute of Technology, Process Technology 

Bombay, India 

9. Mr. K. Maharatna University of Bristol, UK Systems 

10. Dr. A. U. Mane Humboldt Research Fellowship Process Technology 

11. Prof. J. Murota Tohoku University, Sendai, Japan Process Technology 

12. Mr. W. Post University of Duisburg-Essen, Germany Process Technology 

13. Dr. S. Virko Institute of Semiconductor Physics, Process Technology 

Kiev, Ukraina 

14. Prof. O. F. Vyvenko St. Petersburg State University, Russia Materials Research 

(Joint Lab) 


Guest Scientists 

and Seminars 

75


und Seminare 

76 


and Seminars 

Vortragender/Presenter Institution/Institution Topic/Thema 

1. Dr. M. Alexe Max Planck Institute of Microstructure “Epitaxial Ferroelectric Films“ 

Physics, Halle, Germany 

2. Prof. F. F. Bier Fraunhofer Institute for Biomedical “Biochips and BioMEMS for Analytics 

Engineering IBMT, Potsdam, Germany and Medical Diagnostics“ 

3. Prof. C. Boit Technical University of Berlin, Germany “Modern Functional Analysis and FIB 

Editing of ICs Through Si Backside” 

4. Dr. A. Blumenau Max-Planck-Institut für Eisenforschung, “The Modelling of Extended Defects 

Düsseldorf, Germany in Semiconductors“ 

5. Mr. C. Dubourdieu Laboratory of Materials and the Physical “Pulsed Liquid-injection MOCVD of 

Genius (LMGP/ENSPG), France High-K Oxides for Advanced Micro- 

electronic Applications“ 

6. Dr. Ch. Heer Infineon Technologies AG, Munich, Germany “Technical and Economical Challen- 

ges for Library and IP Development 

in Leading Edge CMOS Technologies“ 

7. Dr. G. Kannen, Fraunhofer Patent Center for German “Utilization of Patent Rights – Con- 

RA N. Schmeisser Research, Munich, Germany tract Strategies for Research Coope- 

rations with the Industry“ 

8. Dr. P. S. H. Leather Fizzle Technologies Ltd., Formby, UK “From the Very Front End to the Front 

End: Some of the Radio Frequency 

Requirements for MIMO Terminals“ 

9. Dr. S. Mahapatra Indian Institute of Technology, Bombay, “Negative Bias Temperature Instabi- 

India lity (NBTI) in CMOS Devices“ 

10. Dr. T. Mchedlidze Linköping University, Sweden “Novel Si Technologies – New Defects“ 

11. Dr. W. Post University of Duisburg-Essen, Germany “Tunnel Diodes on Silicon Substrates – 

Devices, Circuits and Application 

Potential“ 

12. Dr. K. Pressel Infineon Technologies AG, Regensburg, “High Frequency Packaging: Status 

Germany and Future Prospects“ 

13. Dr. M. Schmidt Hahn-Meitner Institute, Berlin, Germany “Heterostructures – Basis for Effi- 

cient Solar Cells“ 

14. Ph. D. T. Suligoj University of Zagreb, Croatia “Advanced BiCMOS Technology 

Based on the Vertical/Pillar-like 

Structures“ 

15. Dr. E. Suvar Royal Institute of Technology, “Epitaxy Development with ASM 

KTH Stockholm, Sweden Epsilon“ 

16. Prof. A. Wolisz Technical University of Berlin, Germany “Sensor Networks: A Hype or a Real 

Challenge?“ 

17. Dr. M. Zacharias Max Planck Institute of Microstructure Physics, “Charge Storage in Si Nanocrystal 

Halle, Germany Based MOS Structures“ 

J A H R E S B E R I C H T 2 0 0 5 | I H P A N N U A L R E P O R T


und Seminare 


and Seminars 


Publikationen 

Publications

Area Efficient Hardware Implementation of Elliptic Curve Cryptography by 

Iteratively Applying Karatsuba’s Method 

Zoya Dyka and Peter Langendoerfer 

IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany 

Abstract 

Securing communication channels is especially needed in 

wireless environments. But applying cipher mechanisms in 

software is limited by the calculation and energy resources 

of the mobile devices. If hardware is applied to realize 

cryptographic operations cost becomes an issue. In this 

paper we describe an approach which tackles all these three 

points. We implemented a hardware accelerator for 

polynomial multiplication in extended Galois fields (GF) 

applying Karatsuba’s method iteratively. With this 

approach the area consumption is reduced to 2.1 mm 2 in 

comparison to. 6.2 mm 2 for the standard application of 

Karatsuba’s method i.e. for recursive application. Our 

approach also reduces the energy consumption to 60 per 

cent of the original approach. The price we have to pay for 

these achievement is the increased execution time. In our 

implementation a polynomial multiplication takes 3 clock 

cycles whereas the recurisve Karatsuba approach needs 

only one clock cycle. But considering area, energy and 

calculation speed we are convinced that the benefits of our 

approach outweigh its drawback. 

Key words: Extended Galois fields, polynomial 

multiplication, Elliptic Curve Cryptography, Karatsuba’s 

formula. 

1. Introduction 

Motivation Mobile devices are penetrating our every day 

life. More and more sensitive information is exchanged 

between mobile nodes and between mobile and fixed 

communication endpoints. This data exchange is normally 

protected by cipher mechanisms. But due to the scarce 

resources of mobile nodes, exhaustive use of cryptographic 

means is infeasible. This holds especially true for public key 

cryptography, which is normally used to establish a secure 

channel between the communicating parties as well as for 

Nachdrucke 

ausgewählter Publikationen 

langendoerfer@ihp-microelectronics.com 

providing digital signatures. Hardware accelerators for 

public key cryptography operations are ideal means to reduce 

the calculation time as well as the energy consumption. But, 

a straight forward realization of cryptographic operations 

results in a relatively large area consumption, which makes 

the application of hardware accelerators economically 

infeasible. Thus, our design constraints were: 

• Calculation time, 

• Energy consumption, and 

• Area consumption. 

Reprints of 

Selected Publications 

We decided to use Elliptic Curve Cryptography (ECC) since 

it guarantees the same security level as RSA does but with 

significant shorter keys. In addition to this the ECC 

operations are faster than those of RSA [1]. We selected B- 

233 over Galois field GF(2 233 ) which is recommended by 

NIST [2] and well suited to be implemented in hardware. 

Despite ECC is less computational intensive than RSA it still 

requires a significant effort in terms of energy and time. In 

this paper we concentrate on the area efficient realization of 

basic mathematical operations, which are used in ECC. 

ECC Background In order to calculate the product of two 

233 bit long operands, denoted ‘kP’. Here P is a point on an 

elliptic curve (EC) and k is a large number. The ‘kP’ 

multiplication is based on point doubling and point addition. 

All these EC point operations are based on addition, 

subtraction, squaring, multiplication and division in a chosen 

GF. The basic operations in GF(2 233 ) are addition, squaring, 

multiplication and division of polynomials. Addition of 

polynomials is equivalent to a bit-wise XOR operation. 

Squaring and multiplication require two steps: 

squaring/multiplication itself and reduction of the result. 

Reduction is done using so-called irreducible polynomials 

and it is a fast operation in GF(2 n ). The irreducible 


Nachdrucke 


80 

polynomial for B-233 is the trinomial: f ( x) 

= x ⊕ x ⊕1 

Division of polynomials usually is done in two steps: first 

identifying the inverse of the divisor using the irreducible 

polynomial, and second multiplying the inverse with the 

dividend. Multiplication and division of polynomials require 

the major part of the calculation time. 

In this paper we are concentrating on polynomial 

multiplication, since our long term goal is to implement a 

Montgomery multiplier for the ‘kP’ operation. The 

Montgomery method requires only one polynomial division 

for ‘kP’, so that the major effort comes from the 

multiplication. 

Contribution and structure of this paper In this paper we 

show that an iterative application of the Karatsuba method 

provides very good results with respect to the following 

three parameters: calculation time, area consumption and 

energy consumption. With our iterative hardware solution, 

the chip area needed to calculate the product of two 233 bit 

long operands, is 2.1 mm 2 whereas the standard application 

of Karatsuba’s method needs 6.2 mm 2 . Our approach also 

reduces the energy consumption to 60 per cent of the 

original approach. The price we have to pay for these 

achievements is the increased execution time. In our 

implementation a polynomial multiplication takes 3 clock 

cycles whereas the original one needs only one clock cycle. 

The rest of this paper is structured as follows. Section 2 

contains a short description of implemented methods. We 

propose to use the Karatsuba’s formula for polynomial 

multiplication iteratively. The detailed description of our 

approach is given in Section 3. Section 4 discusses the 

hardware realization of our approach and provides 

measurement results. We conclude the paper with a short 

discussion of our results and an outlook on further research 

steps. 

2. State of the art 

Reprints of 


In this section we describe methods for polynomial 

multiplication in polynomial basis. We implemented these 

methods and different combinations of them to realize our 

own approach and to benchmark our solution. 

1 n 

Note: In GF(2 ) addition and subtraction are XOR operations. Due to this 

and for simpler understanding of formulas we change the usual 

representation of polynomials � − 

= 

= 

1 n 

i 

( ) i 

i 0 

x a x 

n 

i 

A to A x ⊕ ai 

x 

i 

− 

= 

= 

1 

( ) 

. In 

0 

rest of this paper we denote XOR operation as ‘⊕’. The symbol ‘+’ means 

always an ordinary addition. 

233 

74 

1 . 

2.1. Polynomial multiplication 

The product of two polynomials 

i 

A x ⊕ a x 

− 

n 

( ) and B x ⊕ b x 

− 

= 1 

( ) 

n 

= 

i= 

1 

0 


i 

i= 

0 

2n 

2 

i 

is the polynomial: C( x) 

A( 

x) 

B( 

x) 

⊕ c x , 

− 

= ⋅ = 

where ci ak 

⋅bl 

, i.e.: 

= ⊕ 

k + l= 

i 

i 

i 

i= 

0 

c0 

= a0 

⋅b0 

c1 

= a1 

⋅b0 

⊕ a0 

⋅b1 

� 

cn−1 

= an−1 

⋅b0 

⊕ an− 

2 ⋅b1 

⊕�⊕ 

a0 

⋅bn 

−1 

� 

c2n−3 

= an−1 

⋅bn 

−2 

⊕ an− 

2 ⋅bn 

−1 

c2n− 

2 = an−1 

⋅bn 

−1 

(1) 

The straight forward implementation of formula (1) requires 

n 2 partial multiplication and (n-1) 2 XOR operations of partial 

products in order to calculate ci. All operands in formula (1) 

are only one-bit long. In case of using EC B-233 both 

polynomials A(x) and B(x) are 233-bit long. It means that in 

total 233 2 one-bit partial multiplications and 232 2 XOR 

operations are required. 

2.2. Karatsuba based methods 

Original Karatsuba’s method For polynomial 

multiplication with original Karatsuba method [3] both 

operands have to be fragmentized into two equal parts. If the 

length n of operands is odd, they have to be padded with 

leading ‘0’. So, operands can be written as 2 : 

A( 

x) 

= a 

n−1 

... a a 

1 

... a a 

n 

2 

n 

−1 

2 

1 0 

n 

2 0 

= a ⋅ x ⊕ a 

= a 

n−1 

... a 

n 

2 

⋅ x 

n 

2 

i 

⊕ a 

n 

−1 

2 

2 We denote as ai the i th bit and as a i the i th segment of operand A(x). 

... a a 

1 

0 

= 

(2)

The polynomial B(x) is represented in the same way. The 

Karatsuba’s formula for the product C(x)=A(x)�B(x) is 

C( 

x) 

= a 

0 

b 

0 

1 

⊕ 

1 

0 0 1 1 0 1 0 1 

[ a b ⊕ a b ⊕ ( a ⊕ a )( b ⊕ b ) ] ⋅ 

n 

⊕ a b ⋅ x 

i i 

In order to calculate the partial products a b Karatsuba’s 

formula can be applied recursively. In this case it requires 

log 2 3 1. 

58 

in total s = s partial multiplications, where s is the 

number of segments. This method can be used to speed up 

software as well as hardware implementations. Usually in 

software implementations the Karatsuba’s approach is 

applied until both operands have a size of one word. 

In Bailey and Paar [4] a new scheme how to apply 

Karatsuba’s idea was proposed. In this scheme the operands 

are divided into three parts. Throughout the rest of this 

paper we denote this method as Bailey’s method. It requires 

6 partial multiplications of n/3-bit long operands. This 

method can be combined with the original Karatsuba 

formula for operands, whose length is divisible by six. 

3. Iterative Application of the Karatsuba 

Approach 

The major point in our approach is to apply the original 

version Karatsuba’s method iteratively. We denote this as 

Iterative-Karatsuba method. The major benefits of this 

approach are: 

- a smaller area consumption of the hardware accelerators 

due to the fact that partial multiplications can be 

performed serially 

- a reduced number of XOR operations compared with 

the recursive variant of Karatsuba’s method. 

We explain our idea of the iterative application of 

Karatsuba’s formula using an example in which the 

operands are split up into four segments. First of all, we use 

the original Karatsuba formula to obtain the expression for a 

product, in which only 1-segment long operands for partial 

multiplication are used. 

So, at the beginning we have two operands, each of them 

4n-bit long. We fragment each operand into two 2n-bit long 

parts: 

3 

2 

A( 

x) 

= a a a a = a a ⋅ x 

3 2 1 0 3 2 

B( 

x) 

= b b b b = b b ⋅ x 

1 

0 

3 

2 

2n 

2n 

1 

0 

⊕ a a 

1 0 

⊕ b b 

The result of applying Karatsuba’s formula is: 

x 

n 

2 

⊕ 

(3) 

(4) 

Nachdrucke 


C( 

x) 

= a a ⋅b 

b 

⊕ 

3 2 3 2 

⊕ a a ⋅b 

b ⋅ x 

1 

0 

1 0 1 0 3 2 3 2 13 02 13 02 

[ a a ⋅b 

b ⊕ a a ⋅b 

b ⊕ a a ⋅b 

b ] ⋅ 

where 

13 

02 

13 


1 

0 

4n 

n 

⊕ 

02 

1 

3 

0 

x 

2n 

2 

⊕ 

(5) 

a a = a ⋅ x ⊕ a = ( a ⊕ a ) ⋅ x ⊕ ( a ⊕ a ) = 

1 n 0 3 n 2 1 0 3 2 

= ( a ⋅ x ⊕ a ) ⊕ ( a ⋅ x ⊕ a ) = a a ⊕ a a 

(6) 

and 

13 

02 

1 

0 

3 

2 

b b = b b ⊕ b b 

(7) 

Every 2-segments element is: a a = a ⋅ x ⊕ a . So, for 

each partial multiplication from (6) and (7) we use the 

Karatsuba’s formula again. The final result is given in 

formula (8). 

C( 

x) 

= a 

i 

3 3 6n 

2 2 3 3 23 23 5n 

⋅b 

⋅ x ⊕ ( a ⋅b 

⊕ a ⋅b 

⊕ a ⋅b 

) ⋅ x 

1 1 2 2 3 3 13 13 4n 

⊕ ( a ⋅b 

⊕ a ⋅b 

⊕ a ⋅b 

⊕ a ⋅b 

) ⋅ x ⊕ 

0 0 1 1 2 2 3 3 

⊕ ( a ⋅b 

⊕ a ⋅b 

⊕ a ⋅b 

⊕ a ⋅b 

⊕ 

01 01 02 02 13 13 23 23 

⊕ a ⋅b 

⊕ a ⋅b 

⊕ a ⋅b 

⊕ a ⋅b 

0123 0123 3n 

⊕ a ⋅b 

) ⋅ x ⊕ 

0 0 1 1 2 2 02 02 2n 

⊕ ( a ⋅b 

⊕ a ⋅b 

⊕ a ⋅b 

⊕ a ⋅b 

) ⋅ x ⊕ 

0 0 1 1 01 01 n 0 0 

⋅ ⋅ 

⋅ 

⋅ 

⊕ ( a 

b ⊕ a b ⊕ a 

j 

b 

i 

) ⋅ x 

n 

n 

⊕ a 

(8) 

Each of the operands is 1-segment long, so that the resulting 

partial product is (2n-1)-bit long. We denote the bits from n- 

i i i i 

1 to 0 of the product a ⋅ b as a b [ 0] 

and the bits from 2ni 

i 

1 to n as a b [ 1] 

: 

i 

i 

i 

i 

n 

i 

i 

Reprints of 


a ⋅ b = a b [ 1] 

⋅ x ⊕ a b [ 0] 

(9) 

Using the notation introduced in (9) we can represent 

formula (8) as given in table 1. 

j 

b 

⊕ 

⊕

Nachdrucke 


82 

Table1. Representation of formula (8) 

partial products segments of result 

a 0 �b 0 [0] ⊕ ⊕ ⊕ ⊕ 

a 0 �b 0 [1] ⊕ ⊕ ⊕ ⊕ 

a 1 �b 1 [0] ⊕ ⊕ ⊕ ⊕ 

a 1 �b 1 [1] ⊕ ⊕ ⊕ ⊕ 

a 2 �b 2 [0] ⊕ ⊕ ⊕ ⊕ 

a 2 �b 2 [1] ⊕ ⊕ ⊕ ⊕ 

a 3 �b 3 [0] ⊕ ⊕ ⊕ ⊕ 

a 3 �b 3 [1] ⊕ ⊕ ⊕ ⊕ 

(a 0 ⊕ a 1 )�( b 0 ⊕ b 1 ) [0] ⊕ ⊕ 

(a 0 ⊕ a 1 )�( b 0 ⊕ b 1 ) [1] ⊕ ⊕ 

(a 0 ⊕ a 2 )�( b 0 ⊕ b 2 ) [0] ⊕ ⊕ 

(a 0 ⊕ a 2 )�( b 0 ⊕ b 2 ) [1] ⊕ ⊕ 

(a 1 ⊕ a 3 )�( b 1 ⊕ b 3 ) [0] ⊕ ⊕ 

(a 1 ⊕ a 3 )�( b 1 ⊕ b 3 ) [1] ⊕ ⊕ 

(a 2 ⊕ a 3 )�( b 2 ⊕ b 3 ) [0] ⊕ ⊕ 

(a 2 ⊕ a 3 )�( b 2 ⊕ b 3 ) [1] ⊕ ⊕ 

(a 0 ⊕ a 1 ⊕ a 2 ⊕ a 3 )�( b 0 ⊕ b 1 ⊕ b 2 ⊕ b 3 ) [0] ⊕ 

(a 0 ⊕ a 1 ⊕ a 2 ⊕ a 3 )�( b 0 ⊕ b 1 ⊕ b 2 ⊕ b 3 ) [1] ⊕ 

C(x) 

= 

7 6 5 4 3 2 1 0 

c c c c c c c c 

All columns in table 1 which are nested under the topic 

‘segments of result’ in represent a certain segment c i . For 

each partial product two lines are given in Table 1, one line 

representing the lower (a x b x [0]), and a second one 

representing the upper part (a x b x [1]) of the product as 

specified above. The segment c i can be calculated by XOR- 

ing all lines in the table 1, which contain the symbol '⊕ ' in 

the column of c i . For example c 5 can be calculated as 

follows: 

c 5 =a 1 b 1 [1]⊕ a 2 b 2 [0]⊕ a 2 b 2 [1]⊕ a 3 b 3 [0]⊕ a 3 b 3 [1]⊕ 

((a 1 ⊕ a 3 )(b 1 ⊕ b 3 )[1])⊕ ((a 2 ⊕ a 3 )(b 2 ⊕ b 3 )[0]) (10) 

Each segment c i can be calculated iteratively i.e. step by 

0 0 

step as we calculate the partial products starting with a b 

0 1 2 3 0 1 2 3 

down to ( a a ⊕ a ⊕ a ) ⋅ ( b ⊕ b ⊕ b ⊕ b ) 

⊕ . We then start 

to calculate the segments of products using the already 

received results. For example: 

Step 1 Step 2 … 

0 

1 

2 

3 

4 

0 

0 

0 

0 

0 

0 

c = a b [ 0] 

0 

c = a b [ 0] 

⊕ a b [ 1] 

0 

c = a b [ 0] 

⊕ a b [ 1] 

0 

c = a b [ 0] 

⊕ a b [ 1] 

0 

c = a b [ 1] 

0 

0 

0 

0 

0 

0 

1 

2 

3 

4 

5 

1 

2 

3 

4 

1 1 

1 1 

c = c ⊕ a b [ 0] 

1 1 

1 1 

1 1 

c = a b [ 1] 

Reprints of 


1 1 

c = c ⊕ a b [ 0] 

⊕ a b [ 1] 

1 1 

c = c ⊕ a b [ 0] 

⊕ a b [ 1] 

1 1 

c = c ⊕ a b [ 0] 

⊕ a b [ 1] 

And so 

on to 

Step 9 


This iterative calculation of the C(x) reduces the area of our 

hardware multiplier. We need only one partial multiplier for 

1-segment long operands. After each new clock this 

multiplier delivers the next partial product. In that way the 

segments of product C(x) are collected. For the above given 

example this means after 9 clock cycles all segments contain 

the correct product of the polynomial multiplication. 

Additionally we exploit another ‘iterative possibility’: we do 

not need to calculate all segments of C(x) separately. We can 

use c 0 to determine c 1 after the first clock, c 1 for c 2 after 

second clock, and so on (see table 2). This iterative 

calculation reduces the number of XOR operations to 29 

compared to 42 XOR operations if the calculation of every 

c i is done separately. 

In a similar way we applied our iterative approach to 

Bailey’s method, which we call Iterative-Bailey throughout 

the rest of this paper. 

Table 2. Exact operation sequence of our hardware 

implementation of formula (8) 

clock obtained partial product sequence of operations 

1 pr = a 0 ⋅ b 0 c 0 = pr[0] 

c 1 = pr [1] 

2 pr = a 1 ⋅ b 1 c 1 = c 1 ⊕ c 0 ⊕ pr[0] 

c 2 = pr[1] 

3 pr = a 2 ⋅ b 2 c 2 = c 2 ⊕ c 1 ⊕ pr[0] 

c 3 = pr[1] 

4 pr = a 3 ⋅ b 3 c 3 = c 3 ⊕ c 2 ⊕ pr[0] ⊕ pr[1] 

c 7 =pr[1] 

5 pr = (a 0 ⊕ a 1 ) ⋅ (b 0 ⊕ b 1 ) c 6 = c 3 ⊕ c 2 

c 5 = c 3 ⊕ c 1 

c 4 = c 3 ⊕ c 0 ⊕ pr[1] 

c 3 = c 3 ⊕ c 7 ⊕ pr[0] 

c 2 = c 2 ⊕ pr[1] 

c 1 = c 1 ⊕ pr[0] 

6 pr = (a 0 ⊕ a 2 ) ⋅ (b 0 ⊕ b 2 ) c 3 = c 3 ⊕ pr[0] ⊕ pr[1] 

c 2 = c 2 ⊕ pr[0] 

c 4 = c 4 ⊕ pr[1] 

7 pr = (a 1 ⊕ a 3 ) ⋅ (b 1 ⊕ b 3 ) c 4 = c 4⊕ pr[0] ⊕ pr[1] 

c 3 = c 3 ⊕ pr[0] 

c 5 = c 5 ⊕ pr[1] 

8 pr = (a 2 ⊕ a 3 ) ⋅ (b 2 ⊕ b 3 ) c 3 = c 3 ⊕ pr[0] 

c 5 = c 5 ⊕ pr[0] 

c 4 = c 4 ⊕ pr[1] 

9 pr = (a 0 ⊕ a 1 ⊕ a 2 ⊕ a 3 ) ⋅ 

� (b 0 ⊕ b 1 ⊕ b 2 ⊕ b 3 ) 

c 6 = c 6 ⊕ pr[1] 

c 3 = c 3 ⊕ pr[0] 

c 4 = c 4 ⊕ pr[1] 

4. Hardware implementation 

In this section we will present the design and the key 

parameters of our hardware realization of the Iterative 

Karatsuba approach.

The design of the Iterative Karatsuba accelerator consists of 

three major parts (see Fig. 1): 

• Selection block feeds certain parts of both operands 

into the Partial Multiplier, for each new clock 

signal. 

• Partial Multiplier block calculates the partial 

product of the operands delivered by the selection 

block and provides the results to the product 

accumulation block. 

• Product Accumulation block computes the final 

product from the partial products it receives from 

the partial multiplier. The theoretical basis and 

exact operation sequence is discussed in detail in 

Section 3. 

Figure 1: Block diagram of our Iterative-Karatsuba 

multiplier 

The performance, chip area and energy consumption of a 

polynomial multiplier are dominated by the partial 

multiplier which is used. The larger the input signals of the 

partial multiplier may be, the faster the partial multiplier is. 

But this also results in a relatively large area consumption. 

So, the design decision to make seems to be straight 

forward: calculation time versus chip area. This is true as 

long as only the partial multiplier is considered. But for the 

polynomial multiplier also the area of the selection and the 

product accumulation block have to be taken into account. 

The chip area needed for the accumulation block depends on 

the area of the partial multiplier in an inverse proportional 

manner, i.e. the smaller the partial multiplier the larger the 

accumulation block. This results from the fact that in case of 

small partial multipliers more intermediary results have to 

be stored for the final calculation of the polynomial product. 

For example the size of the accumulation block is 0,649 

mm 2 if the partial multiplier accepts 128 bit long operands, 

and 1,466 mm 2 if the maximum length of the operands is 32 

bits. 

In order to determine the most appropriate design for a 

polynomial multiplier we realized several partial multipliers. 

We realized 3 one-clock partial multipliers for our iterative 

Karatsuba as well as for our iterative Bailey approach. 

These partial multipliers accept operands with a maximal 

Nachdrucke 


length of 128, 64 and 32 bits respectively. They were 

synthesized with a library of our in-house 0.25 m CMOS- 

Technology [5]. Table 3 shows the area, the time and energy 

consumption for each of these six partial multipliers. These 

values stem from the Design analyzer tool from Synopsys 

[6]. 

Table 3. Parameters of synthesized partial 

multipliers 

Name of partial 

multiplier (PM) 

Length 

of input 

values, 

bits 

Area, mm 2 time, ns Energy/clock, 

pW s 

k128_k64_k32_k16_sh8 128 1.620410 12.53 1394.4000 

k64_k32_k16_sh8 64 0.514759 8.99 404.3913 

k32_k16_sh8 32 0.159006 5.62 108.2011 

p81_p27_sh9 81 0.896391 7.98 692.0033 

p39_sh13 39 0.264672 5.97 179.4565 

p27_sh9 27 0.133616 4.80 88.4779 

In order to benchmark our approach we realized polynomial 

multipliers using the following approaches: 

• Iterative Karatsuba 

• Iterative Bailey 

• Original Karatsuba (recursive) 

• Original Bailey (recursive) 

Reprints of 


For the first two approaches, i.e. for our own iterative 

approaches, we realized three polynomial multipliers using 

different partial multipliers (see table 3) in order to see how 

the partial multiplier influences the overall parameters. We 

named these multipliers so that the name indicates the 

applied method. For example, the name 

iterative_Karatsuba_8segments means: Iterative-Karatsuba 

fragmentizing incoming operands into 8 segments. 

In the two recursive multipliers the original Karatsuba and 

the Bailey formula are applied down to one-bit operands. 

Both multipliers deliver the polynomial product after one 

clock cycle. They differ in the length of the input operands. 

The Karatsuba multiplier expects always two 256 bit long 

input values whereas the Bailey multiplier expects two 243bit 

long input values. 

Since we are going to use these multipliers for EC B-233 the 

two input values will be only 233-bit long. Therefore the 

operands were padded with leading 0’s if it was necessary. 

The result of the multiplication is always 465-bit long. 

We synthesized all polynomial multipliers using a library of 

our in-house 0.25 m CMOS-Technology [5]. We obtained 

the data represented in these tables with different kinds of 

reports from the Synopsys “Design Analyzer” [6]. The 

parameters of the implemented polynomial multipliers are 


Nachdrucke 


84 

given in Table 4. Our results clearly indicate that an iterative 

application of the original Karatsuba and Bailey approach 

significantly reduces the chip area. If the number of 

iterations is kept small, our approach also helps to reduce 

the energy consumption. In those designs the decision is less 

area and less energy versus slower execution time. 

Increasing the number of iterations helps to reduce the chip 

area needed, but it also leads to an increased power 

consumption and an increased calculation time. So, these 

implementations are beneficial only if cost is the dominating 

parameter. 

Table 4. Parameters of synthesized polynomial 

multipliers 

Name of multiplier Area, 

iterative_Karatsuba_ 

2segments 

(PM - k128_k64_ 

k32_k16_sh8) 


4segments (PM - 

_k64_k32_k16_sh8) 


8segments 

(PM -_k32_k16_sh8) 

iterative_Bailey_ 

3segments 

(PM - p81_p27_sh9) 


6segments 

(PM - p39_sh13) 


9segments 

(PM - p27_sh9) 

recurcive_Karatsuba_ 

for_1clock 

recurcive_Bailey_ 

for_1clock 

Reprints of 


S, mm 2 

Number Period, Power, Energy, 

of T, ns P, mW E=T N P, 

clocks, 

N 

pW s 

2.18 3 15 98.89 4450.1 

1.52 9 10 105.48 9493.2 

1.67 27 9 107.63 26154.1 

2.12 6 10 148.16 8889.6 

1.60 18 9 110.46 17894.5 

1.71 36 9 103.35 33485.4 

6.28 1 19.35 326.15 6311.0 

7.02 1 16.94 441.75 7483.3 

5. Conclusions and Outlook 

In this paper we discussed the iterative application of 

Karatsuba’s method for polynomial multiplications as a 

means to reduce the chip area and energy needed to run 

elliptic curve cryptography on mobile devices. In order to 

evaluate our approach we analyzed different methods for 

polynomial multiplication in GF(2 n ), and implemented 

different polynomial multiplication algorithms. For our own 

approach we realized several partial multipliers. Weused 

them to implement a set of iterative polynomial multipliers 

with the goal to identify the one which is best suited for 

application in mobile devices. Our results clearly indicate 

that our iterative approach leads to significantly better 


results with respect to area and energy consumption than the 

original straight forward application. 

Our next step is the finalization of our Montgomery ‚kP’ 

multiplier. In this multiplier we will use the Fermat theorem, 

since it allows to determine the inverse for the division 

multiplication and squaring. The Fermat theorem is slower 

than the Extended Euklidian Algorithm or the method 

proposed by Shantz [7], but it requires less area. Since the 

Montgomery method requires only a single division, we 

think that the smaller area outweighs the slower 

performance. 

Acknowledgements 

This work was partially funded by the German Ministry of 

Education and Research under grant 01AK060B. 

References 

[1] Brown, M., Cheung, D., Hankerson, D., Hernandez, 

J.L., Kirkup, M., Menezes, A. (2000) PGP in 

Constrained Wireless Devices. Proceedings of the 9th 

USENIX Security Symposium, August 14 –17, 2000, 

Denver, Colorado, USA. USENIX Association, 

http://www.usenix.org/events/sec00/full_papers/brown 

/brown.pdf, last viewed October 6, 2003. 

[2] U.S. Department of Commerce/National Institute of 

Standards and Technology (NIST) (2000) Digital 

Signature Standard. FIPS PUB 186-2. Federal 

[3] 

Information Processing Standards Publication, 

http://csrc.nist.gov/publications/fips/fips186-2/fips186- 

2-change1.pdf, last viewed October 6, 2003. 

Karatsuba A.; Ofman Y. Multiplication of multidigit 

numbers by automata, Soviet Physics-Doklady 7, p. 

595-596, 1963 

[4] Bailey, D. V. and Paar, C. Efficient Arithmetic in 

Finite Field Extensions with Application in Elliptic 

Curve Cryptography. Journal of Cryptology, vol. 14, 

no. 3, 153–176. 2001 

[5] “Technology”, IHP (Innovations for High Performance 

microelectronics), http://www.ihp-ffo.de. 

[6] “Products & Solutions”, Synopsys, 

http://www.synopsys.com/products/logic/logic.html 

[7] A.Weimerskirch, C.Paar and S.C.Shantz (2001) 

Elliptic Curve Cryptography on a Palm OS Device. 

Proceeding of 6 th Australasian Conference on 

Information Security and Privacy (ACISP 2001), 11-13 

July 2001, Macquarie University, Sydney, Australia.

Abstract—In this paper, a low-complexity approximate 

channel inverse initialization scheme for blind equalization is 

proposed. The underlying idea is that the inverse of minimum 

phase finite impulse response (FIR) channels can be well 

approximated by inverting the most significant paths of the 

estimated channel impulse response (CIR). The parameters of 

the inverse of the truncated channel can be expressed in closedform 

expressions in terms of the original CIR and can be used to 

initialize adaptive equalizers. By applying time-reversal method, 

the proposed initialization scheme can also be applied for 

equalization of maximum phase channels. Through extensive 

computer simulations, we show that channels that cannot be 

equalized by blind equalizers with the conventional single-spike 

initialization can now be well equalized with the proposed 

initialization. 

Index Terms—Initialization, adaptive equalizer, inverse filter, 

least mean squares 

I 

I. INTRODUCTION 

NTERSYMBOL interference (ISI) degrades the performance 

of most of the wired and wireless digital communication 

systems, e.g. GSM, WLAN, fiber optical communications, 

and magnetic recording, etc. [1-3]. The complexity of the 

optimal equalization or maximum likelihood sequence 

estimator (MLSE) is growing as M L , where M is the alphabet 

size and L the channel length. Therefore, MLSE is prohibitive 

for many applications, especially for wireless 

communications. Suboptimal equalization techniques, e.g. the 

classical linear equalizer (LE) and decision feedback 

equalizer (DFE), has lower complexity which is linear in the 

channel length L, and independent of the alphabet size M. 

Direct computation of the optimal MMSE DFE filter 

coefficients requires accurate channel estimates and is 

computationally intensive [2]. For time-varying channels 

encountered in practice, direct calculation of parameters of 

LE or DFE needs to continuously updating the parameter and 

thus not practical. A practical low-complexity method to 

approach the optimal parameters of LE or DFE is to use 

either trained or blind adaptive algorithm [1] [5] [7] [8]. 

Nachdrucke 


Low-complexity Initialization of Adaptive 

Equalizers Using Approximate Channel Inverse 

Gang Wang and Rolf Kraemer 

IHP GmbH, Im Technologiepark 25 

D-15236 Frankfurt(Oder), Germany 

Phone: +49 335 5625 346; Fax: +49 335 5625 671 

Email: {gangwang, kraemer}@ihp-microelectronics.com 

However, adaptive equalizers using low-complexity 

adaptive algorithms, e.g. the least mean square (LMS) 

algorithm and the constant modulus algorithm (CMA), have 

slow convergence problem [1]; furthermore, the CMA may be 

trapped to local minima when improperly initialized. An 

efficient and effective way to solve the above problems is to 

find more accurate initial parameters for adaptive equalizers. 

In [3], a low-complexity initialization scheme for adaptive 

DFE with short feedforward filter was proposed. In [4], a 

power ratio approximation is used to estimate the initial 

parameters of adaptive equalizers. 

In this paper, we propose to use the approximate channel 

inverse to initialize adaptive equalizers. Considering the 

practical SNR in most cases is relatively high, we can 

reasonably say that it is ISI, rather than the noise, that 

severely degrades the receiver performance. 

The inverse of a minimum phase filter preserves the 

minimum phase property, which can be exploited to obtain a 

closed-form expression of the inverse filter coefficients. In 

addition, any maximum phase and nonminimum phase 

channels can be transformed to minimum phase by using 

time-reversal method and allpass filter, respectively. 

Therefore, the problem of initialization of an adaptive 

equalizer is reduced to a much simpler problem: to find a 

low-complexity method to calculate the initial channel 

inverse. Using long division method [6], we can get a closed 

form expression of the coefficients of the inverse channel 

filter in terms of the estimated CIR. Exploiting the property of 

minimum phase sequence, we can further simplify the result 

of the channel inverse and use it as initialization. 

The paper is organized as follows. Section II gives the 

system model. Section III presents the algorithm for 

initialization of adaptive equalizers. Section IV shows some 

simulation results. Finally, the paper is concluded in the last 

section. 

II. SYSTEM MODEL 

Reprints of 


We limit our discussion to packet transmission with linear 

modulation where the normal adaptive algorithms, e.g. CMA 


Nachdrucke 


86 

and LMS, tend to converge slowly. Consider an uncoded data 

transmission using linear modulation over discrete-time, 

symbol-spaced channel corrupted by additive white Gaussian 

noise (AWGN). The transmitted packet of data is denoted by 

N 

{ n} n= 

1 

x . The channel output at time n is given by 

K 

K 

r = � x h + η , (1) 

n n−k k n 

k = 0 

Reprints of 


where { h k} is the channel impulse response (CIR), K is the 

k = 0 

channel memory, and ηn is the nth sample of AWGN with 

single-sided power density of N0. 

We use both LE and DFE in the simulation. The LE is 

actually a transversal filter with N taps. A DFE consists of a 

F-tap feedforward filter (FFF), a B-tap feedback filter (FBF). 

From now on, the structure of a DFE is characterized by (F, 

B)-DFE. The taps of both LE and DFE can be adjusted using 

some adaptive algorithm, in this paper the LMS and CMA 

algorithm, to iteratively approach optimal MMSE solution 

and minimum dispersion solution, respectively. 

III. INITIALIZATION OF ADAPTIVE EQUALIZERS 

The multimodal cost surface of CM may exhibit local 

minima of varying cost, thus linking initialization to 

achievable asymptotic performance. This multimodality of the 

CM cost surface necessitates a good initialization to ensure 

convergence to a “good” local minimum as well as to avoid 

temporary local capture by saddle points. Practical 

initialization strategies for CMA equalizers are: single spike 

for baud-spaced CMA, double-spike for T/2-spaced CMA, 

and matched filter initialization for mild-ISI environments. 

The spike position within the CMA equalizer time span 

determines (asymptotic) system delay. Since the equalizer 

performance is significantly dependent on the system delay, 

the position of spike is very critical. 

For the LMS equalizer, the parameters are often initialized 

with all zeros. Another very important parameter to be 

estimated is the decision delay. Specifically, the choice of 

training delay bounds asymptotic LMS performance, and, in 

conjunction with the equalizer initialization, LMS time-toconvergence. 

The aforementioned relationship between 

initialization and channel group delays suggests that prior 

information about the channel may aid in estimation of both 

initialization and decision delay. 

Optimum MMSE channel equalization jointly reduces the 

effects of ISI and noise. Since the equalizing filter 

approximates the inverse of the channel, the equalizer usually 

requires a much longer filter length than the channel. For 

direct computation of a large number of parameters of MMSE 

equalizer, a heavy computational load is required. For 


adaptive calculation of a large number of parameters of 

MMSE equalizer, a slow convergence is induced. 

Since ISI caused by actual channels is of much greater 

importance than noise, we first neglect the noise term and 

reduce the equalization problem to inverse filtering problem, 

which is much simpler to solve. After we get an approximate 

channel inverse filter, we use adaptive algorithms, e.g. CMA 

and LMS, to approach the optimum MMSE solution and 

minimum dispersion solution, respectively. 

A. Channel Estimation 

A first step in our method is to estimate the overall channel 

impulse response. Both data aided and blind channel 

estimation can be performed before initialization of 

equalizers. For data aided case, we can inject several constant 

amplitude zero autocorrelation (CAZAC) sequences as 

preamble for trained channel estimation, and the initial CIR 

can be obtained by using the cyclic correlation method. 

When spectral efficiency is of the predominant concern, 

blind channel estimation can be conducted first, and the data 

received before the channel estimate converges is buffered; 

when steady channel estimate is ready, initialization start to 

be calculated. 

Since we use adaptive equalizers to track the time-varying 

channel response, channel estimate is only needed at the 

beginning of receiving process. 

B. Approximate Channel Inverse Initialization Algorithm 

In this section we utilize the knowledge of the estimated 

CIR for an accurate initialization that can approximately 

invert channel at the beginning of the equalization process. 

We separately consider equalization of three types of classes: 

minimum phase, maximum phase, and nonminimum phase 

channels. Since maximum phase and nonminimum phase 

channels can be respectively transformed into the minimum 

phase case by time-reversing processing and applying an 

allpass phase equalization beforehand, we start from the 

inverse of a minimum phase channel. 

By definition, both poles and zeros of a minimum phase 

filter must be inside the unit circle, therefore, the inverse of 

such filter is also a minimum phase filter, thus causal and 

stable. An important property of minimum-phase sequences is 

h k having the identical magnitude 

that among all signals { [ ] } 

spectra, the minimum-phase signal { �� [ ] } 

h k has the fastest 

decay in the sense that 

N 

2 

� h�� [ k] N 

2 

≥ � h[ k] , k = 0,1,2, � . (2) 

k = 0 k = 0

That is, the signal energy in the first N+1 samples of the 

minimum-phase case is at least as large as any other causal 

signal having the same magnitude spectrum. Thus, minimumphase 

signals are maximally concentrated toward zero time 

delay among the space of causal signals having a given 

magnitude spectrum. With this property in mind, we can 

approximate the minimum phase channel by neglecting the 

trailing paths and keeping only first paths. To keep the 

following derivation simple and to get a low-complexity 

solution, we will only extract the first 4 channel paths and 

neglect the rest. Then, the Z-transform of the truncated 

minimum phase FIR channel can be expressed as 

3 

k 

H( z) h z . 

− 

= �� (3) 

k 

k= 

0 

The inverse of the channel is given in the Z-domain by its 

reciprocal 

3 1 

−k 

= �� gkz . 

(4) 

H( z) 

k= 

0 

By using the long division method, we can express the first 4 

taps of the inverse filter as 

−1 

g0 = h0 

, 

−2 

g1 = − 

h0 h1, 

(5) 

− −2 − 

−1 

2 

g = = h h h − 

− h , 

( ) 

( ) 

2 0 0 1 2 

3 = = − − 2 

0 

− − 1 

0 1 2 − − − 

− 

2 

0 

3 

1 − 

− 

3 

g h 2 h h h h h h . 

Note for minimum phase sequence { g k} 

, we can roughly say 

that the probability that the firsts several taps 0 g and 1 g 

convey more energy than the rest taps. Therefore, when 

complexity is limited, we can just calculate 0 g and g and 1 

use them to initialize two particularly selected taps of the 

adaptive equalizer, the rest taps can be simply initialized with 

zeros. 

C. Algorithm Summary 

In summary, we propose to initialize the equalizer in the 

following steps: 

1. Estimate the channel impulse response 

2. According to the phase of the channel, do the following 

operation: 

a. If it is a minimum phase channel, directly use the 

inverse of channel transfer function for 

initialization. 

b. If it is maximum phase channel, first calculate the 

inverse channel of the time-reversed CIR, then 

time-reverse the received sequence, equalize the 

time-reversed sequence and make decisions, and 

time-reverse the decision sequence. 

Nachdrucke 


Reprints of 


c. If it is a mixed phase channel, then use an allpass 

filter to convert it to (near) minimum phase 

channel, and then initialize the filter as in the 

minimum phase case. 

In the following, we term the proposed initialization 

schemes as Approximate Channel Inverse Initialization 

(ACII). 

D. Potential Application of ACII Algorithm 

In [10], we propose a systematic structure and algorithm 

that can convert any kind of channel into a time-forward and a 

time-reverse (near) minimum phase channels, which allow the 

direct application of the proposed ACII initialization 

effectively. It is shown that proposed ACII initialization 

allows the immediate usage of adaptive DFE with decision 

directed LMS in the bi-directional arbitrated equalization 

without any training sequence. 

IV. SIMULATION RESULTS 

In this section, we investigate the performance of the 

proposed initialization method for the following four blind 

equalizers: 1. decision directed LMS LE (DD LMS LE); 2. 

decision-directed LMS DFE (DD LMS DFE); 3. CMA-LE; 

4. CMA-DFE. The order of the LE is 8. The DFE filters have 

15 feedforward taps and 9 feedback taps, denoted as (15,9)- 

DFE. 

We simulate QPSK transmission over channels of moderate 

length and plot the bit error rate (BER) versus signal to noise 

ratio (SNR). The BER results were averaged over 2000 

packets transmission, each of length 500 symbols. For each of 

the four types of equalizers, the proposed ACII and the 

conventional single-spike initialization are employed for 

comparison. The single-spike initialization sets the LE and 

the forward filter of DFE so that only one carefully selected 

tap is unity and the other taps are zero, and all taps of the 

feedback filter are zero. For all LMS equalizers, the real 

decisions were used to update the weights and were fed to the 

feedback filter of the DFE’s. 

The simulations presented in Fig. 1 to Fig. 3 consider two 

channels used in [9]: a minimum-phase and a maximum-phase 

channel, both given below 

− − 1 − 

− 

2 

Hmin ( z) = = 0.668 + + 0.46z + + 

+ 0.46z 

(6) 

− − 3 − 

− 

4 

+ + 0.227z + + 

+ 0.227 z , 

−− − −1 −− 

− −2 

Hmax ( z) = = 0.227 + + + 0.227z + + 

+ 0.46z 

(7) 

− −3 − 

−4 

+ + 0.46z + 

+ 0.668 z . 

In Fig. 1, the channel used is Hmin(z). Fig. 1 shows that the 

initial weights of an 8-tap LE obtained by using the ACII 

method are already very near the finally converged weights 


Nachdrucke 


88 

Reprints of 


after 20000 iterations. This demonstrates that the 

approximation of channel inverse is accurate. 

1 

0.5 

0 

1 1.5 2 2.5 3 3.5 4 4.5 5 

Amplitude of initial equalizer weights 

2 

1 

Amplitude of CIR 

0 

1 2 3 4 5 6 7 8 

Converged equalizer weights 

2 

1 

0 

1 2 3 4 5 6 7 8 

Amplitude of initially equalized channel 

1 

0.5 

0 

0 2 4 6 8 10 12 

Amplitude of converged equalized channel 

1 

0.5 

0 

0 2 4 6 8 10 12 

Fig. 1. Comparison of the equalized channel response at the beginning 

and at the end of adaptation. Channel: Hmin(z). LMS LE order: 8; ACII 

initialization with no training sequence is used. Step size: 0.0025. 

Converged results were taken after 20000 iterations. 

Fig. 2 and Fig. 3 respectively show the simulation results 

for 8-tap LE and (15,9)-DFE, both compare the results of the 

conventional single-spike initialization and the proposed 

ACII-initialization. For all maximum phase channel cases, the 

channel output sequence is first time-reversed, and then 

equalized with initialization obtained from the approximate 

inverse of the time-reversed channel, and finally time-reverse 

the decision sequence. Almost similar results were obtained 

for both minimum and maximum phase channels. In both 

figures, at high SNR ranges from about 25 dB to 30 dB the 

observed BER is 0 after averaging over 2000 packets 

transmission each with 500 symbols. This is because the total 

number of symbols simulated is not large enough to get a 

meaningful result for high SNR cases. To obtain meaningful 


results, we used 200000 packets of 50000 symbols each and 

get the BER’s at SNR’s of 25 and 30 dB as shown in Fig. 2 

and Fig. 3. 

Average BER 

1.E+00 

1.E-01 

1.E-02 

1.E-03 

1.E-04 

1.E-05 

1.E-06 

1.E-07 

ACII CMA 

1.E-08 

Single spike CMA 

ACII LMS 

1.E-09 

1.E-10 

Single spike LMS 

10 15 20 25 30 

Average Input SNR (dB) 

Fig. 2. Performance comparison of four types of LE with 8 taps: ACII CMA, 

Single spike CMA, ACII LMS, and Single spike LMS. Step size: 0.0025. 

Simulation size: 2000 packets of 500 symbols each. 

Average BER 

1.E+00 

1.E-01 

1.E-02 

1.E-03 

1.E-04 

1.E-05 

1.E-06 

1.E-07 

1.E-08 

1.E-09 

ACII CMA 

Single spike CMA 

ACII LMS 

Single spike LMS 

1.E-10 

10 15 20 25 30 

Average Input SNR (dB) 

Fig. 3. Performance comparison of four types of (15,9) DFE’s: ACII CMA, 

Single spike CMA, ACII LMS, and Single spike LMS. Step size: 0.0025. 

Simulation size: 2000 packets of 500 symbols each. 

As expected, the ACII initialization significantly reduces 

the average BER. We can see from the results that when the 

conventional single spike initialization is applied, the CMA 

and DD LMS fails to converge within the short packet of 500 

symbols, therefore, the BER is around 0.1. Although the

position of the spike can be optimized according the 

estimated channel impulse response, there is no significant 

improvement observed from our simulation. The main reason 

for the low performance with single spike initialization is that 

it is far from the optimal solution for most of channels, and it 

results in an initial large ISI and a low effective SNR. 

In comparison, the ACII initialization immediately set the 

equalizer as an approximate channel inverse, therefore the 

adaptive equalizers settings can immediately reach the 

vicinity of the global minimum solution; therefore, the 

adaptive algorithms do not need to spend a long time before 

convergence, instead, they only need to further optimize the 

near optimum solution in most of cases. 

When the SNR was too low or the initial ISI is too high that 

the eye is not open, the DFE converged poorly. This is 

because in those cases there is significant error propagation 

and large numbers of decision errors. Conversely, when the 

SNR is high or initial ISI is low, the decision errors are 

infrequent and can be ignored. This proposed initialization 

could approximately invert the channel at the beginning and 

thus reduce the ISI. Therefore, the proposed initialization can 

enhance performance of blind DFE significantly, as shown in 

Fig. 3 

In all figures, we see that the DD LMS has lower BER than 

the CMA. This is because the output error level of the CMA 

algorithm is larger than that of the DD algorithm after 

convergence, and the DD algorithm provides faster 

convergence after the eye is open. This suggests that 

performance of equalizer can be further enhanced by 

automatically switching between the CMA and DD 

algorithms. For the equalizers with CMA algorithm, there are 

no local minima is observed in all simulations. 

V. CONCLUSION 

A low complexity initialization scheme for adaptive 

equalizers is proposed. The initialization method can be 

applied directly for minimum phase channels; for maximum 

phase and nonminimum phase channels, time reversal and 

allpass phase equalization are required to convert them to 

minimum phase channels before initialization and 

equalization. The initialization scheme can significantly 

improve the convergence of adaptive equalizers and avoid the 

local minimum of CMA and DD LMS. Through extensive 

computer simulations, we show that channels that previously 

cannot be equalized by blind equalizers with the conventional 

single spike initialization can now be well equalized with the 

proposed initialization. 

REFERENCES 

[1] S. Haykin, Adaptive filter theory. Englewood Cliffs, NJ: Prentice Hall, 

1991. 

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[2] N. Al-Dhahir and J. M. Cioffi, “MMSE Decision Feedback Equalizers: 

Finite-Length Results,” IEEE Trans. Inform. Theory, vol. 41, pp. 961- 

975, July 1995. 

[3] G. Wang and K. Dombrowski, “Two low-complexity techniques to 

improve equalizer performance in wireless burst data 

communications,” in Proc. IASTED Int. Conf. on Communication 

Systems and Networks, pp. 244-249, Sept. 2003. 

[4] M. P. Sellars, S. D. Greaves, J. Porter, A. Hopper and W. J. Fitzgerald, 

“Performance of a fast start-up equalizer for indoor radio,” IEE Proc. 

Of Commun., vol. 148, pp. 49-56, Feb. 2001. 

[5] P.A. Voois, I. Lee, and J. M. Cioffi, “The effect of decision delay in 

finite-length decision feedback equalization,” IEEE Trans. Inform. 

Theory, vol. 42, pp. 618-621, Mar. 1996. 

[6] J. G. Proakis and D. G. Manolakis, Digital signal processing. 3 rd 

edition, Prentice-Hall, 1996. 

[7] S. Ariyavisitakul, L. J. Greenstein, “Reduced-complexity equalization 

techniques for broadband wireless channels,” IEEE Journal on 

Selected Areas in Communications, vol.15, pp. 5-15, Jan. 1997. 

[8] S. L. Ariyavisitakul, G. M. Durant, “A broadband wireless packet 

technique based on coding, diversity, and equalization,” IEEE 

Commun. Magazine, vol. 36, pp. 110-115, July 1998. 

[9] J. K. Nelson, “BAD: Bidirectional Arbitrated Decision-Feedback 

Equalization,” IEEE TRANSACTIONS ON COMMUNICATIONS, 

VOL. 53, NO. 2, FEBRUARY 2005. 

[10] G. Wang, “Bidirectional Arbitrated Adaptive DFE,” patent pending. 


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A Low-Power, 10Gs/s Track-and-Hold 

Amplifier in SiGe BiCMOS Technology 

Yevgen Borokhovych, Hans Gustat, Bernd Tillack, Bernd Heinemann, 

Yuan Lu (1) , Wei-Min Lance Kuo (1) , Xiangtao Li (1) , Ramkumar Krithivasan (1) , John D. Cressler (1) 

IHP, Circuit Design Department, Im Technologiepark 25, D-15236, Frankfurt (Oder), Germany 

borokhovych@ihp-microelectronics.com 

(1) School of ECE, 777 Atlantic Drive, N.W., Georgia Institute of Technology, Atlanta, GA 30332-0250, USA 

Abstract: 

This paper presents a low-power high-speed BiCMOS 

track-and-hold amplifier (THA). It combines the 

differential switched-emitter follower of [1] with the 

low-droop output buffer presented in [2]. A test 

implementation consumes 70 mW of total power 

(30 mW THA). It works up to 15 GS/s, using minimumsize 

HBTs in a 0.25µm 200 GHz SiGe BiCMOS 

technology. At 10 GS/s and an input signal of 1 GHz, the 

achieved THD corresponds to 6.8 bits accuracy. To our 

knowledge, the present circuit is by far the fastest THA 

with low power consumption and high accuracy. 


There are two main factors in communication technology 

that are currently pushing the envelope of speed and 

accuracy in analog/digital converters (ADCs). First 

factor being the very high baseband data rates of 

emerging wireless applications, which require higher 

conversion rates, e.g. in the ultra-wide band (UWB) 

range of 3-10 GHz or the new unlicensed bands around 

60 GHz with a bandwidth up to 5 GHz. Second the A/D 

interface in wireless systems is being moved closer to the 

antenna and up in frequency, which offers the flexibility 

of covering various communication standards with 

shorter design cycles. 

Track-and-hold amplifiers are crucial components in 

ADCs. They perform the continuous-time to discretetime 

conversion part of the A/D function, and provide a 

temporary constant output to subsequent stages. Often, 

the THA performance is the bottleneck in ADCs 

operating at the technological limits. In addition, the 

mobile applications will require low power as another 

important constraint in THA design, making it even more 

difficult to achieve higher performance. 

This paper describes the design of a THA aimed at 

minimum-power operation at 10 GS/s with at least 6 bits 

of accuracy. A test implementation in a 0.25µm 200 GHz 

SiGe BiCMOS technology [3] is presented. 

2. Architecture 

For very high speed and high accuracy, differential openloop 

architecture is an obvious choice. As shown in 

Fig. 1, the present THA includes a fully differential THA 

core based on the well-known switched-emitter-follower 


(SEF) proposed by Vorenkamp [1]. However, beyond the 

hold capacitors CH, pseudo differential low-droop output 

buffers based on Fiocchi’s THA [2] are used. The 

simplicity of the SEF circuit described in [1] allows 

design for low power consumption. Furthermore, the 

fully differential input stage can partly compensate 

imbalances in the input signal, simplifying the driving of 

the THA. These advantages over the more complex THA 

in [2] come at the cost of larger feedthrough in hold 

mode and some additional nonlinearity in the present 

design. To reduce the supply voltage, the linearization 

diodes used in [1] have been omitted here. In this THA 

type, the load resistors of the input differential stage 

along with their parasitic capacitances dominate the 

settling time. To reduce this effect and the power 

consumption, minimum-size transistors are used 

throughout the THA core. The design goal was to 

achieve 10 Gs/s operation at minimum power while 

maintaining an accuracy of ≥ 6 bits. 

3. Circuit Implementation 

The low-power THA is implemented in a low-cost 

high-performance SiGe BiCMOS technology 

(fT = fmax =200 GHz, BVCEO = 2.0 V, and a minimum 

emitter size of 0.21 × 0.84 µm²) with the whole HBT 

structure in one active area [3]. Apart from HBTs and a 

suite of RF passives, the technology provides an 

industrial quality digital CMOS library, which could be 

essential in later stages of ADC design by allowing 

complex calibration. The present BiCMOS THA does 

not yet use digital CMOS cells, but it employs MOS 

transistors for base current compensation. 

3.1. THA Circuit 

A simplified circuit diagram of the implemented THA 

Analog 

input 

Clock 

signal 

THA core Output 

buffers 

Input 

buffer 

S2 

S1 

2 

T/H signal 

CH 

CH 

Test 

buffers 

Fig. 1 Fully differential THA architecture. 

to 

pads

CH 

out2 

VCC 

T 

Switch 2 Input buffer 

Switch 1 

Q8 

Q7 Q6 

I3 

H 

Cff 

R4 R3 

in2 Q2 Q1 in1 

R2 R1 

I1 

Cff 

Q5 

H T 

Q3 Q4 

Fig. 2 Circuit implementation of differential THA input 

buffer and switch. 

core circuit is shown in Fig. 2 [1]. The differential input 

buffer consists of a differential pair Q1 and Q2 with 

degenerative feedback resistors R1 and R2, and load 

resistors R3 and R4. The differential input signal is 

applied to the bases of the transistors Q1 and Q2. For the 

rest of the paper we will refer only to the right part of the 

symmetric circuit of Fig. 2. The voltage switch 1 consists 

of transistors Q3, Q4, Q5, and tail current source I2. CH 

is the hold capacitor. Transistor Q5 acts as an emitter 

follower and transistor Q4 acts as a cascode transistor. 

During the track phase when node T is high with respect 

to node H, the tail current I2 is switched through Q4 and 

Q5 causing the switch to conduct. During the transition 

from track to hold mode, node H becomes high with 

respect to node T, causing the tail current flowing 

through transistor Q5 to turn off. In addition, the base 

voltage of Q5 is reduced due to the tail current I2 now 

flowing through Q3 and the load impedance R3 of the 

input buffer. Thus, transistor Q5 stops to conduct and CH 

holds the current voltage. 

As shown in Fig. 3, the output buffer uses a pMOS 

current mirror to improve the droop rate by 

compensating the base current of Q9 with the replica of 

the base current of Q10 [2]. A test buffer operates with 

separate larger supply voltage to achieve high linearity. 

in 

VCC 

M1 

M2 

Q10 

Q9 

Test buffer 

VCCout 

Q12 

R6 

out 

Fig. 3 Circuit implementation of output and test buffer. 

4. Reduction of THA Amplitude Errors 

In addition to timing errors caused by clock jitter, there is 

a variety of amplitude errors limiting the THA 

performance. The major sources of errors will be 

discussed in the following sections. 

Q11 

4.1. Hold-Mode Feedthrough 

When the THA is in hold mode, the sampling switches 

present finite impedance in their off state and so the 

capacitances Cbe5 and Cbe8 cause feedthrough of the input 

voltage into the hold capacitor [4]. The hold mode 

R5 

I2 

CH 

out1 

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Reprints of 


feedthrough ( f A ) is given by the ratio of the base-emitter 

capacitance of the switching transistor (Cbe5 or Cbe8) and 

the hold capacitance CH. 

Cbe5 

Af 

= 

(1) 

Cbe5 + CH 

. 

This hold-mode feedthrough can be reduced by adding 

two feedforward capacitors (Cff) as shown on Fig. 2 [1]. 

The charge dump of these capacitors is of opposite sign 

to the charge dump of the base-emitter capacitances of 

the switching transistors. The compensated hold-mode 

feedthrough ( A ) is now given by 

c 

C ⎛ C 

be5 

ff ⎞ 

Ac 

= ⋅⎜1 − ⎟ 

(2) 

Cbe5 + CH ⎝ Cbe5 

⎠ . 

Complete cancellation of the hold-mode feedthrough 

would require Cff being identical to the base-emitter 

capacitance. The feedthrough capacitor (Cff) is realized 

using a series-parallel construction of four diodes (Fig. 4) 

[1]. In reality, the device mismatch of the minimumsized 

HBTs limits the cancellation. 

+ - 

Fig. 4 Hold-mode feedthrough capacitor. 

4.2. Pedestal Error 

During the transition from track to hold mode, the switch 

transistors Q3 and Q4 need a non-zero time (aperture 

timeτ ) to turn off the emitter current of Q5, and to turn 

a 

on the current needed to pull down the base voltage of 

Q5. Further, when both transistors conduct duringτ , the a 

input signal still has some effect on the emitter current of 

Q5, which decreases over time due to the increasing 

impedance ZQ4 of Q4. Even though transistors Q3 and 

Q4 are arranged in a differential stage to make the 

switching process more symmetric, they operate at 

different collector voltages causing some timing 

difference ∆ τ . This produces a charge offset a 

I 2⋅ ∆τ 

a 

during the transition. Another source of error is the T/H 

signal coupling into CH through the base-collector 

capacitance of Q4. 

These contributions to the charge on CH can be 

approximated by 

t0 

+ τ a Vin ( t) −Vbe 

( t) 

∆ qpedestal = ∫ dt 

Z t ( ) 

0 Q4 

t 

(3) 

+ I 2 ⋅∆ τ a + VT / H ⋅Cbc 

_Q 4 . 

All three terms are actually signal-dependent. The first 

one contains the input signal to the switch (Vin) 

explicitly. In the second and the third terms, ∆ τ is a a 

function of the voltage at the collector of Q3, and Cbc_Q4 

is a function of the voltage at the collector of Q4, 

respectively. Since their dependence on the signal is not 

linear, it is difficult to reduce their effect, even in a fully 


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92 

Reprints of 


differential configuration. The most efficient way to 

decrease this error is reducing the first two terms by 

minimizing τ as much as possible, applying a very 

a 

steep clock slope. On the other hand, a steep slope 

requires a high voltage swing VT/H, causing the third 

term to grow. We have chosen a swing of 300 mV for 

VT/H as a compromise between these error terms. 

Another major amplitude error is caused by the 

nonlinearity of the continuous THA stages. It depends 

strongly on the signal amplitude, limiting the useful 

signal range to about ±500 mV. 

Fig. 5 THA test chip micrograph. 

5. Experimental Results 

The THA circuit has been realized in a 0.25µm 200 GHz 

SiGe HBT BiCMOS technology and occupies an area of 

0.5 mm 2 including pads. Fig. 5 shows the chip 

microphotograph. The test chip has been wire-bonded on 

a ceramic test board for measurement. Unfortunately, 

only one 180° hybrid and no phase tuners were available 

for measurement in the required frequency range. 

Therefore, the measurement was set up as shown in 

Fig. 6. 

fin 

hybrid 

THA 

fs 

50Ω 

Spectrum 

Analyzer 

Fig. 6 Measurement setup for characterizing THA in 

frequency domain. 

The single-ended sampling clock has been applied to the 

differential clock input of the THA. The signal input of 

the THA is driven differentially. Only one of the THA 

outputs is connected to the spectrum analyser. Thus, the 

inherently good cancellation of even-order distortion 

possible by the symmetrical circuit has not been used for 


determining the THA spectrum. This causes a large 

overestimation of the even harmonics. The effect of the 

input phase imbalance caused by imperfections of the 

hybrid and the cables is less severe, because it is partly 

compensated by the fully differential input stage. 

Fig. 7 Spectrum of the single-ended output signal. 

Fig. 7 shows the measured single-ended THA output 

spectrum at an input frequency ( f ) of 1 GHz and a 

in 

sampling rate ( f ) of 9.99 Gs/s. As expected, the second 

s 

harmonic of the single output dominates the total 

harmonic distortion (THD). This single-ended 

measurement certainly underestimates the performance 

of the differential circuit. 

Fig. 8 compares the measured data with the results of a 

post-layout simulation, both for the single-output case. 

To obtain a reasonable value of the second harmonic of a 

differential output, the measurements have been 

extrapolated to differential mode by simulation. 

According to post-layout simulation, the second 

harmonic is reduced by 40 dB by changing from singleended 

to differential output. To be on the safe side of 

estimation, we have halved this reduction before 

applying it to the measured single-ended second 

harmonic. The resulting value is marked with a triangle 

in Fig. 8. Now, the THD is dominated by the measured 

third harmonic. The THD is -41 dBc. It corresponds to 

an effective number of bits (ENOB) of 6.8. Table I 

summarizes the main parameters of the THA. 

Table I Summary of the THA characteristics. 

SiGe HBT, 

Process 

fT = 200 GHz 

Input range 1 Vp-p differential 

Sampling rate 10 GHz 

Differential droop rate

Normalized signal, dB 

0 

-10 

-20 

-30 

-40 

-50 

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Table II Comparison with published Si/SiGe high-speed THAs. 

Ref fsample 

[GHz] 

fin 

[GHz] 

Input 

[Vpp] 

ENOB 

[bit] 

BW 

[GHz] 

Supply 

[V] 

Pdiss 

[W] 

Process/fT 

[GHz] 

[5] 2 0.9 0.8 8 0.9 -3.3 0.55 SiGe/65 

[6] 12.1 1.5 1 8 5.5 3.5 0.7 SiGe/200 

[7] 1.2 0.6 1 8 2 +2/-5 0.46 Si/25 

[8] 4 8 0.6 6 10 5.2 0.55 SiGe/45 

This 

10 1 1 6.8 

work 

1 2.7 3.3 0.03 2 SiGe/200 

1 

Extrapolated from the measured single-ended signal. 

2 

Test buffers and clock driver (40 mW) are not included. 

-60 

0 1 2 3 

Frequency, GHz 

Measured 

Simulated 

Extrapolated 

Fig. 8 Single-ended measurement, simulation and 

extrapolation at fin = 1 GHz, fs = 9.99 GHz. 

The circuit is functional up to 15 GS/s sampling rate. 

Fig. 9 shows an oscilloscope plot at fin = 1.5 GHz, 

fs = 15 GHz. 

Fig. 9 Differential output of the THA for fin = 1.5 GHz, 

fs = 15 GHz. 

Table II compares this work with similar THA designs in 

Si and SiGe. The present THA has less than ten per cent 

of the power consumption of any other high-speed THA. 

It does not achieve the accuracy and speed of the 

enhanced Fiocchi THA implemented in the same 

technology [6], but it is still the second fastest THA on 

silicon at ≥6 bits known to the authors, and the only 

high-speed THA at comparable accuracy in the lowpower 

class. 

6. Conclusions 

Reprints of 


A low-power THA for 10 GS/s operation has been 

designed based on an implementation of differential 

switched-emitter followers [1] and low-droop output 

buffers [2] using minimum-size HBTs. A test chip in a 

0.25 µm 200 GHz SiGe BiCMOS technology consumes 

70 mW in total, including test buffers and clock driver, 

with only 30 mW for the THA itself. The chip is 

functional up to 15 GS/s sampling rate. At 10 GS/s and 

an input signal of 1 GHz, the measurements exhibit a 

THD of -41 dBc corresponding to an ENOB of 6.8. The 

present circuit is the fastest 6+ bit THA in this class of 

power consumption published so far. 

7. Acknowledgements 

This is work was supported by IHP and GEDC/GTAC at 

Georgia Tech. The authors thank the IHP technology 

team for chip fabrication. 

References: 

[1] P. Vorenkamp and J.P. Verdaasdonk, “Fully Bipolar 120- 

MSample/s 10-b Circuit”, IEEE Journal of Solid State 

Circuits, Vol. 27, pp. 988-992, 1992. 

[2] C. Fiocchi, U. Gatti and F. Maloberti, “Design Issues on 

High-Speed High-Resolution Track-and-Hold in BiCMOS 

Technology”, IEE Circuits Devices Systems, Vol. 147, pp. 

100-106, 2000. 

[3] B. Heinemann et al., “Novel Collector Design for High- 

Speed SiGe:C HBTs“, Proc. IEDM, pp. 775-778, 2002. 

[4] R. van der Plassche, “Integrated Analog-to-Digital and 

Digital-to-Analog Converters”, Kluwer Academic 

Publishers, 1994. 

[5] F. Vessal and C. A. T. Salama, “A Bipolar 2-GSample/s 

track-and-hold amplifier (THA) in 0.35 um SiGe 

technology”, Proc. IEEE Int. Symp. Circuits and Systems, 

Vol. 5, pp. 573-576, 2002. 

[6] Y. Lu et al., “An 8-bit, 12 GSample/sec SiGe Track-and- 

Hold Amplifier”, submitted to BCTM 2005. 

[7] B. Pregardier, U. Langmann and W. Hillery, “A 1.2-GS/s 

8-b Silicon Bipolar Track&Hold IC”, IEEE Journal of 

Solid-State Circuits, Vol. 31, pp. 1336-1339, 1996. 

[8] J. Jensen and L. Larson, “A Broadband 10-GHz Trackand-Hold 

in Si/SiGe HBT Technology”, IEEE Journal of 

Solid State Circuits, Vol. 36, pp. 325-330, 2001. 


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ISSCC 2005 / SESSION 21 / TD: RF TRENDS: ABOVE-IC INTEGRATION AND MM-WAVE / 21.9 

21.9 A Fully Integrated BiCMOS PLL for 60 GHz 

Wireless Applications 

Wolfgang Winkler, Johannes Borngräber, Bernd Heinemann, 

Frank Herzel 

IHP, Frankfurt (Oder), Germany 

An integrated PLL tunable from 54.5 to 57.8GHz manufactured 

in a SiGe:C BiCMOS technology is presented. The PLL is aimed 

at wireless transceivers in the unlicensed band from 57 to 64GHz 

[1]. Existing 60GHz transceivers are based on compound semiconductors 

[2]. By contrast, silicon-based solutions will enable a 

high integration level at low cost. The known 60GHz systems utilize 

free-running oscillators for frequency synthesis. These solutions 

are subject to frequency changes due to device parameter 

variations with process and temperature. Our PLL solution 

allows a simple stabilization of the frequency. In [3], a 45GHz 

PLL manufactured in a SiGe bipolar technology is presented. It 

uses a VCO running at half the output frequency in conjunction 

with a frequency doubler. By contrast, the proposed PLL avoids a 

frequency doubler and uses a fundamental LC oscillator resulting 

in a higher output power at a given power consumption. 

Furthermore, the BiCMOS implementation allows combining 

fast bipolar circuitry with low-power CMOS blocks in order to 

achieve a high integration level. The schematic of the fully integrated 

PLL is presented in Fig. 21.9.1. A VCO with a coarse and 

a fine-tuning input is embedded in a PLL with two parallel loops 

sharing the frequency divider and the phase-frequency detector 

(PFD). This topology allows combining a relatively wide tuning 

range with a low noise sensitivity [4]. The coarse tuning loop with 

a tuning range of 3GHz has no resistor in the loop filter, but only 

a large MIM capacitor to minimize the noise contribution. The 

fine-tuning loop contains a standard loop filter for stability. The 

fine-tuning range is as low as 600MHz, which minimizes the 

noise contribution from the fine-tuning loop. 

The PLL is fabricated in a SiGe:C BiCMOS technology with f T/f max 

= 200GHz/200GHz [5]. The chip micrograph of the PLL is presented 

in Fig. 21.9.2. The chip size is 1000 × 800µm 2 including 

pads and 700×560µm 2 without pads. The VCO is based on a modified 

Colpitts principle in a symmetric configuration similar to 

[6], and is followed by a cascade of ten static dividers. With the 

symmetric signal the sensitivity to substrate noise is reduced and 

the signal coupling to the symmetric ECL divider circuit [7] is 

more effective. Figure 21.9.3 shows the measured coarse tuning 

range, which amounts to 3GHz. Another 600MHz tuning range 

results from the fine tuning. A VCO frequency around 55GHz will 

result in an IF of about 5GHz in a 60GHz heterodyne receiver. 

This will allow circuitry developed for 802.11a WLAN to be 

reused in an integrated 60GHz WLAN transceiver. The measured 

PLL lock range is from 54.5 to 57.8GHz. Figures 21.9.4 and 21.9.5 

show the PLL output spectrum with different resolution. The 

measurements are performed on wafer using the spectrum analyzer 

FSEM 30 in conjunction with the harmonic diode mixer FS- 

Z75 for frequency extension to the V-band. To prevent mixer overload, 

a 20dB wave-guide attenuator is inserted. The reference 

spurs are 50dB below the carrier. The circuit operates from a 3V 

supply except for the first divide-by-two stage which needs a 4.3V 

supply. A signal generator provides a sine-wave reference signal 

from 53.2 to 56.5MHz with 100mV amplitude. The total power 

consumption amounts to 650mW. 

406 • 2005 IEEE International Solid-State Circuits Conference 0-7803-8904-2/05/$20.00 ©2005 IEEE. 


An important issue is the optimization of the loop bandwidth. 

The high PLL output frequency results in a large PLL division 

factor if a commercial crystal oscillator is used to drive the PLL. 

This enhances the jitter contributions of the input signal and the 

charge pump, which are low-pass filtered in a PLL making a narrow-band 

PLL desirable. However, due to the absence of highquality 

passives in an integrated PLL, the VCO phase noise, 

which is high-pass filtered in the PLL, will significantly degrade 

the PLL jitter performance. As shown in [8], the corresponding 

rms phase error contribution (in radians) can be deduced from 

the single-sideband phase noise S SSB [1/Hz] of the free-running 

VCO measured at the offset �f from the carrier, and the loop 

bandwidth f L [Hz] according to 

VCO 

PLL π ⋅ SSSB 

σ φ = ∆f 

. 

f L 

Figure 21.9.6 shows the RMS phase error as a function of fL for 

two typical VCO phase noise values. Obviously, a relatively large 

loop bandwidth will be required for an acceptable phase error, 

resulting in a subtle trade-off with the other noise contributions 

in the PLL. In conclusion, the PLL bandwidth of 200kHz visible 

in Fig. 21.9.5 should be significantly increased in a redesign. 

Acknowledgments: 

The authors acknowledge the IHP technology team for chip fabrication. 

This work was partly funded by the German Federal Ministry of Education 

and Research (BMBF) under the project acronym WIGWAM. 

References: 

[1] W. Winkler et al., “60 GHz Transceiver Circuits in SiGe:C BiCMOS 

Technology,” ESSCIRC, pp. 83-86, Sept., 2004. 

[2] Y. Shoji, K. Hamaguchi, and H. Ogawa, “Millimeter-Wave Remote Self- 

Heterodyne System for Extremely Stable and Low-Cost Broad-Band 

Signal Transmission,” IEEE Trans. on Microwave Theory and Techniques, 

vol. 50, pp. 1458-1467, June, 2002. 

[3] G. Ritzberger, J. Böck, and A. Scholtz, “45GHz Highly Integrated 

Phase-Locked Loop Frequency Synthesizer in SiGe Bipolar Technology,” 

IEEE MTT-S Intl. Microwave Symp., pp. 831-834, June, 2002. 

[4] F. Herzel, G. Fischer, and H. Gustat, “An Integrated CMOS RF 

Synthesizer for 802.11a Wireless LAN,” IEEE J. Solid-State Circuits, vol. 

38, pp. 1767-1770, Oct., 2003. 

[5] B. Heinemann et al., “Novel Collector Design for High-Speed SiGe:C 

HBTs,’’ IEDM, pp. 775-778, Dec., 2002. 

[6] W. Winkler, J. Borngräber, B. Heinemann, and P. Weger, “60GHz and 

76GHz Oscillators in 0.25µm SiGe:C BiCMOS,’’ ISSCC Dig. Tech. Papers, 

pp. 454-455, Feb., 2003. 

[7] W. Winkler et al., “High-performance and Low-Voltage Divider Circuits 

Fabricated in SiGe:C HBT Technology,” ESSCIRC, pp. 827-830, Sept., 

2002. 

[8] F. Herzel, W. Winkler, and J. Borngräber, “An Integrated 10 GHz 

Quadrature LC-VCO in SiGe:C BiCMOS Technology for Low-Jitter 

Applications,” IEEE CICC, pp. 293-296, Sept., 2003.

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ISSCC 2005 / February 9, 2005 / Salon 7 / 12:00 PM 

Figure 21.9.1: Circuit schematic of the PLL. Figure 21.9.2: Chip micrograph of the fully integrated PLL. 

Figure 21.9.3: VCO output frequency as a function of coarse tuning voltage. 

Figure 21.9.5: High-resolution output spectrum around the carrier 

including 20dB external attenuation. 

Figure 21.9.4: Output spectrum of PLL including 20dB external attenuation. 21 

Figure 21.9.6: Plot of rms phase error due to VCO noise versus loop 

bandwidth f L. 

DIGEST OF TECHNICAL PAPERS • 


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96 

Abstract 

Reprints of 


Materials Science in Semiconductor Processing 8 (2005) 279–282 

High-frequency SiGe:C HBTs with elevated extrinsic 

base regions 

H. Ru¨ cker � , B. Heinemann, R. Barth, D. Knoll, P. Schley, R. Scholz, 

B. Tillack, W. Winkler 

IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany 

Available online 18 October 2004 

This paper reports on the transistor design of high-speed SiGe HBTs with low parasitic resistances and capacitances. 

Elevated extrinsic base regions and a low-resistance collector design were integrated in a SiGe:C BiCMOS technology to 

simultaneously minimize base and collector resistances and base-collector capacitance. This technology features CML 

ring oscillator delays of 3.6 ps per stage for HBTs with fT/fmax values of 190/243 GHz and a BVCEO of 1.9 V. 

r 2004 Elsevier Ltd. All rights reserved. 

Keywords: SiGe; Heterojunction bipolar transistors (HBTs); High-speed devices; Ring oscillators; Silicon 


The capability of SiGe HBT technology for circuit 

speeds in the 10–100 GHz range results from the 

combination of short transit times through the thin 

SiGe base with short parasitic charging times. The 

recently reported increase in high-frequency performance 

of SiGe HBTs was to a large extent due to new 

low-parasitic device constructions such as low-resistance 

collector design [1] and elevated extrinsic base regions 

[2,3]. This has resulted in fT and fmax values above 

200 GHz and gate delays below 4 ps [3–5]. 

Here, we report on a high-speed SiGe:C BiCMOS 

technology that combines an elevated extrinsic base 

construction with a low-resistance collector design to 

simultaneously minimize base resistance R B, collector 

resistance RC, and base-collector capacitance CBC. Gate 

� 

Corresponding author. Tel.: +49 335 5625 514; 

fax: +49 335 5625 327. 

E-mail address: ruecker@ihp-microelectronics.com 

(H. Rücker). 

ARTICLE IN PRESS 

1369-8001/$ - see front matter r 2004 Elsevier Ltd. All rights reserved. 

doi:10.1016/j.mssp.2004.09.061 


delays of 3.6 ps per stage were achieved for CML ring 

oscillators using HBTs with an fT of 190 GHz, an fmax 

of 243 GHz, and a BV CEO of 1.9 V. The high-speed HBT 

module has been integrated in a 0.25 mm CMOS 

platform. 

2. Technology 

The design of the investigated HBTs is illustrated in 

cross section in Fig. 1. Key device features are: (1) 

Elevated extrinsic base regions self-aligned to the emitter 

window resulting in low base resistance. (2) Formation 

of the whole HBT structure in one active area without 

shallow trench isolation between emitter and collector 

contact resulting in low collector resistance and small 

collector–substrate junction areas. (3) Device isolation 

without deep trenches resulting in reduced process 

complexity and improved heat dissipation. 

The HBT module was fabricated in a BiCMOS 

process after gate patterning and gate spacer formation 

[1,3]. During HBT fabrication, CMOS regions are

280 

Elevated extrinsic base Emitter 

STI 

protected with a layer stack that is opened over HBT 

regions. The process sequence for HBT fabrication is 

sketched in Fig. 2. It begins with the formation of the 

collector wells by high-dose ion implantation. The 

collector wells are laterally confined by shallow trench 

regions. Next, the active collector region is defined by 

depositing and patterning on oxide layer. A Si buffer 

layer, the SiGe:C base layer, and a Si cap layer are 

grown in one epitaxial step. After epitaxy, a sacrificial 

layer is deposited, and emitter windows are structured. 

An additional inside spacer is formed before depositing 

and structuring the As-doped emitter. Next, spacers are 

formed at the emitter and the sacrificial layer is removed 

by wet etching, followed by the self-aligned selective 

growth of the B-doped extrinsic base. Further details of 

the process are given in [3]. In a reference process 

without the elevated base, the extrinsic base is formed 

by ion implantation after emitter structuring as described 

in [1]. 

3. Device results 

Using the new collector design, collector resistances as 

low as the emitter resistance can be realized even 

without introducing an epitaxially buried subcollector 

(see Table 1). The fabrication of these heavily doped 

collector wells with low defect density has been 

demonstrated by high yield of arrays of 4096 HBTs in 

parallel [1]. 

Introducing the elevated extrinsic base design resulted 

in a reduction of the base resistance by about 20% and a 

reduction of the base-collector capacitance by about 

15% compared to reference devices with implanted 

extrinsic base at the same drawn emitter width of 

0.21 mm. Shrinking the drawn emitter width from 0.21 to 

0.175 mm resulted in a further reduction of RB and CBC 

(Table 1). 

3.1. RF characteristics 

SIC 

SiGe:C 

Heavily-doped collector 

The effect of the low-resistance extrinsic base design 

on f T and f max is demonstrated in Fig. 3. Transistors 


Collector contact 

STI 

Fig. 1. Schematic cross section of an HBT with elevated 

extrinsic base. Single-crystalline and poly-crystalline regions of 

the base layer are indicated by different hachures. 

Nachdrucke 


H. Rücker et al. / Materials Science in Semiconductor Processing 8 (2005) 279–282 

(a) Collector well implant 

STI 

Emitter 

Heavily-doped collector 

(b) Collector window opening & Si/SiGe:C/Si epi 

SiGe:C 

Collector window 

(c) Emitter window opening & SIC implant 

Inside spacer 

(d) Emitter depo. & structuring, spacer formation 

Reprints of 


Sacrificial layer 

Outside spacer 

(e) Selective growth of elevated extrinsic base 

Elevated extrinsic base 

with elevated extrinsic base and reference transistors 

with implanted extrinsic base have similar fT curves due 

to almost identical doping profiles in the active 

transistor region. The peak f max increases from 

186 GHz for the device with implanted extrinsic base 

to 225 GHz for the device with elevated extrinsic base 

due to reduced R B and C BC. The further reduction of R B 


SIC 

STI 

Fig. 2. Process sequence for HBT fabrication: (a) collector well 

implant; (b) collector window opening and Si/SiGe:C/Si epi; (c) 

emitter window opening and SIC implant; (d) emitter depo. and 

structuring, spacer formation; (e) selective growth of elevated 

extrinsic base.

Nachdrucke 


98 

Reprints of 


and CBC due to shrinking the emitter width to 0.175 mm 

resulted in an f max of 243 GHz. 

3.2. Noise performance 

Noise characteristics of the present technology have 

been measured up to 26 GHz. Fig. 4 shows the minimum 

noise figure F min and the associated gain G A vs. 

frequency. The simultaneous realization of low RB and 

high fT for the devices with elevated extrinsic base results 

in high gain (G A at 26 GHz=8 dB) and low noise (F min 

at 26 GHz=1.6 dB) out to high frequencies. The lowresistance 

elevated base design reduces Fmin by about 

0.3 dB compared to the reference devices with implanted 

extrinsic base. 


Table 1 

RF parameter, resistances and capacitances for HBTs with different emitter dimensions fabricated in the process with selectivelygrown 

elevated extrinsic base and in the reference technology with implanted extrinsic base. R E and R C were determined from static 

device characteristics and R B from circle fits of s 11 at V BE=0.9 V. The R B values given here differ from those in [3] due to the different 

extraction procedure 

Selectively grown elevated extrinsic base Implanted extrinsic base 

Drawn emitter area (mm 2 ) 0.175 � 0.84 0.21 � 0.84 0.21 � 0.84 

fT (GHz) 190 200 202 

fmax (GHz) 243 225 186 

CML gate delay (ps) 3.6 3.9 4.3 

C BC (fF) 2.4 2.8 3.3 

RB (O) 75 85 110 

RE (O) 22 18 19 

R C (O) 21 16 16 

f T / f max (GHz) 

200 

150 

100 

50 

0 

V CE=1.5V 

f max 

10 -4 

H. Rücker et al. / Materials Science in Semiconductor Processing 8 (2005) 279–282 281 

f T 

A E =2x(0.21x0.84)µm 2 

10 -3 

Collector Current (A) 

10 -2 

Fig. 3. Transit frequency f T and maximum oscillation frequency 

f max vs. collector current for transistors with elevated 

extrinsic base (lines with circles) and for reference HBTs with 

implanted extrinsic base (lines). 

Min. Noise Figure (dB) 

2.0 

1.6 

1.2 

0.8 

0.4 

3.3. Ring oscillator gate delays 


Implanted 

extrinsic base 

Elevated 

extrinsic base 

0.0 

0 5 10 15 20 25 

0 

30 

Frequency (GHz) 

CML ring oscillators with 53 stages were investigated 

to benchmark the high-frequency performance for 

digital applications. Using a series of ring oscillators 

with various load resistances, we have measured the gate 

delay as a function of current per gate (Fig. 5). 

Minimum gate delays of 3.6 ps per stage were achieved 

for single-ended voltage swings from 200 to 400 mV. 

Gate delays for the three types of HBTs compared in 

this study are given in Table 1 for a voltage swing of 

300 mV. The shortest gate delays were achieved for the 

HBTs with elevated extrinsic base design and drawn 

emitter widths of 0.175 mm. These transistors feature fT 

and f max values of 190 and 243 GHz, respectively. 

25 

20 

15 

10 

5 

Associated Gain (dB) 

Fig. 4. Minimum noise figure and associated gain vs. frequency 

at IC=2 mA and VCE=1.5 V for devices with eight emitters 

with drawn areas of 0.21 � 0.84 mm 2 in parallel. De-embedded 

values are shown.

282 

Gate Delay (ps) 

5.0 

4.8 

4.6 

4.4 

4.2 

4.0 

3.8 

3.6 

3.4 

1 2 3 4 

The gate delays obtained for the three types of HBTs 

compared in Table 1 scale roughly as 1/fmax. This 

dependence is in accordance with the analysis given in 

[6,4] which suggests similar first-order expressions for 

the delay in a current switch and for 1/fmax. However, 

comparison of different high-speed SiGe HBT technologies 

shows that comparable stage delays are obtained 

in spite of transistors with significantly different fmax [4]. 

Previously, shortest ring oscillator gate delays of 3.9 ps 

were reported for SiGe technologies with peak f max 

values of 338 GHz [4] and 197 GHz [5]. In this work, a 

reduced gate delay of 3.6 ps was achieved although 

devices of the present technology have a significantly 


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H. Rücker et al. / Materials Science in Semiconductor Processing 8 (2005) 279–282 

T=300K; V EE =-2.5V; A E =0.175x0.56µm 2 

Current per Gate (mA) 

∆V=400mV 

∆V=300mV 

∆V=200mV 

Fig. 5. CML ring oscillator gate delay vs. current per gate for 

oscillators with 53 stages. The single-ended voltage swing was 

varied from 200 to 400 mV. Data points are average values of 

six devices measured on one wafer. The transistors have 

elevated extrinsic base regions and drawn emitter areas of 

0.175 � 0.56 mm. 

Reprints of 


lower fmax than those of [4]. This indicates that device 

optimization for minimum gate delay has to include in 

addition to f max also other parameters such as substrate 

capacitance (CJS) and interconnect capacitances. The 

use of an CML architecture in the present work and in 

[5] and a ECL architecture in [4] is expected to have only 

a minor impact on ring oscillator gate delay. 

4. Summary 

Reducing parasitic resistances and capacitances by 

innovative device design is key for increasing the speed 

of HBT circuits. Combining a new low-resistance 

extrinsic base design and a low-resistance collector 

design, we have demonstrated ring oscillator gate delays 

of 3.6 ps in a SiGe:C BiCMOS technology featuring 

HBTs with fT/fmax of 190/243 GHz. 

References 

[1] Heinemann B, et al. Novel collector design for high-speed 

SiGe:C HBTs. IEDM Tech. Dig. 2002. p. 775–8. 

[2] Jagannathan B, et al. Self-aligned SiGe NPN technology 

with 285 GHz f max and 207 GHz f T in a manufacturable 

technology. IEEE Electr Device Lett 2002;23:258–60. 

[3] Ru¨ cker H, et al. SiGe:C BiCMOS technology with 3.6 ps 

gate delay. IEDM Tech. Dig. 2003. p. 121–4. 

[4] Jagannathan B, et al. 3.9 ps SiGe HBT ECL ring oscillator 

and transistor design for minimum gate delay. IEEE Electr 

Device Lett 2003;24:324–6. 

[5] Meister TF, et al. SiGe bipolar technology with 3.9 ps gate 

delay. In: Proceedings of BCTM. 2003, p. 103–6. 

[6] Stork JM, Bipolar transistor scaling for minimum switching 

delay and energy dissipation. IEDM Tech. Dig. 1988. 

p. 550–3. 


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100 

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A Low-Cost SiGe:C BiCMOS Technology with Embedded Flash 

Memory and Complementary LDMOS Module 

D. Knoll, A. Fox, K.E. Ehwald, B. Heinemann, R. Barth, A. Fischer, H. Rücker, P. Schley, R. Scholz, 

F. Korndörfer, B. Senapati, V.E. Stikanov # , B. Tillack, W. Winkler, Ch. Wolf, and P. Zaumseil 

IHP, Im Technologiepark 25, 15 236 Frankfurt (Oder), Germany 

# Kiev Polytechnical Institute, CAD Department, Kiev, Ukraine 

Abstract - We present a low-cost, modular BiCMOS 

process for wireless and mixed-signal applications. A SiGe:C 

bipolar module, a complementary LDMOS module, and a 

low-power flash memory were combined with a 0.25µm 

CMOS technology to enable SoC integration. The low-cost 

approach is demonstrated by the fact that only 29 mask steps 

are applied in total for the full process flow including all 

modules, a full suite of passives, and 5 metal layers. 

Index Terms - BiCMOS technology, heterojunction 

bipolar transistors, LDMOS devices, embedded memory. 


SiGe:C BiCMOS technology allows one to combine 

state-of-the-art CMOS circuitry with best bipolar RF 

performance on a single chip [1]. This combination, 

supplemented by further functions such as high-voltage 

and non-volatile memory (NVM) enables the realization 

of integrated mixed-signal systems-on-a-chip (SoC). 

However, a big challenge for the development of such an 

SoC-able platform is reasonably to compromise device 

performance and functionality with cost, affected by 

features such as no. of masks and process steps, yield etc. 

Here, we present a modular SiGe:C BiCMOS platform 

which offers a wide device spectrum with ample 

performance at low process complexity, and hence cost. 

The essential process features can be summarized as 

follows: (1) A SiGe:C bipolar module, a complementary 

LDMOS module, and a low-power flash memory were 

integrated in a triple-well, 0.25µm RF-CMOS core. (2) 

The bipolar module fabricates several types of SiGe:C 

HBTs with peak-fT/BVCEO values ranging from 29GHz/7V 

up to 140GHz/2V. (3) The LDMOS module offers n- 

LDMOS transistors with fT/BVDSS values in a range of 

17GHz/26V to 23GHz/15V, an isolated n-LDMOS device 

with 21GHz fT and 11.5V BVDSS, and p-LDMOS 

transistors with up to 13GHz fT and -13.5V BVDSS. (4) 

The flash memory uses floating gate cells. For the 

write/erase cycles, Fowler-Nordheim (FN) tunneling is 

applied to get low power consumption. (5) Among the 

passives are MOS and junction varactors, high-speed 

Schottky diodes, several types of resistors, and a MIM 

0-7803-9309-0/05/$20.00 ©2005 IEEE 

132 


cap. (6) For fabricating the full device menu, including 5 

layers of AlCu, the process uses only 29 mask steps which 

demonstrates the low-cost process approach. 

RF-CMOS Flow Module Integration 

Shallow Trench Isolation 

Well Implants 

Gate Oxidation 

Gate Poly Deposition 

Gate Structuring 

Gate Spacer Formation 

S/D Implants 

Salicide Blocker 

Contact Module 

Collector Implant for 

High-fT HBT (1) 

Dual Gate Oxide Wet 

Etch for Flash (1) 

Floating Gate + Flash p-Well Implant (1) 

1-Mask HBT-Module (1) 

Floating Gate Etch + HV n-Well Impl. (1) 

Control Gate Etch + HV n-LDD Impl. (1) 

Complementary 

LDMOS Module (2) 

Schottky Diodes (1) 

BEOL including: 5 Al Layers, MIM Module 

(20 mask steps) 

Fig. 1. Flow diagram of the BiCMOS process. The numbers in 

brackets illustrate the no. of added mask steps. 

II. PROCESS FLOW AND INTEGRATION ISSUES 

IEEE BCTM 8.4 

Fig. 1 shows a flow diagram of the complete process. 

Device structures, such as HBT, memory cell and 

LDMOS, are illustrated by the Figs. 2-4. As shown in Fig. 

1, the full process results from the integration of several 

modules into an RF-CMOS flow. Clearly, any module 

integration must not change the CMOS transistor 

parameters to guarantee re-usability of libraries for all

“Coll.” 

Oxide 

Spacer 

“Emitter” “Coll.” 

n + 

SiGe:C 

p + Gate 

Poly 

STI 

Fig. 2. SEM cross-section of a SiGe:C HBT with base contact 

in line with the emitter contact. 

Fig. 3. SEM cross-section of a stacked gate flash memory cell 

along bitline direction, with S/D contacts. 

S 

n + p + 

G 

n-Well 

p-LDD + n-LDD2 

p-Substrate 

Fig. 4. Schematic cross-section of the p-LDMOS transistor. (p- 

LDD is a masked B implantation, while n-LDD2 is a blanket 

co-implantation of P and BF 2) 

process versions over the CMOS-only flow. LDMOS 

integration without affecting the normal CMOS devices 

can be done easily [2]. A standard floating gate approach 

was chosen for the NVM just because of its good CMOS 

compatibility [3]. The particular HBT integration scheme 

of our process completes the vertical HBT structure 

already before all CMOS post-gate implantations are 

carried out [4, 5]. Thus, HBT fabrication has nearly no 

D 

p + 

n-Buried layer (Deep P implant) 

STI 

133 

Nachdrucke 


Reprints of 


effect on the final CMOS doping profiles. To get same 

MOS transistors in the pure CMOS and the BiCMOS 

flow, we had only to optimize carefully the strongest 

thermal step of the HBT module, the H2-prebake carried 

out before base deposition to get a perfect epi-layer. 

A further advantage of our HBT module is the good 

compatibility with the chosen memory cell type. This type 

can not so easily be integrated in a BiCMOS process with 

the commonly applied HBT-after-gate integration scheme. 

The only critical point in our process with respect to an 

unwanted effect of the memory integration is illustrated by 

Fig. 5. It shows the HBT structure after deposition of the 

memory control gate layer. This layer and the underlying 

isolator layer are later etched away from the HBT regions. 

The question was if the applied etch procedure has a 

negative impact on the properties of the HBT emitter-base 

complex, for example by damaging the oxide spacer 

separating the highly doped emitter from the external base. 

Fig. 6 demonstrates that this is not the case showing that 

the stacked gate, flash memory integration is fully 

compatible with the HBT module. 

Percentage of Good Devices 

STI 

Good Device: I ECs < 1nA @ V EB = 0.4V 

100 

80 

60 

40 

20 

Oxide 

Spacer 

Emitter 

SiGe:C 

with or w/o flash integration 

0 

0 5 10 15 20 25 

Fig. 6. 

Wafer ID 

Emitter-base leakage current yield of 4k HBT arrays 

fabricated in a process flow with or without flash memory. 

III. HBT MODULE 

IEEE BCTM 8.4 

Control Gate Layer 

CMOS Gate Layer 

Fig. 5. SEM cross-section of the HBT structure after 

deposition of the control gate layer for the flash memory. 

A primary requirement from the system side with 

respect to HBT integration was the simultaneous 


Nachdrucke 


102 

Reprints of 


availability of high-fT and high-BVCEO transistors. The 

challenge was to fulfill this requirement with a minimum 

of additional mask and process steps, compared to the 

underlying RF-CMOS process. 

Essential structure and integration features of the 1- or 

2-mask HBT module which both can be used for the 

BiCMOS option were already described in detail [4, 5]. 

Meanwhile, we explored the performance limits of our 

low-cost HBT approach, with the best results shown in 

Fig. 7. The demonstrated 140GHz fT and 150GHz fmax 

were reached at 2V BVCEO , 7V BVCES, and a current gain 

of 400 (@ 0.7V VBE). 

f T or f max (GHz) 

160 

140 

120 

100 

80 

60 

40 

20 

0 

IV. LDMOS Module 

Integration of RF n-and p-LDMOS transistors into 

CMOS or BiCMOS allows the use of complementary 

circuit techniques and enables efficient solutions for linear 

RF power amplifiers, power switches, DC/DC converters 

and high voltage IO circuits. 

f T or f max (GHz) 

A E = 10x(0.24x0.82)µm 2 

10 -4 

f max 

10 -3 

Details of the 2-mask, complementary LDMOS module 

used for this platform, were previously described [2]. In 

addition to n-LDMOS transistors with breakdown voltages 

near 30V, isolated n-LDMOS and p-LDMOS transistors 

f T 

V CE = 1.5V 

Collector Current (A) 

10 -2 

Fig. 7. f T and f max vs. collector current for a high-f T HBT. 


can be fabricated on the same wafer and achieve 

breakdown voltages of 11.5V and -13.5V and fT/fmax 

values of 21/47GHz or 13/30GHz (Fig. 8), respectively. 

V. Flash Memory Module 

A modular NVM technology, embedded into a 

BiCMOS process, has significant potential for a range of 

important system-level applications. Main requirements 

are cost-effectiveness and low power consumption, 

particularly for use in portable systems. Memories are 

needed ranging from small to medium density (from a few 

byte, e.g. for non-volatile registers, up to a few Mbit, e.g. 

for operation system storage). Cell size and performance 

must be sufficient for these memory sizes. The overall 

advantages of such embedded memory integration are the 

added system functionality and a reduced total system 

cost. 

As mentioned before, a standard floating-gate approach 

was chosen for CMOS compatibility. Uniform channel 

FN-tunneling was chosen as cell-programming mechanism 

due to its intrinsic low power consumption. One 

consequence is the need to handle the high voltages (+/- 

6V) used for this technique, which requires high-voltage 

(HV) devices. One challenge is to integrate the flash cells 

together with HV-MOS transistors at low additional cost 

in terms of mask count and process steps. 

The developed flash module needs 4 additional mask 

steps on top of the baseline BiCMOS flow, while sharing 

process steps for flash-cells, HV-MOS and CMOS devices 

[3]. The single cells (Fig. 3) show a writing time of as low 

as 1µs for programming with Vprg = 16V (+/-8V at gate 

and well) and a 4V VT-window between the written and 

erased state (Fig. 9). An endurance of 10 5 write and erase 

40 

30 

20 

V = - 8V 

DS 

fmax 10 

V = - 4V 

DS 

fT -2.5 -2.0 -1.5 -1.0 -0.5 

V (V) GS 

10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 

3 

2 

1 

0 

+16V +14V 

+12V 

-12V 

-1 

-2 

-14V 

-16V 

Fig. 8. Measured (data points) and simulated (solid lines) fT and fmax vs. VGS characteristics of a p-LDMOS transistor. 

-3 

Pulse Width (sec) 

Fig. 9. Transient characteristics of a flash memory cell for 

different programming voltages. 

134 

V T (V) 

IEEE BCTM 8.4 

cycles has been demonstrated. The HV-MOS transistors 

show a breakdown voltage of >10V, which is sufficient 

for this application. 1-Mbit, functional demonstrator

memories (Fig. 10) were fabricated, thus showing the 

feasibility of the process for memories of this density. 

Fig. 10. Micrograph of the 1-Mbit demonstrator flash memory, 

together with the top view on the memory-array before 

formation of the metal interconnects. 

Table I summarizes all devices offered under use of the 

full mask step count of 29. 

TABLE I 

DEVICE SUMMARY OF THE 29-MASK BICMOS PROCESS 

• HBTs: up to 4 devices with peak-fT/BVCEO values 

ranging from 29GHz/7V to 140GHz/2V 

• NMOS and isolated NMOS transistors with 

570µA/µm IDS and 10pA/µm IOFF @ VDS= 2.5V 

• PMOS transistors with 290µA/µm IDS and 10pA/µm 

IOFF @ VDS= 2.5V 

• MOS varactor with 3.2:1 tuning range 

• Junction varactor with 1.7:1 tuning range 

• n-LDMOS: several devices with fT/BVDSS values in a 

range of 17GHz/26V to 23GHz/15V 

• Isolated NLDMOS: 11.5V BVDSS, 21GHz peak-fT 

• PLDMOS: -13.5V BVDSS, 13GHz peak-fT 

• Embedded flash memory: Floating gate cells, 

uniform channel FN tunneling for cell-programming 

• HV MOS transistors: p- and n-type, BV> 10V 

• Resistors: from 6Ω up to 2kΩ sheet resistance 

• Schottky diode: 180GHz RC cut-off frequency 

• MIM capacitor: 1fF/µm 2 up to 2fF/µm 2 cap density 

For further device details, see also references [2, 3, 5] 

VI. PROCESS QUALIFICATION RESULTS 

Essential parts of the process, such as the CMOS core, 

and the 1-mask, 80GHz HBT module were already 

qualified. For other ones, as the LDMOS module, 

qualification is just running. Table II and Fig. 11 show 

exemplary some results. Table II summarizes the stress 

tests with SRAMs we used as CMOS qualification 

135 

Nachdrucke 


Reprints of 


devices. Fig. 11 shows an intrinsic HBT reliability 

characteristics. 

TABLE II 

1-MBIT SRAM STRESS TEST SUMMARY 

Pass criteria: continuity test, stand-by current of all 

blocks, functionality at 4 different voltages, ... 

• HTOL (2.75V, 125°C, 1MHz, 1000hours, 336DUTs) 

Test passed with 2/336 fails in different lots 

• Static Bake (150°C, 1000hours, 120DUTs) 

Test passed with 0/120 

• AATC (-65°C to 150°C, 1000cycles, 90DUTs) 

Test passed with 0/90 

• Pressure Cooker (121°C, 100% RH, 2bar, 168hrs, 

90 DUTs) Test passed with 0/90 

• EFRS (2.5V, 125°C, 1MHz, 48hours, 1278DUTs) 

0.4% fail (5/1278) 

Lifetime (hours) 

10 3 

10 4 

10 5 

10 6 

10 7 

10 8 

10 

1 10 100 

1 

10 2 

T = 150°C 

Stress Current I (mA) E 

Fig. 11. Current dependence of lifetime (for 10% βdegradation 

@ V BE= 0.7V ) for an array with four 80GHz 

HBTs in parallel. 

VII. SUMMARY AND CONCLUSIONS 

In summary, we have demonstrated a low-cost, modular 

SiGe:C BiCMOS process which offers up to four different 

HBT types, including high-fT and high-BVCEO transistors, 

several n-LDMOS and p-LDMOS devices with excellent 

RF performance, and an embedded, low-power flash 

memory. The combination of these modules with a highly 

integrated digital CMOS backbone and advanced passive 

elements, with only 29 mask steps in total, meets the 

needs of the majority of current wireless and mixed-signal 

applications in a cost-effective way. 

REFERENCES 

V CB = 1V 

[1] B. Orner et al., Proc. of the 2004 BCTM, p. 203 

[2] K. E. Ehwald et al., Proc. of the ESSDERC 2004, p. 121 

[3] A. Fox et al., Proc. of the ICM2004, p. 463 

[4] D. Knoll et al., IEDM 2002 Tech. Dig., p. 783 

[5] D. Knoll et al., Proc. of the 2004 BCTM, p. 241 


I E @ f T,max 

11 years 

T = 100°C 

IEEE BCTM 8.4

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104 

Abstract 

Reprints of 


Materials Science in Semiconductor Processing 8 (2005) 273–278 

Spectroscopic ellipsometry for in-line process control of 

SiGe:C HBT technology 

O. Fursenko a,� , J. Bauer a , P. Zaumseil a , D. Kru¨ ger a , A. Goryachko b , 

Y. Yamamoto a , K. Ko¨ pke a , B. Tillack a 

a IHP, Im Technologiepark 25, D-15236 Frankfurt, Oder, Germany 

b Brandenburg University of Technology Cottbus, Postfach 101344, D-03013 Cottbus, Germany 

Available online 18 October 2004 

Spectroscopic ellipsometry (SE) was successfully applied for in-line thickness and composition control of graded 

SiGe:C heterojunction bipolar transistors (HBTs). We have calculated a thickness of Si-cap and SiGe:C base, split into 

the gradient and plateau part and Ge content in the plateau. The procedure included the creation of databases for the 

refractive index dispersion of all components of HBT stacks using simple one-layer structures, with thickness and 

composition calibrated by X-ray diffractometry (XRD). These databases (e.g. SiGe:C optical constants vs. Ge content) 

were applied for thickness and composition characterization of graded HBTs with different profile shapes. The 

difference between SE and XRD for the estimation of the main structural parameters is discussed. Finally, the 

suitability of SE for measuring wafer uniformity of HBT layer thickness and composition was demonstrated, allowing a 

proper and efficient fine-tuning of the epitaxial growth process. 

r 2004 Elsevier Ltd. All rights reserved. 

PACS: 78.20.-e; 78.20.C 

Keywords: Spectroscopic ellipsometry; SiGeC 


Present day SiGe:C heterojunction bipolar transistor 

(HBT) technologies require precise, fast, nondestructive 

and in-line thickness and composition control of HBT 

layer stacks with wafer mapping capability for patterned 

product wafers [1]. A well-developed in-line control 

technique for determination of thickness and Ge 

composition, such as X-ray diffractometry (XRD) [2], 

� 

Corresponding 

fax:+49 335 56 25 661 

author. Tel.: +49 335 56 25 328; 

E-mail address: fursenko@ihp-microelectronics.com 

(O. Fursenko). 


1369-8001/$ - see front matter r 2004 Elsevier Ltd. All rights reserved. 

doi:10.1016/j.mssp.2004.09.058 


is very accurate, especially in the Ge content determination 

for SiGe HBT. However, for SiGe:C HBT it is 

difficult to separate carbon and germanium contributions 

in the XRD signal and only ‘‘effective’’, i.e. mixed 

Ge and C concentration can be obtained. Other drawbacks 

of XRD are: being time consuming for use in 

production environment, it does not allow for easy 

lateral mapping and it is unsuitable for measurements 

on patterned wafers in small areas (o100 � 100 mm 2 ). 

Secondary ion mass spectrometry (SIMS) can measure 

complete structures, including Ge, B and C profiles, but 

is expensive, slow and needs a large sample area. The 

most promising candidate for in-line process control is 

spectroscopic ellipsometry (SE) [3]. It is fast, nondes-

274 

tructive, reproducible and allows fast wafer mapping, 

but it needs some preliminarily obtained additional 

information, namely the optical constants (refractive 

index n and extinction coefficients k) of materials formed 

in the structure. 

As it is known from the literature, SE has been 

successfully applied for SiGe HBT characterization 

[4–6]. In [4,5] simple HBT film stacks without gradient 

were measured and calculated. In [6] HBTs with graded 

or abrupt profiles were investigated, but similar to [5], 

analysis was based on the database of Si1�xGex optical 

constants currently provided in the literature for relaxed 

materials. 

While in the literature there is no deficiency of optical 

constants for Si1�xGex alloys [4,7–11], the information 

of optical constants of Si 1�x�yGe xC y films is limited. 

The effect of C doping on the dielectric function of 

Si1�x�yGexCy was described in [12–14] using critical 

points (CP) analysis for limited C concentrations without 

extraction of accurate values of the optical 

constants. Zollner et al. [4] built a matched database 

for Ge concentration of 21% and C concentration up to 

1.3%. However, these data are not sufficient to describe 

the whole Ge-concentration profile. 

In our work SE was successfully applied for graded 

SiGe:C HBT characterization. After the determination 

of optical constants of SiGe:C on Ge content in the 

range of 0–30% for C�0.3%, we calculated the 

thicknesses of a Si-cap and a SiGe:C base, being split 

into the gradient and plateau part, and Ge content in the 

plateau part. SE results were compared with data 

obtained by XRD technique. Finally, the suitability of 

SE for wafer uniformity evaluation of HBT layer 

thickness and composition is demonstrated, allowing a 

proper and efficient fine tuning of the epitaxial growth 

process. 

2. Experimental details 

In order to develop a model of SiGe:C optical constants, 

sets of strained Si 1�xGe x and Si 1�x�yGe xC y (0oxo0.32, 

y�0.003) layers with about 50 nm thickness were deposited 

pseudomorphically on Si (1 0 0) using reduced pressure 

chemical vapor deposition (RP-CVD) as described in [15]. 

Also, the sets of graded SiGe and SiGe:C HBT structures 

with thickness variation in the cap (�50–70 nm), plateau 

(�20–30 nm) and gradient (�5–30 nm, from 20% down to 

�7% Ge concentration) were grown. 

SE measurements of tg C and cos D were done in the 

energy range of 1.5–5.2 eV using an automated, smallspot 

(14 � 28 mm 2 ) spectroscopic ellipsometer (KLA- 

TENCOR UV1280) with a 701 angle of incidence. SE 

analysis consisted of solving the inverse ellipsometric 

problem, while performing a mathematical regression 

analysis between experiment and theory. In this way the 


Nachdrucke 


O. Fursenko et al. / Materials Science in Semiconductor Processing 8 (2005) 273–278 

n,k 

(a) 

En, eV 

7 

6 

5 

Reprints of 


4 

SiGe:C, Ge% C~0.03% 

3 

0 

5 

2 

10 

15 k 

1 

20 

25 

0 

1.5 2.0 

30 

2.5 3.0 3.5 4.0 4.5 5.0 

E, eV 

4.4 

4.2 

4.0 

3.8 

3.6 

3.4 

3.2 

difference between calculated and measured spectra 

(tg C, cos D) is minimized within a dedicated structural 

model [3] with known optical constants dispersions of all 

components. 

XRD measurements were carried out in a double 

crystal diffraction scheme with CuKa radiation and 

symmetrical 400 reflection [2] for thickness and compo- 


n 

SiGeC SiGe 

En0 

En1 

En2 

3.0 

0 5 10 15 20 25 30 35 

(b) 

Ge,% 

Ed, eV 

2.5 

2.0 

1.5 

1.0 

0.5 

SiGeC SiGe 

Ed0 

Ed1 

Ed2 

0.0 

0 5 10 15 20 25 30 35 

(c) 

Ge,% 

Fig. 1. (a) SiGe:C optical constants for various concentrations 

of Ge and C�0.03%, (b) dependence on Ge content of HO 

resonance energies (E n0, E n1 and E n2) and (c) damping energies 

(Ed0, Ed1 and Ed2).

Nachdrucke 


106 

Reprints of 


sition characterization of single SiGe and SiGe:C layers 

as well as HBT stacks. Auger electron spectroscopy 

(AES) and SIMS were used additionally for Ge profile 

characterization. 

3. Results and discussion 

3.1. Optical constants of SiGe and SiGe:C 

The series of uniform single layer SiGe and SiGe:C 

samples were used to build a matched databases of 

tg Ψ 

(a) 

(b) 

tg Ψ 

tg Ψ 

(c) 

0.8 

Si cap var. : sample 

0.7 

1 - standard 

2 - > cap 

0.6 

3 - < cap 

0.5 

0.4 

0.3 

0.2 

0.1 

∆ 

-0.7 

tg Ψ 

cos cos 

∆ 

-0.8 

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 

E, eV 

0.8 

SiGe:C grad. var. : sample 

0.7 

1 - standard 

4 - > grad 

0.6 

5 - < grad 

0.5 

0.4 

0.3 

0.2 

0.1 

0.5 

0.4 

0.3 

0.2 

0.1 


O. Fursenko et al. / Materials Science in Semiconductor Processing 8 (2005) 273–278 275 

-0.3 

-0.4 

-0.5 

-0.6 

-0.9 

-1.0 

-0.3 

-0.4 

-0.5 

-0.6 ∆ 

-0.7 

tg Ψ cos 

cos ∆ 

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 

E, eV 

0.8 

SiGe:C plateau var. : sample 

0.7 

1 - standard 

6 - > plateau 

0.6 

7 - < plateau 

-0.8 

-0.9 

-1.0 

-0.3 

-0.4 

-0.5 

-0.6 ∆ 

-0.7 

tg Ψ cos 

cos ∆ 

-0.8 

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 

E, eV 

-0.9 

-1.0 

Fig. 2. (a) SE measurements (symbol) and best fit model (lines) 

of tg C and cos D vs energy for SiGe:C HBTs with different 

thickness of Si-cap layer, (b) SiGe:C gradient and (c) SiGe:C 

plateau. 


the refractive index (RI) dispersion for Si1�x�y 

GexCy (0pxp0.32, y ¼ 0 and 0.003). Thickness 

and composition were calibrated using XRD 

under assumption that Ge content in SiGe:C layers is 

the same as in the SiGe, grown under identical 

conditions. 

To find the RI dispersions, reproduced through 

the dielectric constant, the semiempirical harmonic 

oscillator (HO) (Lorenz) model [16] with 

(a) 

Ge content, % 

(b) 

Ge content, % 

(c) 

15 

10 

5 

SiO2 

d - ? 

Si-cap 

d - ? 

25 

sample 1 

SIMS 

20 SE model 

d - ? 

grad 

SiGeC 

Ge,% - ? 

d - ? 

plateau 

0 

0 20 40 60 80 100 120 140 

Depth, nm 

25 

sample 4 

SIMS 

20 SE model 

15 

10 

5 

0 

0 20 40 60 80 100 120 140 

Depth, nm 

Fig. 3. (a) SE model for calculation with fitted parameters, (b) 

comparison of the Ge profiles obtained from SIMS and SE for 

sample 1 and (c) sample 4.

276 

d(Si cap), nm 

d(SiGeC gradient), nm 

d(SiGeC plateau), nm 

d(SiGeC total), nm 

Ge content, % 

70 

65 

60 

55 

50 

40 

30 

20 

10 

0 

30 

25 

20 

60 

55 

50 

45 

40 

35 

22 

21 

20 

19 


SE 

XRD 

Nachdrucke 



1 2 3 4 5 6 7 

Sample 

Fig. 4. Thickness of Si-cap, SiGe:C gradient, SiGe:C plateau, 

SiGe:C total and Ge content in SiGe:C plateau obtained by SE 

and XRD. 

four different oscillator levels was used: 

P 

Hk 

k 

� ¼ 1 þ 

1 � P 

nkHk 

k 

; where Hk ¼ 

Reprints of 


16pNkR2 yr3 0 

ðE2 nk � E2 þ iEdkEÞ e�iFk 

and nk is the local field correction factor, Ry and r0 are 

the Rydberg constant (13.6058 eV) and Bohr radius 

(0.0529177 nm), N k, E nk, E dk, F k are the concentration, 

resonant energy, damping energy and phase of the koscillator, 

respectively. As a result, the dispersions of 

optical constants for Si1�x�yGexCy (0oxo0.32, y�0 

and 0.003) were calculated and are shown in particular 

for the case of y�0.003 in Fig. 1a. 

The parameter values for RI dispersion model, 

namely three HO resonant (E n) and damping (E d) 

energies for SiGe and SiGe:C, fall in the range of 3–4.5 

and 0.25–2.5 eV, correspondingly (Figs. 1b and c). From 

the CP singularities point of view, it is possible to relate 

the En0 and En2 with E1 and E2 optical transitions from 

the conduction band to the valence bands. With 

increasing Ge concentrations, the main changes are 

observed near E1: the E n0 peak shifts toward lower 

energies and broadens (Ed0 increase) due to alloy 

scattering, strain effects and increasing spin–orbit 

splitting [7,13]. It corresponds to a shifted position of 

the peak value of the RI real part (Fig. 1a) and follows 

the same trend as observed in [4,7–11] for SiGe. 

Therefore, E n0 can be considered as a basis for 

stoichiometry determination using SE. The En2 peak 

has only a small shift to higher energies with increasing 

Ge composition, but it broadens (E d2 increases) and 

reduces its amplitude similar to En0. 

The addition of C to SiGe results in a small blue shift 

of the En0 and En1 with nonshifted En2 and increasing 

broadening of CP. The same tendency was observed for 

the C-influence on SiGe in [12–14]. This dependence can 

be attributed to the strong local strain near the carbon 

atoms and to the internal strain splitting of electronic 

bands [13]. 

Using the alloy mixing algorithm [17] the database, 

e.g. composition x vs. Si 1�x�yGe xC y optical data, was 

built and applied for thickness and composition 

characterization of HBT film stack. 

3.2. SE analysis of HBT film stack 

In Fig. 2 the experimental results of tg C and cos D for 

7 HBTs with different Si-cap (samples 1–3) (a), SiGe:C 

gradient (samples 1,4,5) (b) and SiGe:C-plateau thickness 

(samples 1,6,7) (c) are plotted along with the best fit 

model. All thickness changes in different parts of HBTs 

were related to sample 1, which was considered as 

standard. Since the top Si-cap is highly absorbing in the 

UV-wavelength range, any variation in the underlying 

layers is correlated to changes in tg C and cos D mainly 


Nachdrucke 


108 

Reprints of 


in the visible spectral range, i.e. below 3.5 eV. Therefore, 

the ability to see through the Si-cap is suppressed and, 

for example, information about Ge content is obtained 

mainly from analyzing the E1 transitions. A four-layer 

stack model on Si substrate (Fig. 3a), consisting of a 

uniform SiGe:C layer, a graded SiGe:C layer, a Si-cap 

and native oxide layer was used. The final fitting 

parameter set included five variable parameters: SiGe:C 

plateau thickness with Ge content, SiGe:C gradient 

thickness and Si-cap thickness with native oxide on the 

surface. The gradient part was modeled as a parametric 

gradient layer with different shapes. For example, Figs. 

3b and c show the different profiles calculated by SE in 

comparison with SIMS measurements. 

Fig. 4 presents the numerical results for the SE-fitted 

Si-cap, SiGe:C-plateau, SiGe:C-gradient, SiGe:C total 

(estimated as sum of plateau and gradient part) 

thickness and Ge content in plateau in comparison with 

XRD results. For Si-cap and SiGe:C total thickness the 

data show a good agreement with only 1–2% deviation. 

In separate estimation of SiGe:C plateau and gradient 

layer thickness somewhat larger discrepancies up to 

15% were detected. The estimation of Ge content was 

obtained with relative discrepancy below 5%. 

In order to verify and explain our results, a correlation 

matrix was considered, which displays the statistical 

correlation between each pair of parameters selected for 

regression (Table 1). It is known that values close to zero 

represent nearly independent fit parameters. But values 

close to 71 represent a very strong correlation. It 

follows from our calculation that maximal value of 0.87 

was obtained for correlation of d(SiGe:C plat)–d(SiGe:C 

grad) parameters. It means that for these parameters a 

small degree of nonuniquness is possible. Also, estimation 

of XRD results [2] indicates that a relative accuracy 

of 10% in the plateau layer thickness estimation is 

possible. One discrepancy was found during comparison 

of results obtained with sample 4: while AES, SIMS and 

SE found a significant deviation from a linear increase of 

the Ge content in the gradient part (Fig. 3c), this could 

not be seen by XRD. We are still investigating a possible 

cause for this inconsistency. A comparably strong 

correlation: 0.61 between Ge content and d(Si-cap) and 

0.65 between Ge content and d(SiGe:C plat), which is 


O. Fursenko et al. / Materials Science in Semiconductor Processing 8 (2005) 273–278 277 

Table 1 

Correlation matrix of two-parameters correlation coefficients 


evident from analyzing the correlation coefficients 

(Table 1), effectively sets a lower limit for accuracy of 

the Ge content measurements. Also, since sensitivity of 

dielectric function with respect to Ge content is greater 

at photon energies around E1, the shielding of the 

SiGe:C base by the Si-cap layers will increase the 

uncertainty in concentration estimation in this case. But 

in general, the absolute errors of SE technique are 

related to the measurement error and accuracy of XRD 

calibration. 

All the above mentioned suggests a technological 

application as a deposition uniformity control tool in a 

process environment, which allows the adjustment of 

growth conditions in the CVD reactor. Fig. 5 shows a 

49-point diameter scan of HBT thickness and concentration 

across a 200 mm wafer measured by SE. These 

results demonstrate that a single recipe can measure not 

only a broad range of Si-cap and SiGe:C-base (separately 

plateau and gradient part) thickness, but also Ge 

content, and is sensitive to different shapes of the 

gradient part. 

4. Conclusion 

In our work, the SE technique was successfully 

applied for robust, stable and accurate in-line thickness 

and composition characterization of graded SiGe:C 

HBTs. As a first step we established the databases of 

refractive index dispersion for Si1�x�yGexCy 

(0pxp0.32, y�0.0 and 0.003) in the energy range of 

1.5–5.2 eV, using simple one-layer structures with thickness 

and composition calibrated by XRD. As a second 

step, these databases (e.g. SiGe:C optical constants vs. 

Ge-content) were applied for calculation of SiGe:C 

plateau thickness with different Ge-content, SiGe:C 

gradient thickness with different shape concentration 

profile, Si-cap thickness with native oxide on the surface. 

The obtained SE results were compared with XRD data. 

The relative difference between techniques for Si-cap 

and SiGe:C total thickness estimation was about 1–2%. 

For separate estimation of SiGe:C plateau and gradient 

layer thickness larger discrepancies up to 15% were 

Parameters Ge % d(SiGe:C plat) d(SiGe:C grad) d(Si cap) d(ox) 

Ge % 1.0 0.655 �0.451 �0.614 �0.005 

d(SiGe:C plat) — 1.0 �0.874 �0.227 �0.003 

d(SiGe:C grad) — — 1.0 �0.172 0.005 

d(Si cap) — — — 1.0 0.005 

d(ox) — — — — 1.0

278 

d(SiGe:C gradient), nm 

d(SiGe:C plateau), nm 

d(Si cap), nm 

Ge content, % 

70 

69 

68 

67 

66 

65 

64 

15.0 

14.5 

14.0 

13.5 

13.0 

12.5 

24.0 

23.5 

23.0 

detected. The estimation of Ge content was obtained 

with relative discrepancies below 5%. 

Nonetheless, we demonstrated that a single recipe 

could measure not only a broad range of Si-cap and 

SiGe:C base (separately plateau and gradient part) 

thickness, but also the Ge content. The measurement 

is sensitive to different shapes of the gradient part. 

The suitability of SE for controlling HBT layer 

thickness and Ge concentration wafer uniformity was 

demonstrated allowing a proper and efficient fine-tuning 

of the epitaxial growth process. 

References 

Mean: 66.65 

Std: 2.42% 

Mean:14.179 

Std: 3.38% 

Mean: 23.46 

Std: 1.21% 

19.0 Mean: 18.305 

Std:1.87% 

18.5 

18.0 

0 10 20 30 40 50 

Measurement point 

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110 

Reprints of 


Praseodymium silicate layers with atomically abrupt interface on Si„100… 

G. Lupina, a� T. Schroeder, J. Dabrowski, Ch. Wenger, A. Mane, 

G. Lippert, and H.-J. Müssig 

IHP-Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany 

P. Hoffmann and D. Schmeisser 

Angewandte Physik-Sensorik, BTU Cottbus, Konrad-Wachsmann-Allee 17, 03046 Cottbus, Germany 

�Received 28 March 2005; accepted 30 June 2005; published online 22 August 2005� 

Synchrotron radiation x-ray photoelectron spectroscopy was applied to study the solid state reaction 

between praseodymium and thin silicon dioxide layers on Si�100�. Nondestructive depth profiling 

studies by variation of the incident photon energy indicate after praseodymium deposition at room 

temperature the reaction of the upper silicon dioxide to praseodymium oxide and silicide. 

High-temperature annealing of films with an appropriate praseodymium / silicon dioxide ratio 

results in homogeneous praseodymium silicate films with an atomically abrupt interface. Ab initio 

calculations corroborate the results of the photoemission study. © 2005 American Institute of 

Physics. �DOI: 10.1063/1.2032596� 

Vertical scaling of gate dielectrics is a consequence of 

the miniaturization of complementary metal oxide semiconductor 

�CMOS� devices. However, the increasing gate leakage 

current sets the scaling limit of the conventional silicon 

dioxide �SiO 2� gate oxide to a maximum of 1.0 nm. 1 A new 

approach is to replace SiO 2 by an oxide of higher dielectric 

constant k. 2 Transition metal and rare earth metal silicates are 

the most promising post-SiO 2 gate dielectrics but many materials 

problems remain. 3,4 For example, the thermally induced 

phase separation of certain silicates �e.g., ZrSi xO y, 

HfSi xO y� compromises the processing window. 3,5 

In this letter, we describe praseodymium �Pr� silicate 

films �k�15� formed by solid state reaction between metallic 

Pr and thin SiO 2 layers. We find that the films can be 

prepared on Si�001� without a low-k SiO 2 interface layer. 

This silicate exhibits excellent thermal stability up to 900 °C. 

SiO 2 films 1.2 and 2.6 nm thick were grown on p-type 

Si�100� wafers by rapid thermal oxidation. Pr films of 1 nm 

were deposited at a rate of 0.5 nm/min by e-beam evaporation. 

The substrates were kept at room temperature �RT� and 

the chamber pressure was 10 −8 mbar. Subsequently, in situ 

postdeposition annealing �PDA� at 600 °C of 1 min duration 

was applied. The reaction was monitored by synchrotron radiation 

x-ray photoelectron spectroscopy �SR-XPS� at 

BESSY II �UPGM 49/2�. 6 Photon energies of 440, 660, and 

920 eV were chosen to allow depth profiling over the whole 

film thickness. Spectra were referenced to the Au 4f 7/2 line 

�84.0 eV� and measured under normal takeoff angle. The 

dielectrics were further characterized by x-ray diffraction 

�XRD� using Cu K � radiation and by transmission electron 

microscopy �TEM� with a Philips CM300. 

Figure 1 shows SR-XPS Si 2p data. The Si 2p lines 

measured after various preparation steps are displayed for 

several excitation energies. The SiO 2/Si reference spectra of 

the 2.6 nm �Fig. 1�a�� and 1.2 nm �Fig. 1�b�� SiO 2 films 

exhibit the Si substrate signal with its maximum at 99.3 eV. 

The SiO 2 emission is centered around 103.9 eV for the 

thicker �Fig. 1�a�� and around 103.7 eV for the thinner �Fig. 

a� Author to whom correspondence should be addressed; electronic mail: 

lupina@ihp-microelectronics.com 

APPLIED PHYSICS LETTERS 87, 092901 �2005� 


1�b�� oxide film. The Si 4+ 2p binding energy decrease with 

reduced SiO 2 thickness was attributed mainly to an image 

charge interaction across the interface, 7 a conclusion recently 

supported by XPS model studies using epitaxial SiO 2 films 

on Mo�112� single crystals. 8 

After Pr deposition, both the bulk and oxide Si 2p core 

levels shift by 0.25 eV towards higher binding energies. This 

indicates that the bands in the surface of Si move downwards 

in response to Pr deposition. 9 Further evidence is given by an 

additional displacement �0.2 eV� of the Si 2p peaks towards 

higher binding energies when the excitation energy decreases 

FIG. 1. Si 2p SR-XPS study of Pr silicate films on Si �a� 

1 nm Pr/2.6 nm SiO 2 system and �b� 1 nm Pr/1.2 nm SiO 2 system. 

0003-6951/2005/87�9�/092901/3/$22.50 © 2005 American Institute of Physics 

87, 092901-1 

Downloaded 16 Jan 2006 to 194.95.141.238. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp

from 920 to 440 eV. The presence of the shift means that an 

additional electrical dipole moment is created across the dielectric. 

Formally, this dipole may be caused by positive 

fixed charge injected into the film �e.g., Pr ions from the 

metal� and/or by a change in the charge balance between the 

substrate and the surface of the dielectric �e.g., charge transfer 

between metal and substrate�. Ab initio calculations indicate 

that the injection of Pr interstitials into SiO2 �Fig. 2� 

from Pr metal is energetically unfavourable by approximately 

2 eV or more. Furthermore, the incorporation of Pr 

atoms into SiO2 �e.g., as substitutional Pri� would, for Fermi 

levels within the energy gap of Si, lead to the formation of 

mostly negative charges. We thus assign this band bending to 

charge transfer across the dielectric from the metal to the 

substrate. 

The Pr/SiO2 system is thermodynamically unstable at 

RT. The extra emissions at 98.3 and 98.5 eV in the 

1 nm Pr/2.6 nm SiO2 and the 1 nm/1.2 nm SiO2 systems, 

respectively, indicate Pr silicide formation. These peaks are 

more pronounced in the surface sensitive mode �h� 

=440 eV� locating the reaction at the Pr/SiO2 interface. 

From ab initio calculations we estimate that metallic Pr has 

sufficient affinity to drain O from SiO2 even by creating 

oxygen vacancies in the oxide. The calculations also confirm 

that the reaction in which Pr decomposes SiO2 into PrSi2 and 

Pr2O3 is exothermic. This is in line with the analysis of the 

Pr 3d spectra �not shown�. After Pr deposition only 20% of 

the deposited film remains in the metallic state. 

Ab initio calculations indicate that the oxidation of PrSi2 to Pr2Si2O7 is exothermic no matter whether the Pr for this 

reaction arrives from the metal or from Pr2O3 and whether 

oxygen is supplied from O2 or from SiO2. Indeed, after PDA 

the silicide emission in Fig. 1 disappears. This is observed 

for the thin as well as for the thick SiO2 layer. Furthermore, 

the substrate Si 2p peak shifts to its original position �99.3 

eV�. Annealing removes therefore the band bending induced 

by Pr deposition. The chemically shifted Si 2p oxide-related 

signal from the 1 nm Pr/2.6 nm SiO2 system becomes broad 

��2.9 eV�. In the surface sensitive spectrum �h�=440 eV�, 

the dominating peak is located at 102.1 eV. From electronegativity 

rules, this Si 2p component is attributed to Pr 

silicate. 10 In addition, a SiO2 line around 103.9 eV is still 

visible at the excitation of 440 eV and raises in intensity with 

increasing photon energy. This proves the presence of unreacted 

SiO2 underneath the Pr silicate. In contrast, after annealing 

the 1 nm Pr/1.2 nm SiO2 system, the Si 2p substrate 

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092901-2 Lupina et al. Appl. Phys. Lett. 87, 092901 �2005� 

FIG. 2. Interstitial Pr +1 ion in amorphous SiO 2. Dark, middle and bright 

gray circles are Si atoms, Pr ions, and O atoms, respectively. 

FIG. 3. O 1s SR-XPS study of Pr silicate films prepared by using �a� 2.6 nm 

and �b� 1.2 nm SiO 2 layers on Si. 

peak �99.3 eV� is accompanied only by a single oxide Si 2p 

peak �full width at half maximum �FWHM�=1.7 eV� centered 

around 102.2 eV. Changing the excitation energy reveals 

no sign of interfacial SiO2. It is therefore concluded 

that PDA completely converts the underlying SiO2 layer into 

a homogeneous Pr silicate film; in particular, there is no evidence 

for an interfacial SiO2 layer. 

Figure 3 presents the O 1s spectra. The SiO2 O 1s reference 

lines on Si�001� are at 533.2 eV. After Pr deposition, 

the O 1s spectra exhibit three features giving further evidence 

for a RT reaction. In case of the 2.6 �1.2� nm SiO2 film, the O 1s peaks are located at 530 �530.3�, 531.3 

�531.8�, and 533.5 �533.5� eV. These peaks are assigned to Pr 

oxide, Pr silicate, and SiO2, respectively. Depth profiling by 

variation of the photon energy from 660 to 920 eV results in 

both cases in a decrease of the intensities of the Pr oxide and 

Pr silicate O 1s peaks relative to the SiO2 O 1s line. This 

proves that Pr oxide and Pr silicate are located on top of 

unreacted SiO2. It is noted that the O 1s line of unreacted 

SiO2 is shifted by about 0.3 eV towards higher binding energy 

after Pr deposition. This behavior was already reported 

for the Si 2p substrate peak. It supports the statement that Pr 

induces a surface potential change by downward band bending 

due to charge injection from the metal into Si. 

The O 1s spectra after annealing are in line with the Si 

2p signals. In case of the 2.6 nm SiO2 system, the O 1s 

spectrum in Fig. 3�a� is dominated by the peak at 531.1 eV, 

indicative of Pr silicate. A shoulder at 533.3 eV is visible and 

shows residual SiO2. Its location at a binding energy 0.2 eV 

below that after metal evaporation shows again that band 

bending in the Pr/SiO2/Si system is reduced after annealing. 

Raising the photon energy strongly increases the SiO2 peak 

intensity with respect to the Pr silicate line. This is in accor- 

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112 

Reprints of 


092901-3 Lupina et al. Appl. Phys. Lett. 87, 092901 �2005� 

FIG. 4. XPS O 1s spectra �a� and specular �−2� XRD scans �b� of annealed 

Pr silicate films. 

dance with the Si 2p study and proves the presence of SiO2 underneath the Pr silicate. The complete reduction of the 

initial SiO2 layer is possible when the same amount of Pr is 

evaporated on a thinner SiO2 layer. The O 1s spectra of the 

1 nm Pr/1.2 nm SiO2 system in Fig. 3�b� show no sign of 

SiO2 after PDA. These spectra exhibit a sharp line 

�FWHM=1.5 eV� and the position at 531.2 eV is consistent 

with Pr silicate. 10,11 The stoichiometry of the Pr silicate appears 

to be uniform over the whole film thickness, as neither 

peak shape nor position are influenced by varying the excitation 

energy �660–920 eV�. It is noted for completeness that 

after annealing the Pr 3d5/2 peak �not shown� is located at 

934.5 eV which is �0.7 eV higher than for pure Pr2O3. 12 

This is in agreement with electronegativity rules, pointing to 

the formation of mixed PrxSiyOz. The absence of a SiO2 interface layer is important for the 

use of amorphous Pr silicate films as high-k dielectrics because 

SiO2 deteriorates the total capacitance value due to its 

lower dielectric constant. A further point is that the films 

must be thermally stable, i.e., no phase segregation and no 

crystallization must occur under CMOS process conditions. 

These points are illustrated by a combined XPS and 

XRD study in Fig. 4. The XPS spectra in Fig. 4�a� show that 

the O 1s peak of the Pr silicate film remains unchanged after 

several 1 min UHV annealing steps in the range from 700 to 

900 °C. In particular, it does not decompose into metal oxide 

and SiO2 peaks, resulting in O 1s spectra similar to the ones 

reported after Pr deposition �Fig. 3�. In contrast, phase seg- 

3 

regation was reported for �ZrO2�x�SiO2�y and 

5 

�HfO2�x�SiO2�y silicates when heated to �800 °C. The 

driving force was attributed to the crystallization of the segregated 

metal oxide grains. These randomly oriented grains 

give rise in specular �−2� XRD scans to various metal oxide 

Bragg peaks. Figure 4�b� shows the �−2� XRD scan of the 

annealed Pr silicate film on Si�100�. No Bragg peaks apart 


FIG. 5. Cross-section TEM images of Pr silicate films prepared by using �a� 

2.6 nm and �b� 1.2 nm SiO 2 layers on Si. 

from Si�100� substrate reflections are observed, confirming 

that Pr silicates remains amorphous up to 900 °C. 

Cross-section TEM images in Fig. 5 corroborate the SR- 

XPS results. Figure 5�a� shows the dielectric formed by reaction 

of 1 nm Pr with 2.6 nm SiO 2 on Si�100�. According to 

SR-XPS, the structure with the bright interface layer is interpreted 

as a Pr-silicate/SiO 2/Si�100� stack. Figure 5�b� shows 

the Pr silicate system prepared by solid state reaction between 

1 nm Pr and 1.2 nm SiO 2 on Si�100�. An atomically 

sharp interface is observed between the Pr silicate and Si, 

confirming the complete transformation of SiO 2. 

In summary, the solid state reaction between Pr and SiO 2 

on Si�100� was tailored to prepare Pr silicate dielectrics without 

an SiO 2 interface layer. This result and the excellent thermal 

stability make Pr silicate systems interesting for high-k 

applications. Further studies on metal-oxide-semiconductor 

field effect transistors with integrated Pr silicate gate dielectrics 

are currently under way to extract the Pr silicate/Si interface 

quality �roughness, defects, etc.�. 

1 

G. Lucovsky, J. Vac. Sci. Technol. A 19, 1553 �2001�. 

2 

G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys. 89, 5243 

�2001�. 

3 

C. Krug and G. Lucovsky, J. Vac. Sci. Technol. A 22, 1301 �2004�. 

4 

A. Sakai, S. Sakashita, S. Zaima, and S. Miyazaki, Appl. Phys. Lett. 85, 

5322 �2004�. 

5 

J.-H. Ha, D. Chi, and P. C. McIntyre, Appl. Phys. Lett. 85, 5884 �2004�. 

6 

D. Schmeisser, P. Hoffmann, and G. Beuckert, Electronic Properties of the 

Interface formed by Pr2O3 growth on Si(001), Si(111) and Si(0001) Surfaces 

in Materials for Information Technology, Devices, Interconnects and 

Packaging, Springer �2005�. 

7 

A. Pasquarello, M. Hybertsen, and R. Car, Phys. Rev. B 53, 10942 �1996�. 

8 

T. Schroeder, A. Hammoudeh, M. Pykavy, N. Magg, M. Baeumer, and 

H.-J. Freund, Solid-State Electron. 45, 1471 �2001�. 

9 

K. Horn, Appl. Phys. A: Solids Surf. 51, 289 �1990�. 

10 

D. Schmeisser, Mater. Sci. Semicond. Process. 6, 59 �2003�. 

11 

T. L. Barr, J. Vac. Sci. Technol. A 9, 1793 �1991�. 

12 

S. Lütkehoff, M. Neumann, and A. Slebarski, Phys. Rev. B 52, 13808 

�1995�. 

Downloaded 16 Jan 2006 to 194.95.141.238. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp

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Reprints of 


High Quality Layered Pr 2 Ti 2 O 7 /SiO 2 MIM Capacitor for Mixed- 

Signal Applications 

Ch. Wenger, R. Sorge, T. Schroeder, A.U. Mane, D. Knoll, J. Dabrowski, and H.-J. Müssig 

IHP, Im Technologiepark 25, D – 15236 Frankfurt (Oder), Germany 

Tel: ++335 5626 135, Fax: ++335 5625 681, email: wenger@ihp-microelectronics.com 

Abstract — The performance of layered Pr 2Ti 2O 7/SiO 2 

MIM capacitors for mixed-signal and RF device applications 

is presented for the first time. A capacitance density of 

3.2 fF/µm 2 with a very low leakage parameter of 5 fA/pFV 

and quadratic voltage capacitance coefficient of –100 ppm/V 2 

was achieved. The extrapolated operating voltage for 10 

years lifetime is 3 V. 

Index Terms — high-k dielectric, metal-insulator-metal 

(MIM) capacitor, RF application, voltage linearity, thin film 

devices. 


Metal-Insulator-Metal (MIM) capacitors as passive 

devices for Radio-Frequency (RF) and mixed-signal 

Integrated Circuit (IC) applications have attracted much 

attention. The replacement of conventional SiO 2 and Si 3 N 4 

by high-k dielectric materials is essential to reduce the 

capacitor area. Recently, several high-k materials, such as 

Al 2 O 3 , AlTiO x , AlTaO x , (HfO 2 ) 1-x (Al 2 O 3 ) x , HfO 2 , ZrO 2 , 

Y 2 O 3 , Ta 2 O 5 , PrTi x O y and Pr 2 O 3 have been investigated as 

potential candidates for MIM capacitor dielectrics [1-9]. 

According to these reports, the high-k materials, except 

Ta 2 O 5 , exhibit unacceptable high positive quadratic 

voltage capacitance coefficients (α). As alternatives, 

layered dielectrics like SiO 2 /HfO 2 and Ta 2 O 5 /HfO 2 /Ta 2 O 5 

have been introduced, showing excellent α values [10, 

11]. In this letter, we present a new high-k MIM stack 

with a capacitance density of 3.2 fF/µm 2 and a low 

quadratic voltage coefficient of -100 ppm/V 2 . 

II. EXPERIMENTS 

Polycrystalline TiN films were radio frequency 

x 

magnetron sputtered on Si(100) substrates from a pure Ti 

target using Ar and N as sputtering gases at room 

2 

temperature. SiO films with various thicknesses were 

2 

deposited by Plasma-CVD at 400 °C. Pr2Ti2O7 dielectric 

films with various thicknesses were prepared by electron 

beam evaporation of a Pr O /TiO mixture at a substrate 

2 3 2 

temperature of 30 °C. The pressure during deposition was 

10 -6 

mbar. Finally, Al-dots with 400 µm diameter were 

evaporated. 

α (ppm/V 2 ) 

3000 

2500 

2000 

1500 

1000 

500 

0 

-500 

SiO 2 

Pr 2 Ti 2 O 7 

-1000 

0 2 4 6 8 10 12 

Capacitance Density (fF/µm 2 ) 

Fig. 1: Quadratic voltage capacitance coefficient α of pure 

Pr 2 Ti 2 O 7 (�) and SiO 2 (�) MIM capacitors at 100 kHz. 

III. RESULTS 

Capacitance-voltage C(V) curves of pure SiO 2 MIM 

capacitors show negative parabolic behavior, caused by an 

anisotropic change in the index of refraction in response to 

an electric field, the so called quadratic optical Kerr effect 

[12]. MIM capacitors with Pr 2 Ti 2 O 7 as dielectric exhibit a 

positive quadratic C(V) curves. Excess carriers are 

injected from the electrodes into the dielectric layer by 

Schottky emission. The excess carrier concentration in the 

dielectric increases with rising electrical fields. The 

quadratic variation of capacitance is thus reduced with 

increasing thickness of the dielectric [13]. The determined 

quadratic voltage coefficients are summarized in Fig. 1. 

The quadratic voltage capacitance coefficients can be 

engineered by combining dielectric materials to a stacked 

MIM structure [10]. The SiO 2 layer affects the leakage 

current characteristics as well as the dielectric breakdown 

values. Due to the low k-value of SiO 2 , the resulting 

capacitance will be reduced. Therefore, this oxide layer 

thickness must be kept as thin as possible. 


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114 

C/C 0 

1.0005 

1.0000 

0.9995 

0.9990 

0.9985 

0.9980 

Reprints of 


-2 -1 0 1 2 

Fig. 2: Normalized C/C 0 (V) curves of stacked Pr 2 Ti 2 O 7 / SiO 2 

MIM capacitors, measured at 100 kHz. SiO 2 thickness is 8 nm. 

Capacitance Density (fF/µm 2 ) 

4.5 

4.0 

3.5 

8 nm SiO 2 

24 nm Pr 2 Ti 2 O 7 

18 nm Pr 2 Ti 2 O 7 

13 nm Pr 2 Ti 2 O 7 

Bias Voltage (V) 

8 nm SiO 2 

3.0 

12 14 16 18 20 22 24 

Pr 2 Ti 2 O 7 Thickness (nm) 

Fig. 3: Capacitance density (�) at 0 V and 100 kHz and α 

values (�) of Pr 2 Ti 2 O 7 / SiO 2 MIM capacitors. SiO 2 thickness is 

fixed to 8 nm. 

Fig. 2 illustrates the normalized C/C (V) curves of 

0 

stacked MIM capacitors with 8 nm SiO2 and various 

Pr Ti O layer thickness. Due to the impact of the SiO 2 2 7 2 

layer, the sign of α remains slightly negative. 

The capacitance densities at 0 V, measured at 100 kHz 

and the determined α values are illustrated in Fig. 3. The 

best achieved α value of this sequence with fixed SiO2 thickness is –100 ppm/V 2 at a capacitance density of 

3.2 fF/µm 2 

. By reducing the thickness of the Pr2Ti2O7 layer, the capacitance density of the stacked capacitors can 

be increased. Simultaneously, the quantity of α increases 

to unacceptable high values. 

-50 

-100 

-150 

-200 

-250 

-300 

α (ppm/V 2 ) 

Leakage Parameter @ 1V (fA/pFV) 


Fig. 4: Leakage parameter of Pr 2 Ti 2 O 7 / SiO 2 MIM capacitors 

at an applied voltage of 1V. 

Average Breakdown Voltage (V) 

10 

8 

6 

4 

2 

8 nm SiO 2 

0 

10 12 14 16 18 20 22 24 26 28 

30 

25 

20 

15 

10 

5 

0 

Pr 2 Ti 2 O 7 Thickness (nm) 

pure Pr 2 Ti 2 O 7 

8 nm SiO 2 + Pr 2 Ti 2 O 7 

8 nm SiO 2 

5 10 15 20 25 30 35 40 45 50 

PrTi x O y Thickness (nm) 

Fig. 5: Average breakdown voltages of pure Pr 2 Ti 2 O 7 MIM 

and stacked Pr 2 Ti 2 O 7 / SiO 2 MIM capacitors. 

Beside the quantity of the voltage coefficient α, which 

should be smaller than 100 ppm/V 2 

, the leakage 

parameter, is important to meet the current ITRS 

requirements. The leakage parameter is defined as 

quotient of leakage current and capacitance density at a 

certain applied voltage. The leakage parameters of the 

stacked MIM capacitors, determined at 1V, are shown in 

Fig. 4. Caused by the excellent leakage current of 2*10 -9 

A/cm 2 

at 1V, the leakage parameter values are lower than 

7 fA/pFV, as demanded by the ITRS. 

The dielectric breakdown voltages measured by I(V) 

characteristics, are shown in Fig. 5. The dielectric breakdown 

field of pure Pr Ti O was estimated by a linear fit. 

2 2 7

j (A/cm 2 ) 

Fig. 6: Breakdown characteristics of MIM capacitors with 

8 nm SiO 2 / 24 nm Pr 2 Ti 2 O 7 as a function of time at 25 °C. 

Time to Breakdown (s) 

10 -1 

10 -2 

10 -3 

10 -4 

10 9 

10 8 

10 7 

10 6 

10 5 

10 4 

10 3 

10 2 

10 1 

10 0 

stressed @ 13 V 

stressed @ 12 V 

stressed @ 11.5 V 

0 500 1000 1500 2000 

Stress Time (s) 

T = 25 °C 

24 nm Pr 2 Ti 2 O 7 

8 nm SiO 2 

10 years 

0 2 4 6 8 10 12 14 16 

Voltage (V) 

Fig. 7: Time to breakdown characteristics of a stacked MIM 

capacitor. 

The determined breakdown field is 6.5 MV/cm. 

Pr2Ti2O7 obeys the experimental "square root" rule for the 

breakdown field, EBD = 29.9 k -0.55 , which is compatible 

with the thermochemical model [14]. This model proposes 

that the defect generation in the dielectric, meaning a bond 

breaking mechanism, is a field-driven process. From 

Fig. 5, we extracted a dielectric breakdown strength of 

6.5 MV/cm, while the rule gives a breakdown field of 

7.0 MV/cm at the dielectric constant k of 13. Thin plasma 

SiO2 films exhibit an average dielectric breakdown 

strength higher than 10 MV/cm. The breakdown voltage 

of stacked SiO2/Pr2Ti2O7 MIM capacitors is affected by 

the higher dielectric strength of the individual layers. The 

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breakdown voltage of the stacked MIM capacitor with 

8 nm SiO2 and 24 nm Pr2Ti2O7 is dominated by the 

breakdown strength of the Pr2Ti2O7 layer. 

The reliability of the stacked MIM capacitor with 8 nm 

SiO2 and 24 nm Pr2Ti2O7 was studied by applying the 

Time Dependent Dielectric Breakdown (TDDB) test at 

room temperature. Three different monitored leakage 

currents during the TDDB test are shown in Fig. 6. The 

hard failure events are clearly visible. From the analysis of 

breakdown data, the mean time to failure is calculated. 

The extracted mean time to breakdown values of layered 

MIM capacitors are shown in Fig. 7. The extrapolated 

operating voltage for stacked MIM capacitors for 10 years 

lifetime is 3 V. 

IV. CONCLUSION 

The stacked SiO2 /Pr2Ti2O7 MIM capacitors show 

excellent electrical performances. The quadratic voltage 

coefficient of capacitance and leakage parameter fulfill the 

requirements of the current ITRS. The extrapolated 

operating voltage to 10 years lifetime is 3 V for MIM 

capacitors with a capacitance density of 3.2 fF/µm 2 

. 

Further work will be dedicated to achieve capacitance 

densities higher than 5 fF/µm 2 

. 

REFERENCES 

[1] S.B. Chen, C.H Lai, A. Chin, J. C. Hsieh, and J. Liu, “Highdensity 

MIM capacitors using Al O and AlTiO 2 3 x 

dielectrics”, IEEE Electron Device Lett., vol. 23, pp. 185- 

187, 2002. 

[2] M.Y. Yang, C.H. Huang, A. Chin, C. Zhu, M.F. Li, and D.- 

L. Kwong, “High-density MIM capacitors using AlTaOx Dielectrics”, IEEE Electron Device Lett., vol. 24, pp. 306- 

308, 2003. 

[3] H. Hu, C. Zhu, X. Yu, A. Chin, M.F. Li, B. J. Cho, D.-L. 

Kwong, P.D. Foo, M.B. Yu, X. Liu, and J. Winkler, “MIM 

capacitors using atomic-layer-deposited high-k (HfO ) 2 1x 

(Al2O3 ) dielectrics”, IEEE Electron Device Lett., vol. 24, 

x 

pp. 60-62, 2003. 

[4] X. Yu, C. Zhu, H. Hu, A. Chin, M.F. Li, B. J. Cho, D.-L. 

Kwong, P.D. Foo, and M. B. Yu, “A high-density MIM 

capacitor (13 fF/µm 2 ) using ALD HfO dielectrics”, IEEE 

2 

Electron Device Lett., vol. 24 , pp. 63-65, 2003. 

[5] S.-Y. Lee, H. Kim, P.C. McIntyre, K.C. Sarawat, and J.-S. 

Byun, “Atomic layer deposition of ZrO on W for metal- 

2 

insulator-metal capacitor application”, Appl. Phys. Lett., 

vol. 82, pp. 2874-2876, 2003. 

[6] C. Durand, C. Vallée, V. Loup, O. Salicio, C. Dubourdieu, 

S. Blonkowski, M. Bonvalot, P. Holliger, and O. Joubert, 

“Metal-insulator-metal capacitors using Y O dielectric 

2 3 

grown by pulsed-injection plasma enhanced metalorganic 

chemical vapor deposition”, J. Vac. Sc. Tech. A, vol. 22, pp. 

655-660, 2004. 


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116 

Reprints of 


[7] T. Ishikawa, D. Kodama, Y. Matsui, M. Hiratani, T. 

Furusawa, and D. Hisamoto, “High-capacitance 

Cu/Ta 2 O 5 /Cu MIM structure for SoC applications featuring 

a single-mask add-on process”, IEDM Tech. Dig, pp. 940- 

942, 2002. 

[8] Ch. Wenger, J. Dabrowski, P. Zaumseil, R. Sorge, P. 

Formanek, G. Lippert, and H.-J. Müssig, „First 

investigation of metal-insulator-metal (MIM) capacitor 

using Pr 2 O 3 dielectrics”, Mat. Sc. Sem. Pr., vol. 7, pp. 227- 

230, 2004. 

[9] Ch. Wenger, R. Sorge, T. Schroeder, A.U. Mane, G. 

Lippert, G. Lupina, J. Dabrowski, P. Zaumseil, and H.-J. 

Muessig, „MIM capacitors using amorphous high-k PrTi x O y 

dielectrics“, Micr. Eng., vol. 80, pp. 313-316, 2005. 

[10] S.J. Kim, B.J. Cho, M.-F. Li, S.-J. Ding, M.B. Yu, C. Zhu, 

A. Chin, and D.-L. Kwong, “Improvement of voltage 

linearity in high-k MIM capacitors using HfO 2 -SiO 2 stacked 

dielectric, IEEE Electron Device Lett., vol. 25, pp. 538-540, 

2004. 


[11] Y.-K. Jeong, S.-J. Won, D.-J. Kwon, M.-W. Song, W.-H. 

Kim, M.-H. Park, J.-H. Jeomg, H.-S. Oh, H.-K. Kang, and 

K.-P. Suh, “High quality high-k MIM capacitor by 

Ta 2 O 5 /HfO 2 /Ta 2 O 5 multi-layered dielectric and NH 3 plasma 

interface treatments for mixed-signal/RF applications”, 

VLSI Tech. Dig., pp. 222-223, (2004). 

[12] R. Adair, L.I. Chase, and S.A. Payne, “Nonlinear refractive 

index of optical crystals”, Phys. Rev. B, vol. 39, pp. 3337- 

3350, 1989. 

[13] S. Blonkowski, M. Regache and A. Halimaoui, 

“Investigation and modelling of the electrical properties of 

metal-oxide-metal structures formed from chemical vapour 

deposited Ta 2 O 5 films”, J. Appl. Phys., vol. 90, pp. 1501- 

1508, 2001. 

[14] J. McPherson, J.-Y. Kim, A. Shanware and H. Mogul, 

“Thermochemical description of dielectric breakdown in 

high dielectric constant materials”, Appl. Phys. Lett., 

vol. 82, pp. 2121-2123, 2003.

Nachdrucke 


On the epitaxy of twin-free cubic „111… praseodymium sesquioxide films 

on Si„111… 

T. Schroeder, a� P. Zaumseil, G. Weidner, Ch. Wenger, J. Dabrowski, and H.-J. Müssig 

IHP-Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany 

P. Storck 

SILTRONIC AG, PF 1140, 84479 Burghausen, Germany 

�Received 1 September 2005; accepted 13 October 2005; published online 3 January 2006� 

Twin-free epitaxial cubic �111� praseodymium sesquioxide films were prepared on Si�111� by 

hexagonal-to-cubic phase transition. Synchrotron radiation grazing incidence x-ray diffraction and 

transmission electron microscopy were applied to characterize the phase transition and the film 

structure. As-deposited films grow single crystalline in the �0001�-oriented hexagonal 

high-temperature phase of praseodymium sesquioxide. In situ x-ray diffraction studies deduce an 

activation energy of 2.2 eV for the hexagonal-to-cubic phase transition. Transmission electron 

microscopy shows that the phase transition is accompanied by an interface reaction at the oxide/ 

Si�111� boundary. The resulting cubic �111� low-temperature praseodymium sesquioxide film is 

single crystalline and exclusively shows B-type stacking. The 180° rotation of the cubic oxide lattice 

with respect to the Si substrate results from a stacking fault at the substrate/oxide boundary. © 2006 

American Institute of Physics. �DOI: 10.1063/1.2136788� 


Scaling plus successful integration of new materials will 

be the primary means of the semiconductor industry to pave 

the way from micro- to nanoelectronics. 1 Among the various 

materials classes discussed, the potential of engineered oxide 

systems to provide solutions to problems in microelectronics 

is generally acknowledged. 2 This is due to the tremendous 

diversity of solid-state phenomena encountered in complex 

oxides. 3 Of special interest are heteroepitaxial oxide films on 

Si, because lattice matched systems combine functionality 

with high structural stability and open the way towards 3D 

integration. 4 The successful integration of new functional epitaxial 

thin-film oxides in conventional silicon �Si� processing 

technology would thus enable one to implement new 

device concepts of superior performance. 5 Before this can 

occur, however, considerable progress in basic research for 

oxide electronics must be made to optimize the structural and 

electric quality of complex epitaxial oxide layers on Si. 6–9 

Our research on device-quality thin epitaxial high-k oxide 

layers on Si is focused on praseodymium sesquioxide 

�Pr 2O 3� films. 10 Epitaxial Pr 2O 3 films can be grown on 

Si�001� in the �101�-oriented cubic �cub� oxide phase �space 

group: Ia-3�, but the long-range order is limited by the presence 

of a 90° rotation domain structure in the film. 11,12 In 

contrast to the cub-Pr 2O 3�101�/Si�001� system, hexagonal 

�hex� Pr 2O 3 films �space group: P-3m1� of �0001� orientation 

form a �1�1� structure on clean Si�111� substrates, resulting 

in films of high quality. 13,14 An interesting alternative to the 

hex-Pr 2O 3�0001�/Si�111� system is the growth of cub- 

Pr 2O 3�111� films on Si�111�. Cub-Pr 2O 3�111� films are usually 

prepared when Pr 2O 3 is deposited on oxidized Si�111� 

wafers. However, due to the amorphous silicon dioxide 

a� Electronic mail: schroeder@ihp-microelectronics.com 

JOURNAL OF APPLIED PHYSICS 99, 014101 �2006� 

Reprints of 


�SiO 2� buffer layer, the cub-�111� Pr 2O 3 grains in these films 

lack azimuthal alignment and show a high density of stacking 

twins. In this work, we report the preparation of epitaxial 

twin-free cub-Pr 2O 3�111� films on Si�111� by inducing a 

hex→cub phase transition in the as-deposited oxide film. 

Furthermore, the stabilization mechanism responsible for the 

formation of the truly single-crystalline cub-Pr 2O 3�111� film 

structure on Si�111� is discussed. 

II. EXPERIMENT 

Boron-doped Si�111� substrates were cleaned by a standard 

procedure and an HF dip removed the native oxide 

layer immediately before the H-passivated wafers were 

loaded into the ultrahigh vacuum �UHV� chamber. 15 Epitaxial 

Pr 2O 3 overlayers, 50 nm thick, were grown by molecular 

beam epitaxy �MBE� at a flux of 0.1 nm/s, keeping the 

Si�111� substrate at a temperature of 625 °C during deposition. 

The phase transition was carried out by annealing the 

sample at 600 °C for 30 min in 10 −5 mbar of oxygen. To 

protect the oxide against humidity, approximately 20 nm 

thick Si films were deposited at a flux of 0.05 nm/s on top of 

the Pr 2O 3 layers. For x-ray diffraction studies, Si was deposited 

at room temperature to grow amorphous capping layers. 

For electron microscopy studies, a poly-Si cap was deposited 

at 650 °C to check for thermally induced interface reactions 

between Pr 2O 3 and the Si overlayer. 

A Philipps CM300 transmission electron microscope 

�TEM� was used to measure direct lattice cross-section images 

along the bulk Si�11 ¯ 0� directions, and record electron 

diffraction patterns in plan view mode along the Si �111� 

surface normal. These invasive and local measurements were 

supplemented by nondestructive x-ray diffraction studies 

which yield highly averaged, global informations about the 

sample structure. X-ray diffraction �XRD� studies in the 

0021-8979/2006/99�1�/014101/9/$23.00 99, 014101-1 

© 2006 American Institute of Physics 


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014101-2 Schroeder et al. J. Appl. Phys. 99, 014101 �2006� 

form of specular �-2� scans were performed on a diffractometer 

of the Bragg-Brentano type using a graphite monochromator 

in front of the detector to separate the Cu K � diffraction 

lines ��=0.154 nm� from the background. The 

synchrotron radiation-grazing incidence x-ray diffraction 

�SR-GIXRD� study was carried out with a Kappa-Six circle 

diffractometer available at the insertion device beamline ID 

32 of the European Synchrotron Radiation Facility �ESRF�. 

A beam energy of 11 keV �0.1127 nm� was used so that the 

critical angle � c for total reflection from the Si capping layer 

amounts to 0.16°. 16 Film and bulk sensitive GI-XRD studies 

were carried out by fixing the incident angle � of the beam 

on the sample surface to values only slightly above �0.2°� 

and well above �0.6°� the critical angle � c. The x-ray penetration 

depth in Pr 2O 3 and Si is limited for �=0.2° to about 

10 and 300 nm, respectively, thereby guaranteeing the study 

of the 50 nm Pr 2O 3 layer through the amorphous Si cap 

�20 nm� without any influence from the Si�111� substrate 

wafer. In contrast to this, the Si substrate signal is collected 

in the bulk sensitive mode at an incident angle of �=0.6° 

where an information depth on the micrometer scale results. 

Intensities of the x-ray studies are given in counts per second 

�CPS�. The Bragg reflections of the oxide and the Si substrate 

are always indexed with respect to the corresponding 

bulk lattices �bulk�. The scans of the GI-XRD study are however 

more conveniently carried out by using the hexagonal 

surface coordinate system of the Si�111� substrate �surf�. The 

procedure to determine the orientation matrix of the GI-XRD 

study and transform in reciprocal space from hexagonal 

Si�111� surface coordinates into cubic Si bulk indices is described 

in the literature. 17 Here, we only give for completeness 

the reciprocal space matrix to transform the measured 

Si�111� surface system coordinates of cubic Pr 2O 3 reflections 

into its bulk oxide Bragg peak indices: 

Si 

h �� k . �1� 

�surf l 

� h 

cub−Pr2O3 4 − 4 6 

k = 1/3 �� 4 8 6 

�bulk l − 8 − 4 6� 

This matrix takes into account that �a� the unit cell dimension 

of cubic Pr2O3 is about twice the value of the cubic 

Si lattice, and that �b� the oxide grows 180° rotated around 

the Si�111� surface normal, as will be proven in the following. 

III. RESULTS 

A. Epitaxial relationship 

The vertical stacking of the 50 nm Pr2O3 epilayer on the 

Si substrate was studied by specular �-2� XRD scans shown 

in Fig. 1. The Si substrate orientation results in the presence 

of sharp �111�, �222�, and �333� bulk reflections indicated by 

dashed lines on the top. The scan on the as-deposited Pr2O3 film is shown by the dotted line. It is characterized by the 

presence of �000n; n=2–6� reflections of the hex-Pr2O3 phase, which are labeled with solid lines. The specular 

�-2� scan of the annealed film is depicted by the solid line. 

Clearly, the hex-Pr2O3 reflections vanished and new diffraction 

signals are detected. These can be assigned to �222�, 


FIG. 1. Specular �-2� scans on 50 nm thick as-deposited �dotted line� and 

annealed �solid line� Pr 2O 3 films on Si�111�. 

�444�, and �666� Bragg peaks of the cub-Pr 2O 3 phase. It is 

therefore demonstrated that the complete 50 nm thick hex- 

Pr 2O 3 �0001� epilayer transforms into a cub-Pr 2O 3 �111� 

structure during the annealing procedure, a result in line with 

former studies on much thinner Pr 2O 3 films. 13 

In-plane measurements were applied to determine the 

azimuthal orientation of the oxide films on Si�111�. The inplane 

scans were measured at an incident angle �=0.6° to 

sample the whole Pr 2O 3 film plus the Si substrate. Two highsymmetry 

in-plane directions exist in the hexagonal Si�111� 

surface system, highlighted in the inset of Fig. 2 by gray 

panels. 

First, radial scans along the Si surf unit cell direction 

H surf =�100� are displayed on the left of Fig. 2 and correspond 

in Si bulk coordinates to scans along the �112 ¯ � bulk direction. 

Diffraction from the Si wafer results in sharp peaks at 

H surf =1, 2, and 3. As indicated on top, the peaks at H surf =1 

and 2 are crystal truncation rod �CTR� signals but the spike 

at H surf =3 is a bulk Si Bragg peak, namely the �224 ¯ � reflection. 

In the case of the as-deposited film, these sharp Si diffraction 

peaks at H surf =1, 2, and 3 are slightly asymmetric, 

broadened towards lower reciprocal space values by superimposed 

oxide reflections. The latter can be assigned to hex- 

Pr 2O 3 �101 ¯ 0�, �202 ¯ 0�, and �303 ¯ 0� Bragg peaks, respectively. 

This is in line with a previous publication of our group where 

it was shown that �a� hex-Pr 2O 3 films on Si�111� match the 

in-plane symmetry within 0.5% by aligning the hex-Pr 2O 3 

�101 ¯ 0� face normal direction along the Si H surf =�100� �Si 

�112 ¯ � bulk � azimuth and that �b� the oxide layers are fully relaxed 

for film thicknesses exceeding 12 nm. 14 After annealing, 

the intensity distribution of oxide reflections along the 

H surf direction changes dramatically. New oxide peaks appear 

at H surf =0.74, 1.48, 2.22, and 2.96, which can be assigned to 

cub-Pr 2O 3 �112�, �224�, �336�, and �448� reflections, respectively. 

The cub-Pr 2O 3 �448� reflection at H surf =2.96 is used 

to deduce two interesting insights. First, its position at H surf 

=2.96 indicates that the 50 nm thick cub-Pr 2O 3 film is not 

pseudomorphic. The calculated d spacing �0.1138 nm� cor-

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responds to the bulk value so that the cub-Pr 2O 3 layer is fully 

relaxed. Second, from the full width at half maximum 

�FWHM� of the cub-Pr 2O 3 �448� reflection, an average inplane 

domain size of the oxide layer of about 14 nm is deduced. 

The second set of high-symmetry in-plane scans is 

shown on the right-hand side of Fig. 2 and was measured 

along the Si surf �110� direction �Si bulk �011 ¯ � azimuth�. The 

as-deposited Pr 2O 3 film is characterized by the presence of 

hex-Pr 2O 3 �112 ¯ 0� and �224 ¯ 0� reflections, which closely coincide 

with the Si bulk �022 ¯ � and �044 ¯ � Bragg peaks at 

H surf =K surf =1 and 2, respectively. Film annealing does not 

produce any new peaks along the Si surf �110� direction. A 

closer inspection, however, reveals that the form of the diffraction 

signals changes. The diffracted intensity at H surf 

=K surf =1 becomes very broad and is interpreted as the overlapping 

signals of the Si bulk �022 ¯ � and the cub-Pr 2O 3 �044 ¯ � 

Bragg peaks. The latter occurs at H surf =K surf =0.98 and is a 

very intense cub-Pr 2O 3 Bragg diffraction. 18–20 In contrast to 

this, the observed diffraction signal at H surf =K surf =2 is much 

narrower due to the fact that the cub-Pr 2O 3 �088 ¯ � Bragg peak 

at H surf =K surf =1.96 is very weak, so only the Si �044 ¯ � Bragg 

peak is observed. 

To further corroborate the azimuthal alignment of the 

cub-Pr 2O 3 film on the Si�111� surface, a � scan was measured 

by fixing the in-plane momentum transfer to the reciprocal 

space value of the cub-Pr 2O 3 �112 ¯ � Bragg peak �H surf 

=0.74, marked by a dotted arrow in Fig. 2� and turning the 

sample over an angular range of about 250° around the sur- 

face normal of the sample. The location of the � scan �dotted 

circle� in the reciprocal in-plane space map of the Si�111� 

hexagonal surface system is depicted on the left of Fig. 3. 

The scan on the right detects the family of cub-Pr 2O 3 �112 ¯ � 

Bragg peaks, and the well-evolved 60° spacing demonstrates 

the hexagonal in-plane symmetry of the cub-Pr 2O 3 �111� 

plane. This symmetry illustrates the perfect in-plane alignment 

of the cub-Pr 2O 3 �111� film on Si�111� after the phase 

transition; in particular, no azimuthally misaligned crystal 

grains are detected. 

B. Stacking behavior 

FIG. 2. In-plane measurements on 50 nm thick asdeposited 

and annealed Pr 2O 3 films on Si�111� along 

the Si surf �100� �left panel� and the Si surf �110� direction 

�right panel�. Indexing of the diffraction peaks is given 

on the top. 

The stacking behavior of the cub-Pr 2O 3 film on Si�111� 

was studied by comparing the intensity distributions in the 

L surf −H surf �Fig. 4�a�� and the L surf −K surf �Fig. 4�b�� recipro- 

FIG. 3. Left: In-plane hexagonal Si�111� surface system showing the location 

of the � scan. Right: � scan �L=0.1� over family of �112 ¯ � reflections 

reveals hexagonal in-plane symmetry of cub-�111� Pr 2O 3 film. 


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FIG. 4. �10L� �a� and �01L� �b� rod scan measurement to determine the stacking behavior of �111�-oriented cub-Pr 2O 3 on Si�111�. 

cal lattice planes. The positions of these planes within the 

reciprocal hex-Si�111� surface system are shown on the left 

of Fig. 4. The intensity distribution on the �n0L; n 

=0, ±1, ±2� surf rods in the L surf −H surf and on the �0nL;n 

=0, ±1, ±2� surf rods in the L surf −K surf plane is sketched in 

the middle of Fig. 4�a� and Fig. 4�b�, respectively. The position 

of the Si substrate �filled circles� and cub-Pr 2O 3 �open 

circles� Bragg peaks was derived from experimental data. As 

an example, the �10L� surf �Fig. 4�a�� and �01L� surf �Fig. 4�b�� 

rods, drawn with gray background panels, are discussed below. 

GI-XRD studies of the �10L� surf �Fig. 4�a�� and the 

�01L� surf �Fig. 4�b�� rods were performed at two different 

incident angles, namely in the film sensitive ��=0.2°� and in 

the bulk sensitive ��=0.6°� mode. In the bulk sensitive 

scans ��=0.6°�, the measured Bragg peaks of the cub-Pr 2O 3 

film and the Si�111� substrate are indicated by dotted and 

solid arrows, respectively. The indexing of these diffraction 

signals with respect to the bulk lattices is given to the left of 

the scans. On the �10L� surf rod scan of Fig. 4�a�, we observe 

the Si �111 ¯ � bulk and the �220� bulk reflection at L=0.33 and 

1.33, respectively. On the �01L� surf rod scan of Fig. 4�b� only 

one allowed Si�111� substrate peak at L=1.66 is detected, 

namely the Si �131� bulk Bragg peak. The Si �020� bulk reflection 

at L=0.66 is forbidden. As the �10L� surf and the �01L� surf 

rod are situated on the H and K in-plane directions, respectively, 

they are related to each other by a 60° in-plane rotation. 

The different locations of the Si Bragg reflections on the 

�10L� surf �L=0.66+n; n=0,1,2, etc.� and the �01L� surf �L 

=0.33+n; n=0,1,2, etc.� rods demonstrate that, in contrast 

to the Si�111� in-plane symmetry, no sixfold symmetry exists 

for Si�111� off-plane Bragg peaks. Due to the ABC stacking 

sequences of Si�111� planes along the vertical Si �111� bulk 

direction of the fcc-like cubic Si crystal �space group: 

Fd-3m�, the latter direction is only a threefold rotation axis. 21 

In the film sensitive measurement ��=0.2°� of the �10L� surf 

and �01L� surf rods, all the Si Bragg peaks are absent and only 

the cub-Pr 2O 3 Bragg peaks are present. The much weaker 

intensity of the oxide reflections in the surface sensitive scan 

�10 3 CPS� than in the bulk sensitive study �10 4 CPS� dem- 


onstrates that the information depth of the 0.2° measurement 

is smaller than the actual cub-Pr 2O 3 layer thickness. Note 

that the distribution of the cubic oxide Bragg peaks on the 

�10L� surf and �01L� surf rods follows the same scheme as found 

for the Si reflections but in a reversed way: The oxide peaks 

on the �10L� surf and �01L� surf rod appear close to the positions 

of the Si Bragg peaks on the �01L� surf and �10L� surf rod, respectively. 

For example, the cub-Pr 2O 3 Bragg peaks on the 

�01L� surf rod are found at L=0.3 and L=1.3, very close to the 

positions of the Si �111 ¯ � bulk �L=0.33� and �220� bulk �L 

=1.33� Bragg peaks on the �10L� rod. According to the derived 

d spacings, these cub-Pr 2O 3 Bragg peaks can be identified 

as �222 ¯ � bulk �L=0.3� and �440� bulk �L=1.3� reflections. 

Cub-Pr 2O 3 crystallizes in the space group Ia-3 with the 

body diagonal of the structure being a threefold rotation axis. 

This threefold off-plane symmetry of the �111�-oriented cub- 

Pr 2O 3 film on Si�111� is demonstrated by performing a � 

scan over the position of the oxide �440� bulk reflection on the 

�01L� surf rod at L=1.3. Figure 5 depicts the �-scan measurement 

on the left, and the result is plotted on the right. The 

threefold off-plane symmetry of the cub-�111� Pr 2O 3 film is 

evident from the observed 120° spacing between the oxide 

reflections belonging to the family of �440� bulk Bragg peaks. 

C. Interface reaction 

TEM electron diffraction and cross-section measurements 

were performed to corroborate the results of the x-ray 

FIG. 5. Left: Off-plane �-scan sketch in the Si�111� surface system. Right: 

Off-plane � scan �L=1.3� on family of �440� reflections to demonstrate type 

B orientation of the �111�-oriented cub-Pr 2O 3 epilayer on Si�111�.

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FIG. 6. TEM study of the hex-Pr 2O 3�0001�/Si�111� �left column� and cub- 

Pr 2O 3�111�/Si�111� �right column� systems: electron diffraction patterns �a� 

and �b�; overview direct lattice cross section images �c� and �d�; highresolution 

direct lattice cross section images �e� and �f�. Arrows indicate 

surface normals of �111 ¯ � planes. 

diffraction studies and gain insight into the role of the 

oxide/Si interface structure on the phase transition, respectively. 

Figures 6�a� and 6�b� show electron diffraction patterns 

of plan view samples mounted with the Si�111� substrate 

direction parallel to the incident electron beam. In the case of 

the hex-Pr 2O 3�0001�/Si�111� �Fig. 6�a��, the hexagonal electron 

diffraction pattern can be understood as a �1�1� overstructure 

created by the projection of the spots from the 0001 

pole of the hex-Pr 2O 3 layer on those of the 111 pole of the Si 

substrate. After the phase transition �Fig. 6�b��, the superposition 

of the 111 pole of the cub-Pr 2O 3 layer �weak spots� 

with the 111 pole of the Si substrate �bright spots� results in 

a �4�4� overstructure. This �4�4� structure is due to the 

four times bigger surface unit cell of the cub-Pr 2O 3�111� 

plane with respect to the Si�111� substrate, a consequence of 

the reduced symmetry of the cub-Pr 2O 3�111� surface lattice 

�P3� with respect to the cub-Pr 2O 3 bulk structure �Ia-3�. 14 In 

that way, it can be concluded that both patterns are in line 

with the epitaxial relationships between oxide and Si lattices 

determined above in the XRD studies. 

Figures 6�c� and 6�d� show overview TEM cross-section 

pictures of the as-deposited hex-Pr 2O 3�0001�/Si�111� and 

the annealed cub-Pr 2O 3�111�/Si�111� systems, respectively. 

In both images, the materials stack on the Si�111� substrate 

�Si� is composed of an approximately 50 nm thick Pr 2O 3 film 

and a 20 nm thick Si capping layer. The hex- 

Pr 2O 3�0001�/Si�111� system in Fig. 6�c� is one of the rare 

examples where an atomically sharp high-k oxide/Si interface 

without a SiO 2 interface layer can be realized. 22 In contrast 

to this, the TEM image of the cub-Pr 2O 3/Si�111� system 

clearly shows the presence of an interface layer �bright 

contrast� at the Si substrate/oxide boundary after the annealing 

procedure. It is interesting to note that no such interface 

layer is observed at the Pr 2O 3/Si capping layer boundary, 

although the Si cap was deposited at higher temperatures 

than the oxide on the Si substrate. This shows that the interface 

layer is not the result of a thermally induced reaction 

between Pr 2O 3 and Si but grows during the annealing procedure 

in the oxygen ambient. 

To study the oxide/Si substrate interface in more detail, 

high-resolution images of the hex-Pr 2O 3�0001�/Si�111� and 

the cub-Pr 2O 3�111�/Si�111� systems have been obtained 

�Figs. 6�e� and 6�f�, respectively�. The view direction in both 

cases is along the Si�111� �011 ¯ � in-plane direction, a projection 

sensitive to the stacking sequence of the Si�111� planes 

along the Si�111� surface normal. This can be inferred from 

the Si substrate regions of the images, where the vertically 

stacked Si�111� lattice planes are seen to be in-plane displaced 

with respect to each other, resulting in the wellknown 

fcc ABC stacking sequence along the Si�111� surface 

normal. The orientation of the observed lattice fringes in the 

Si substrate is indicated by dotted arrow structures. The surface 

normal is inclined by 70° with respect to the Si�111� 

surface normal so that these lattice fringes can be assigned to 

Si�111 ¯ � planes. In the case of the hex-Pr 2O 3�0001�/Si�111� 

system �Fig. 6�e��, an atomically smooth epitaxial interface 

with no indication of an interface reaction is visible. In the 

cub-Pr 2O 3�111�/Si�111� system �Fig. 6�f��, the highresolution 

image shows the presence of an amorphous interface 

layer �IF� with a bilayer structure. The latter is composed 

of a white and grayish region, each of about 1.5 nm 

thickness. Based on depth profiling sputter-XPS studies �not 

shown�, the chemical origin of the white and grayish layer at 

the interface can be assigned to a SiO 2-rich and a SiO 2-poor 

Pr-silicate structure, respectively. The epitaxial cub- 

Pr 2O 3�111� film is visible in the upper part of Fig. 6�f�, and 

close inspection shows that the fcc-like stacking of oxide 

�111� planes does not follow the ABC sequence of the Si 

substrate. The in-plane displacement of adjacent oxide �111� 

planes is opposite in direction with respect to the Si substrate, 

so that the cub-Pr 2O 3�111� film structure stacking sequence 

is accordingly denoted CBA. In consequence, the orientation 

of the lattice fringes of �111 ¯ � planes in the oxide 

�white arrow structure� is different from the Si substrate. 

However, a relationship exists and it is obvious from the 

figure that the surface normals of �111 ¯ � planes in the oxide 

and the Si substrate can be superimposed by rotating one of 

the lattices around the Si�111� surface normal by 180°. 


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D. Phase transition 

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FIG. 7. In situ hex→cub Pr 2O 3 phase transition study on Si�111� by specular 

�-2� XRD measurements. 

Specular �-2� scans on the Bragg-Brentano diffractometer 

��=0.154 nm� over the angular 2� range from 56° to 

63° were applied to study in situ the hex→cub Pr 2O 3 phase 

transition on Si�111�. These scans were recorded for 4 min 

each, while the sample was kept in 10 −5 mbar oxygen at a 

constant elevated temperature. To control the velocity v of 

the phase transition, different temperature �T� runs in the 

range from 450 to 550 °C were applied. Figure 7 shows as 

an example the measurement at 464 °C and summarizes the 

results by plotting only the scans after time intervals of 

12 min. The double-peak structure of the Si�222� substrate 

peak �2�=58.85°� originates from the � 1 and � 2 components 

of the Cu K � radiation, which are not separated by the 

graphite monochromator. The as-deposited Pr 2O 3 film �t 

=0 min� exhibits only the hex-Pr 2O 3�0004� reflection at 2� 

=60.91°. It is clearly seen that the intensity decrease of this 

peak during the annealing procedure �t=12, 24, 36, and 

48 min� is accompanied by the formation of the cub- 

Pr 2O 3�444� Bragg peak at 2�=56.97°. At the end of the annealing 

procedure �t=48 min�, the Pr 2O 3 film is completely 

transformed into the cub-Pr 2O 3 phase. A simple data analysis 

�not shown� was applied to extract the activation energy E 0 

of the thermally induced phase transition. By plotting the 

integrated oxide Bragg peak intensity against time, the phase 

transition velocities v of the measurements at different temperatures 

T were determined. These phase transition velocities 

v were found to closely follow a linear relationship in an 

Arrhenius plot � log v against 1/kT� so that the activation 

energy E 0 of 2.2 eV could be easily extracted from its slope. 


IV. DISCUSSION 

A. Epitaxial relationship 

The specular �-2� XRD scans of Fig. 1 determine the 

phase and the vertical stacking direction of the Pr2O3 films 

on Si�111�. The as-deposited film grows in the hex-Pr2O3 phase �a=b=0.386 nm; c=0.601 nm� on Si�111� and is attached 

with its �0001� basal plane to the substrate. After the 

annealing treatment, the Pr2O3 epilayer is crystallized in the 

�111�-oriented cubic phase whose unit cell �b=1.115 nm� is 

a little bit more than two times bigger than the cubic Si cell 

�a=0.543 nm�. Accordingly, cubic oxide reflections are always 

observed at Sisurf coordinate values that are slightly 

smaller than the closely situated Si bulk Bragg peaks, and the 

oxide indices are twice the values of these Si diffraction 

signals. 

The in-plane GI-XRD measurements of Figs. 2 and 3 

define the azimuthal orientation of the Pr2O3/Si�111� systems 

in real space. In the case of the as-deposited Pr2O3 film, 

the in-plane �101 ¯0� direction of the hex-Pr2O3 lattice is 

aligned along the Sisurf�100� �Sibulk�011 ¯�� azimuth, so that an 

almost perfect lattice matching results. The surface unit cell 

of the oxide surface is bigger than the Si�111� in-plane 

dimensions by only 0.5%. 14 In the case of the annealed 

Pr2O3 epilayer, the azimuthal orientation is determined by 

the cub-Pr2O3�01 ¯1� direction pointing along the Sisurf�100� �Sibulk�011 ¯�� vector, resulting in an in-plane lattice misfit of 

about 2.6%. The antiparallel alignment between the cub oxide 

and the Si in-plane vectors given here corresponds to a 

180° rotation around the Si�111� surface normal of the cub 

oxide coordinate system with respect to the bulk Si lattice. 

Note that the in-plane measurements of Figs. 2 and 3 cannot 

discriminate between parallel and antiparallel alignment. It is 

only by the stacking sensitive off-plane GI-XRD measurements 

of Figs. 4 and 5 that the antiparallel alignment of the 

cub-Pr2O3�111� film lattice on the Si�111� substrate is determined. 

This can be best understood with the help of the 

reciprocal Lsurf−H surf and Lsurf−K surf lattice planes sketched 

in Fig. 4�a� and Fig. 4�b�, respectively. A relationship exists 

between the distribution of the oxide �open circles� and the 

Si�111� substrate Bragg peaks �filled circles�, namely the oxide 

reflections can be created from the Si Bragg peaks by 

carrying out a reflection across the plane spanned by the 

�00L�surf��00L�surf� and the �12 ¯0�surf��2 ¯10�surf� vectors in Fig. 

4�a� �Fig. 4�b��. Certainly, such a reflection operation is identical 

with a 180° rotation around the �00L�surf�Si�111�bulk� direction of the oxide coordinate system with respect to the 

Si�111� bulk lattice. It can therefore be concluded on the 

basis of the measured intensity distribution of oxide and Si 

reflections on the �10L�surf �Fig. 4�a�� and the �01L�surf �Fig. 

4�b�� rods that the cub-Pr2O3�111� film lattice is rotated by 

180° around the Si�111� surface normal with respect to the 

Si�111� substrate coordinate system. Following the convention 

in the literature on the epitaxy of cubic �111� film structures 

grown on single-crystal �111� surfaces of cubic substrates, 

this relationship is called a type B-oriented film 

structure. 23 Type A twins are created when epilayer crystal 

grains adopt the crystal lattice orientation of the substrate. In

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FIG. 8. Structure model of the type B-oriented cub-Pr 2O 3�111� epilayer on 

Si�111�. 

consequence, the intensity distribution of type A domain reflections 

and Si substrate Bragg peaks follows the same 

scheme. From the fact that no oxide reflections are observed 

in the film sensitive �10L� surf �Fig. 4�a�� and �01L� surf �Fig. 

4�b�� rod measurements at the positions of the Si substrate 

Bragg peaks, the absence of type A cub-Pr 2O 3�111� crystal 

grains is proven. Furthermore, the twin-free character of the 

type B-oriented cub-Pr 2O 3�111� epilayer is evident from the 

threefold symmetry �120° spacing� observed in the � scan of 

Fig. 5. The simultaneous presence of type A and type B 

epilayer grains would result in diffraction signals with 60° 

spacing due to the superposition of the intensity distributions 

of the two domains �each domain has threefold symmetry, 

but type A and B are rotated with respect to each other by 

180°�. 24 

The TEM electron diffraction and cross-section studies 

in Fig. 6 fully support the epitaxial relationships detected by 

XRD for the hex-Pr 2O 3�0001�/Si�111� and the cub- 

Pr 2O 3�111�/Si�111� system. In particular, the TEM crosssection 

image 6�f� demonstrates that a change of the stacking 

sequence of the cub-Pr 2O 3�111� planes �CBA� with respect 

to the Si�111� planes �ABC� is the microscopic origin 

of the observed type B epitaxy. This is a well-known result 

from defect characterization studies of �111�-oriented fcc epilayer 

structures on �111� fcc crystal surfaces, so that type 

A/type B domains are also called stacking twins. 25 

Figure 8 summarizes the epitaxial relationships derived 

for the cub-Pr 2O 3�111�/Si�111� system. The side view is 

shown along a stacking sensitive Si bulk �01 ¯ 1� direction so that 

the change of the stacking sequence of the oxide �111� planes 

in the type B-oriented epilayer structure is clearly visible. 

B. Type B epitaxy 

Various examples of the heteroepitaxial growth of �111�oriented 

cubic epilayer structures on Si�111� substrates have 

been reported in the literature, ranging from conductors �e.g., 

CoSi 2 �Ref. 26�� over semiconductors �e.g., Ge �Ref. 27�� to 

insulators �e.g., CaF 2 �Ref. 28��. The mechanisms responsible 

for the coexistence of type A and type B domains or the 

preferential growth of one of the two orientations are at 

present not clear. For example, the growth of singlecrystalline 

type B-oriented CoSi 2 films was achieved on 

clean Si�111� surfaces, and electronic aspects of the metal 

disilicide-silicon interface were invoked to account for this 

result. 29 First studies on the growth of CaF 2�111� films on 

Si�111� substrates resulted in the undesired presence of type 

A and type B stacking twins in the epilayer structure. 28 In 

later studies, the stacking conflicts could be avoided by 

growing the fcc-like CaF 2 films in the form of a twin-free 

epilayer structure—either A- or B-type oriented—on the 

Si�111� substrate. 30 It turned out that the structure and the 

stoichiometry of the initially formed insulator/Si interface 

were crucial to achieve this result. 28,31 A further interesting 

example is the growth of homoepitaxial Si films on Si�111�. 

Films grown on the Si�111�-�7�7� reconstructed surface are 

crystallographically aligned with the substrate and have the 

untwinned A-type orientation. 32,33 However, boron �3��3 

reconstructed Si�111� surfaces were found to act as appropriate 

templates for the nucleation of B-type oriented Si films, 

and a stabilization mechanism based on chemical effects was 

proposed. 34 Silicon prefers the cubic �diamond or zinc 

blende� stacking sequence over the hexagonal �wurtzite� 

stacking sequence because the bonding is covalent with no 

ionic component. Wurtzite stacking brings third-nearest 

neighbors closer than zinc-blende stacking, so that ionic 

II-VI compounds like CdS and ZnO prefer this structure. As 

the twin boundary formed during overlayer growth at the 

interface can be described as a local wurtzite structure, the 

stabilization of the type B-oriented Si epilayer structure was 

attributed to the ionic bonding contributions induced by boron 

on the reconstructed Si�111� surface. 

The ionic character of Pr 2O 3 makes it very probable that 

this mechanism is also of importance in the stabilization of 

the type B cub-Pr 2O 3 epilayer structure on Si�111�. However, 

it is not possible at present to construct an appropriate interface 

model of the crystalline type B cub-Pr 2O 3/Si�111� 

structure. The reason is that the hex→cub Pr 2O 3 phase transition 

was found to be correlated with the formation of an 

interface layer at the oxide/Si substrate boundary which appears 

amorphous in the reported TEM images �Figs. 6�d� and 

6�f��. Indeed, all experimental findings indicate that the 

growth of cub-Pr 2O 3 on Si�111� only happens when such an 

amorphous interface layer is present. Sakai et al. reported 

recently the preparation of cub-Pr 2O 3 layers with type A/type 

B twinning on Si�111�. 35 TEM images of the Pr 2O 3/Si�111� 

stacks clearly indicated the presence of an amorphous interface 

layer. The same results were obtained by our group 


Nachdrucke 


124 

Reprints of 



when Pr 2O 3 films were deposited on preoxidized Si�111� wafers. 

Interestingly, we found furthermore that UHV annealing 

of as-deposited hex-Pr 2O 3�0001�/Si�111� samples at 600 °C 

neither resulted in an interfacial layer at the substrate/oxide 

boundary nor did the phase transition occur. 

These results can be explained by the fact that the epitaxial 

interface energy stabilizes the growth of hex- 

Pr 2O 3�0001� on Si�111�. The Pr-O phase diagram shows that 

the cub and hex modifications are the low- ��700 °C� and 

high-temperature ��700 °C� phases of Pr 2O 3, respectively. 20 

The lattice misfit between Si�111� and hex-Pr 2O 3�0001� is 

0.5%, but 2.6% in the case of �111�-oriented cub-Pr 2O 3. 14 It 

is the lower epitaxial strain energy of the �0001� crystal face 

of the high-temperature hex-Pr 2O 3 phase which stabilizes its 

growth on clean Si�111� surfaces. The low-temperature cub- 

Pr 2O 3 phase is only produced when the oxide film is disconnected 

from the crystalline Si�111� substrate by an amorphous 

interface layer. This interface layer can be prepared in 

two ways which result in very different cub-Pr 2O 3�111� film 

morphologies. 

First, the wafer can be preoxidized prior to oxide deposition. 

Deposited �111�-oriented cub-Pr 2O 3 films on 

SiO 2-covered Si�111� wafers do not show a defined in-plane 

alignment, and the density of A- and B-type stacking twins is 

high. The prefered �111� orientation demonstrates the low 

surface energy of this crystal face of the fluorite related cub- 

Pr 2O 3 film structure, a result in line with comparative studies 

on CaF 2 �fluorite structure�. 28 

Second, the interface layer can be prepared by postdeposition 

annealing of hex-Pr 2O 3�0001� films on Si�111� in an 

oxygen atmosphere. Here, the formation of the interface 

layer is the result of the oxidation of the oxide/Si boundary 

due to the very high mobility of oxygen in PrO x 

compounds. 36–38 The hex�0001�→cub�111� Pr 2O 3 phase 

transition on Si�111� is observed, which results in twin-free 

epitaxial cub-Pr 2O 3�111� films of high quality. Note that we 

discussed the transformation of a hex-Pr 2O 3�0001� plane into 

a cub-Pr 2O 3�111� crystal face on the atomic scale in a previous 

publication. 14 It was found that the Pr sublattice of the 

two crystal faces is almost identical, and only diffusion of 

oxygen atoms is required to convert one plane into the other. 

In contrast to the structure of the individual planes, the hex 

→cub Pr 2O 3 phase transition is characterized by a rearrangement 

of the Pr sublattice, namely the AB stacking sequence 

of �0001� planes in hex-Pr 2O 3 must become an ABC stacking 

of �111� planes in cub-Pr 2O 3. In other words, the two lattices 

differ in particular in the positions of the second-nearest 

neighbors. The �0001� direction of the hex lattice becomes a 

cubic �111� direction, and one of the close-packed �101 ¯ 0� 

rows coincides with a cubic �011 ¯ � direction. This can be 

accomplished in two ways leading to ABC and CBA stacking 

twins arrangements due to the various starting points of the 

nuclei of the phase transformation. 39,40 There is a priori no 

reason for preferring one twin; both should be created in the 

process of the hex→cub phase transition. The observation of 

a single-crystalline type B-oriented cub�111� Pr 2O 3 film 

therefore indicates that the phase transition does not start in 

the bulk but nucleates at the oxide/Si interface. The follow- 


ing mechanism of the hex→cub Pr 2O 3 phase transformation 

on Si�111� can therefore be proposed. 

The epitaxial interface energy stabilizes the hex- 

Pr 2O 3�0001� structure on Si�111�. During annealing in an 

oxidizing ambient, the high oxygen diffusion in Pr 2O 3 results 

in the oxidation of the Pr 2O 3/Si boundary. In the beginning 

of this interface oxidation process, the oxygen uptake in 

Si�111� results in an ionic bonding contribution in the substrate. 

This changes the character of the Pr 2O 3/Si�111� interface 

from an initially ionic/covalent boundary into a more 

ionic/ionic heterostructure which favors the nucleation of a 

type B-oriented epilayer �local wurtzite structure�. With 

progress of the oxidation process, the epitaxial interface stabilization 

energy of the hex-Pr 2O 3�0001� phase is continuously 

lifted and the transforming oxide layer forms the type 

B cub-Pr 2O 3�111� orientation by passing the stacking information 

from the interface through the whole film structure. 

It is noted for completeness that the strong influence of 

the oxide/Si interface on the phase transition makes it difficult 

to assign a microscopic origin to the measured activation 

energy E 0 of 2.2 eV of the hex→cub Pr 2O 3 phase transition 

�Fig. 7�. A possible origin is based on the reported activation 

energies for ion diffusion in rare-earth oxide lattices, typically 

in the range of 0.8 to 1 eV for oxygen and several electron 

volts for cations. 9,41 The magnitude of the measured 

activation energy could therefore in principle indicate that 

the mobility of the Pr sublattice is the rate limiting step in the 

phase transition. 

V. CONCLUSION 

A preparation recipe for single-crystalline, type 

B-oriented cub-Pr 2O 3�111� films on Si�111� was developed 

which is based on inducing a hex-Pr 2O 3�0001�→cub- 

Pr 2O 3�111� phase transition in the as-deposited oxide film. 

The epitaxial relationships of the hex-Pr 2O 3�0001� and the 

cub-Pr 2O 3�111� layers on Si�111� were unequivocally determined 

by XRD and SR-GIXRD studies. TEM studies revealed 

that the hex-Pr 2O 3�0001�→cub-Pr 2O 3�111� phase 

transition crucially depends on the oxide/Si interface structure. 

As the interface structure plays an important role in the 

stabilization of the type B cub-Pr 2O 3�111� epilayer structure 

on Si�111�, in situ GIXRD phase transition studies will be 

applied in the future to clarify the fundamental mechanism at 

work. Besides potential applications in Si-based nanoelectronics, 

the Pr 2O 3/Si�111� system will become a suitable 

model system for condensed matter physicists interested in 

understanding the physics of phase transitions of epitaxial 

oxide layers on Si. 

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Nachdrucke 


126 

Abstract 

Reprints of 


Dislocation Engineering for a Silicon-Based Light Emitter at 1.5 µm 

M. Kittler 1,2 , M. Reiche 3 , T. Arguirov 2 , W. Seifert 1,2 and X. Yu 1,2 

A new concept for a Si light emitting diode (LED) capable of 

emitting at 1.5 µm efficiently is proposed. It utilizes radiation 

from a well-defined dislocation network created in a 

reproducible manner by Si wafer direct bonding. The 

wavelength of the light emitted from the network can be 

tailored by adjusting the misorientation between the Si 

wafers. 

Introduction 

Currently used interconnects based on Cu wiring will cause 

serious problems in the future such as heat penalty, nonacceptable 

delay and complexity, crosstalk etc. On-chip 

optical interconnects are able to overcome these problems 

and will be essential for future integrated circuits. Several 

CMOS-technology compatible key components have already 

been demonstrated, as for example a fast Si based electrooptical 

modulator (1), allowing the use of continuous-wave 

light sources. However, a silicon based light emitter, which is 

compatible with CMOS technology, is still lacking. The 

recently demonstrated first Si-based Raman laser cannot be 

used for this purpose because it is optically pumped (2). 

Different approaches for light emitters have been studied (3). 

Recently, light-emitting diodes (LED) made either by boron 

(4-8) or by phosphorus (8) implantation into Si attract special 

interest, allowing efficient room temperature (RT) electroluminescence 

(EL) of the Si band-to-band (BB) line at 1.1 

µm. However, the desired light emitter, besides exhibiting 

high luminescence efficiency at RT, should also be spatially 

confined and should emit at about 1.5 µm. The D1 emission 

close to 1.5 µm, related to dislocations in Si, is a suitable 

candidate for the light emitter (9), but application of 

dislocations as active device components requires their 

reproducible formation. The present paper demonstrates that 

Si wafer bonding allows the reproducible formation of 

dislocation networks that exhibit a dominating light emission 

at the desired wavelength of about 1.5 µm. 

Critical analysis of Si LED made by ion implantation 

Light sources made by ion implantation are reported for 

example in (4-8). The achievement of intense BB radiation at 

RT after boron implantation and annealing has been 

attributed to the formation of dislocation loops which 

1 IHP microelectronics, Im Technologiepark 25 


2 IHP/BTU Joint Lab, Konrad-Wachsmann-Allee 1, 03046 Cottbus, Germany 

3 MPI für Mikrostrukturphysik, Weinberg 2, 06120 Halle, Germany 


introduce a local strain field modifying the Si band structure 

locally, thus preventing non-radiative recombination (4). 

Furthermore, it was stated that engineering of {113} defects 

formed during the post anneal of the boron implant are the 

reason for an even stronger BB emission (7). Despite the 

observation of strong BB radiation in conjunction with 

defects/dislocations its straight ascription to defects, as stated 

in (4,7), is misleading. 

Luminescence intensity [a.u.] 

1000 

900 

800 

700 

600 

500 

400 

300 

200 

100 

0 

0-7803-9269-8/05/$20.00 (c) 2005 IEEE 

D1 

80 K B B 

300 K 

0.8 0.9 1.0 1.1 1.2 1.3 

Photon energy [eV] 

Fig. 1 

Defect and band-to-band emission in a Si diode made by ion implantation: 

Photoluminescence spectra at 80 and 300 K, exhibiting BB and D1 line at 

1.1 µm and 1.5 µm, respectively. 

implanted BB 

region emission 

Fig. 2 

Example of crystal defects after ion implantation and post anneal: Crosssectional 

TEM micrograph (dark field) of a sample after P implantation (750 

keV, 2x10 14 cm -2 ) and furnace anneal (1000 °C, 30 min). The region where 

the BB line mainly arises is also indicated. 

As seen from Figs. 1 and 2, the crystal defects do not emit the 

BB line but give rise to an additional radiation, namely the 

D1 line. Moreover, BB emission arises mainly from the 

defect-free region. Fig. 3 shows that the EL efficiency of the

BB line in the LED increases with temperature T (anomalous 

behavior). For comparison, the ordinary temperature behavior 

of luminescence in as-grown Si is shown in the insert. 

Our model suggests different explanation of the results (8). It 

takes into account the three recombination components in Si, 

namely Shockley-Read-Hall (SRH) recombination via deep 

levels in the band-gap, Auger recombination with the energy 

given to a third carrier and the radiative BB recombination 

(10). 

Fig. 3 

Efficiency of electro-luminescence: Anomalous T behavior of the BB line 

(1.1 µm) of EL observed at 1.2 V forward bias in a diode made by P 

implantation into p-Si (10 Ωcm); implantation at 500 keV, 4x10 14 cm -2 

followed by furnace anneal (1000°C, 30 min). The insert represents the 

ordinary T behavior of luminescence in as-grown Si. 

300 K 

Fig. 4 

Internal quantum efficiency vs. excess carrier concentration calculated with 

SRH lifetime as parameter. Experimental data points for diodes implanted 

with P at energies of 135 and 500 keV, respectively, are shown together with 

data for B implantation from Ng et al. (4). 

The recombination rates R of these mechanisms depend on 

the excess carrier concentration ∆n. For the SRH 

recombination the rate is given by RSRH = ∆n . 1/τSRH, where 

τSRH denotes the SRH lifetime. The dependence of the 

radiative recombination rate and the Auger recombination 

rate on ∆n are given by RBB ~ ∆n 2 . B or RAuger ~ ∆n 3 . C, 

respectively. Here, B denotes the radiative recombination 

coefficient (for BB recombination) and C is the Auger 

recombination coefficient. The internal quantum efficiency is 

defined by the ratio of the radiative recombination rate RBB 

and the overall recombination rate, i.e. ηi = RBB / (RSRH + RBB 

+ RAuger). Fig. 4 depicts the calculated internal quantum 

efficiency ηi as a function of the excess charge carrier density 

Nachdrucke 


Reprints of 


∆n, e.g. the carriers formed close to a forward biased p-n 

junction. The calculation was done for 300 K by using for the 

coefficients B = 10 -14 cm 3 s -1 (11) and C = 10 -31 cm 6 s -1 (12), 

with the SRH lifetime τSRH as parameter. Note that 1/τSRH is 

proportional to the concentration NT of traps/impurities 

characterizing the quality of the bulk material. Also the 

coefficients B and C reflect bulk properties. Hence, the model 

postulates that the intensive EL of the BB line escapes from 

the Si bulk (below the p-n junction) and is not formed 

at/around crystal defects as stated in (4,7). The efficiency for 

light emission is largely governed by the SRH lifetime. The 

implantation-related crystal defects may improve τSRH in the 

bulk due to their gettering action, i.e. they support reaching a 

strong BB emission in an indirect way. In nearly perfect Si 

bulk material with τSRH = 10 -3 s the maximum of the quantum 

efficiency ηi is expected to reach about 30% at 300 K. This 

value is in agreement with Trupke et al. who concluded from 

their experimental data that the internal quantum efficiency 

of Si at 300 K might exceed 20% (13). 

Fig. 4 demonstrates the agreement of our experimental data 

(circles) with the model. The efficiency values η have been 

measured and the corresponding values of the excess carrier 

density ∆n have been calculated with the process and device 

simulator ‘ISE TCAD’ for the process conditions applied to 

fabricate the diodes and for the applied forward bias of 1.2 V. 

There is also a good correspondence of the model with 

experimental data published by Ng. et al. in (4). The lifetime 

τSRH = 10 µs deduced by the model for the sample used in (4) 

(black square) is in a fairly good agreement with the 

measured lifetime of τSRH = 18 µs reported in (4). The model 

allows explaining the anomalous T-behavior of the BB line as 

well, which is another argument for its validity (8). 

Summarizing, this “bulk model” claims that the BB radiation 

is not spatially confined at/around the implantation related 

defects. It predicts that the BB light is generated in the 

interior of the Si bulk below the p-n junction. This was 

verified experimentally as well (14). Both, missing 

confinement of the BB radiation and a wavelength of about 

1.1 µm are strong arguments against the applicability of a Si 

LED made by ion implantation as on-chip light emitter. In 

contrast, a light emitter based on dislocation-related 

luminescence exhibits a promising candidate for this task. 


D1 

D2 

D3 

D4 

0.7 0.8 0.9 1.0 1.1 1.2 1.3 

Energy [eV] 

Fig. 5 

D-band luminescence: A typical luminescence spectrum of dislocated Si, 

exhibiting the D1-D4 lines formed by the dislocations and BB radiation. 


BB

Nachdrucke 


128 

Reprints of 


A Si based light emitter made by dislocation engineering 

using wafer direct bonding 

A typical luminescence spectrum for dislocated Si with the 

quartet of defect-related D1-D4 lines (15), and the BB 

luminescence is shown in Fig. 5. The D1 line appears at 

about 1.5 µm, the wavelength suitable for the light emitters. 

Recently, an external efficiency > 0.1% at RT (corresponding 

to a few percent internal efficiency) has been reported for the 

emission in a LED utilizing glide dislocations (9). Here the 

D1 line dominates and a weak D2 line appears while the D3, 

D4 and BB lines are completely absent. However, a 

drawback in that case is that the dislocations acting in this 

device have been introduced by plastic deformation, which is 

not really reproducible in terms of device fabrication. 

Using Si wafer direct bonding can solve this reproducibility 

problem. In this method, depending on the misorientation 

between the wafers subjected to bonding, a regular 

dislocation network is formed. For the case of two (100)oriented 

Si wafers the periodic dislocation network consists 

of screw dislocations accommodating the twist component 

and of 60° dislocations compensating the tilt. The distances, 

d, between the dislocations depend on the misorientation 

angles, α, according to d ~ b/sin α (b = a/2 denotes the 

Burgers vector and is related to the Si lattice constant a = 

0.543 nm). Consequently, the distance between the 

dislocations can be controlled in a wide range by adjusting α. 

For example, for a misorientation of 2° the distance between 

the dislocations yields about d ~ 10 nm. 

Czochralski-grown (100)-oriented Si wafers with p-type 

conductivity and a resistivity of about 25 Ωcm were used for 

the experiments. After cleaning in standard RCA 1, 2 

solutions the wafers were dipped into 1% HF for 2 minutes. 

The wafers were then bonded using a commercial bonding 

equipment ‘CL 200’. After bonding the wafer pairs were 

annealed for 2 hours at 1000 °C under inert atmosphere to 

increase the bonding strength. Pairs of wafers with the 

required tilt angles were selected by X-ray diffraction from 


commercially available mirror-polished wafers. The twist 

between the wafers was adjusted prior to bonding. More 

details of the bonding treatment used are described in (16). 

An example of a periodic dislocation network consisting of 

closely spaced screw dislocations and of 60° dislocations is 

represented in Fig. 6. 

The dislocation network for the given misorientation (twist 

and tilt α value, respectively) can be well reproduced. Fig. 7 

shows that different misorientations result in different 

spectra. Hence, the luminescence spectrum can be tailored by 

the misorientation. 


# 2 

D1 

# 1 

Fig. 6 

Example of a network 

formed by Si wafer direct 

bonding and scheme: 

The TEM micrograph 

(plan view) shows a close 

mesh of screw 

dislocations due to a twist 

of ~ 1.7° and two 

horizontal lines consisting 

of 60° dislocations due to 

a tilt of ~ 0.07°. 

BB 

# 3 

0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 

Photon energy [eV] 

Fig. 7 

Tailoring the luminescence spectrum by the choice of misorientation: 

Radiation in samples containing different dislocation networks, formed by 

direct bonding of p-type Si wafers (25 Ωcm). 

For the proper misorientation, the D1 radiation is the 

dominating feature even at RT, see Fig. 8. Such result was 

achieved by using dislocation engineering for the first time. 

The process of radiative recombination, causing the emission 

at about 1.5 µm, originates from the network, i.e. in a 

spatially confined region and not in the interior of the Si bulk.

To position the dislocation network close to the wafer 

surface, the wafer pair was subjected to a layer transfer 

treatment (17). Depth positions of the network in the range 

between less than 100 nm and 1 µm can be achieved in such 

a way. This allows fabricating the network close to a p-n 

junction (Fig. 9) so that carriers injected by forward biasing 

recombine radiatively at the network. 

Fig. 8 

Dominance of D1 radiation at 1.5 µm for a dedicated network: Intensity of 

the defect D1 line in sample # 2 at 80 K, 140 K and 290 K, respectively. The 

D1 radiation dominates also at room temperature. 

To estimate the achievable quantum efficiency of the D1 

radiation we use the fact that the efficiency of the BB 

emission, observed at RT, was at least 10 times smaller (see 

Fig. 8), i.e. there holds η(D1) / η(BB) > 10. The BB 

efficiency exhibits an internal reference depending on τSRH 

and ∆n (see above). For an effective lifetime of τSRH = 5 µs 

one gets together with an excess carrier density of ∆n = 10 17 

cm -3 an internal BB efficiency of η(BB) ~ 0.5% (compare 

Fig. 4). Hence, η(D1) yields about 5%. The value of τSRH = 5 

µs used here for the effective lifetime seems to be reasonable. 

Indeed, for a trap density NT = 2 x 10 13 cm -3 , a carrier capture 

cross-section σ = 10 -15 cm 2 and a carrier thermal velocity Vth 

= 10 7 cm/s one calculates from τSRH = 1 / (NT . σ . Vth ) a 

lifetime of 5 µs. The trap density NT = 2 x 10 13 cm -3 results 

from the assumption that the dislocation network, with a 

distance of 10 nm between the dislocations, dominates the 

recombination in a volume of 100 µm thickness (diffusion 

length which corresponds to τSRH = 5 µs) and that each 

dislocation exhibits 10 5 states/traps per cm dislocation length, 

which is a reasonable value, see (18). Summarizing our 

estimates, we expect that an internal RT efficiency of the D1 

emission of a few % can be achieved. 

We believe that we have proposed a promising concept for 

the realization of a Si-based on-chip light emitter. Further 

increase of efficiency may be achieved by a ‘nanosystem’ of 

closely spaced stacks of well-defined dislocation networks. 

Nachdrucke 


Reprints of 


Fig. 9 

Schematic view of a Si LED based on D1 emission generated by a 

dislocation network. 

Acknowledgements 

The authors would like to thank D. Bolze for ion 

implantation, A. Fischer for process and device simulation, P. 

Formanek for TEM on P implanted samples, R. Kurps for 

SIMS measurements and T. Mtchedlidze for critical reading 

the manuscript. Parts of this work have been supported by the 

Volkswagenstiftung Hannover, Germany. 

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130 

Erschienene Publikationen Published Papers 

Erschienene Publikationen 

Published Papers 

(1) FTIR Study of Precipitation of Implanted 

Nitrogen in CZ-Si Annealed under High Hydro- 

static Pressure 

V.D. Akhmetov, A. Misiuk, H. Richter 

Solid State Phenomena 108-109, 157 (2005) 

The evolution of nitrogen related infrared vibrational 

spectra of CZ-Si implanted with nitrogen, with doses 

10 17 ion/cm 2 and 10 18 ion/cm 2 , at 140 keV, was studied 

after annealing at 1130 °C/5h under different hydrostatic 

pressures, from 1 bar to 10.7 kbar. It was found 

for each pressure applied, that the increased nitrogen 

dose leads to transformation of broadband spectra to 

the fine structure ones, corresponding to crystalline 

silicon nitride. The spectral position of observed sharp 

peaks in the investigated pressure region is red shifted 

in comparison to the peaks of crystalline silicon 

oxynitride found recently by other investigators in nitrogen-containing 

poly-Si as well as in a residual melt 

of nitrogen-doped CZ-Si. The application of pressure 

during annealing results in further red shift of the nitrogen-related 

bands. The observed decrease of frequency 

of vibrational bands is explained in terms of 

the pressure induced lowered incorporation of oxygen 

into growing oxynitride phase. 

(2) Enhanced Silicon Band Edge Related Radia- 

tion: Origin and Applicability for Light 

Emitters 

T. Arguirov, M. Kittler, W. Seifert, X. Yu 

Materials Science and Engineering B 124-125, 

431 (2005) 

We have investigated the influence of phosphorous 

implantation and annealing on the photoluminescence 

spectra of Si. The implantation was carried out at 

750 keV with doses between 1x10 13 and 2x10 14 cm -2 . 

We show that the band edge luminescence of the implantation 

modified layer at room temperature is low 

compared to the luminescence from the substrate. 

The photoluminescence spectra at 80 K are found to 

depend strongly on the annealing treatment performed 

(rapid thermal versus furnace annealing). For high 

implantation doses, a shift in the two-phonon-assisted 

line is observed and associated with a strong strain 


field. The band edge luminescence does not show 

quenching, but increases upon increase of temperature 

for the highest implantation dose. 

(3) Accurate Modeling of Low-Cost SiGe:C-HBTs 

Using Adaptive Neuro-Fuzzy Inference System 

A. Chakravorty, R.F. Scholz, B. Senapati, D. Knoll, 

A. Fox, R. Garg, C.K. Maiti 

Materials Science in Semiconductor Proces- 

sing 8(1-3), 307 (2005) 

A low-cost BiCMOS SiGe:C-HBT is accurately modeled 

using adaptive neuro-fuzzy inference system (ANFIS) 

for the first time. The Volterra kernel-based approach 

can be suitable for this new kind of modeling. The model 

has been trained and tested with different sets of 

input/output data. Accuracy of the model is checked 

for all the DC and S parameters in a wide range of bias 

and frequencies. On the validation of the ANFIS model, 

the average error is found to be less than 4 %. Especially 

in high-current and high-frequency regions, the 

ANFIS model is proved to be excellent unlike most of 

the physics-based equivalent circuit models that fail to 

track the actual device behavior. 

(4) Strained Silicon on Insulator (SSOI) by Wafer- 

bonding 

S.H. Christiansen, R. Singh, I. Radu, M. Reiche, 

U. Gösele, D. Webb, S. Bukalo, B. Dietrich 



Strained silicon devices provide for an enhanced carrier 

mobility compared to that of unstrained silicon 

devices of identical dimensions. The device performance 

gets even better when using strained silicon on 

insulator material. We report experimental procedures 

based on wafer bonding, smart cutting and selective 

chemical etching to obtain thin strained silicon (15 nm) 

on insulator wafers. The starting material is an 8˝ wafer 

with pseudomorphically grown strained silicon on a 

so-called virtual substrate as realized by epitaxial chemical 

vapor deposition of relaxed SiGe (grown with a 

grading rate of 10 % Ge in the SiGe-alloy per 1 µm layer 

deposition) on a Si(001) substrate. The starting and 

bonded wafers are characterized: (i) structurally using 

transmission electron microscopy, (ii) topographically, 

using atomic force microscopy and (iii) the strain is 

quantified using UV-Raman spectroscopy.

(5) Mechanisms of B Deactivation Control by 

F Co-Implantation 

N.E.B. Cowern, B. Colombeau, J. Benson, and 

A. J. Smith, W. Lerch, S. Paul, T. Graf, F. Cris- 

tiano, X. Hebras, D. Bolze 

Applied Physics Letters 86, 101905 (2005) 

Thermal annealing after preamorphization and solidphase 

epitaxy of ultrashallow B implants leads to deactivation 

and diffusion driven by interstitials released 

from end-of-range defects. F inhibits these processes 

by forming small clusters that trap interstitials. 

A competing B&F interaction causes deactivation 

when F and B profiles overlap. Both pathways suppress 

B transient enhanced diffusion. 

(6) Atomic-Scale Properties of High-k Dielectrics: 

ab initio Study for Pr-based Materials 

J. Dabrowski, A. Fleszar, G. Lippert, G. Lupina, 

A. Mane, H.J. Müssig, T. Schröder, R. Sorge, 

H. Thieme, C. Wenger, P. Zaumseil 

Advances in Solid State Physics 45, 339 

(2005) 

We discuss the atomic and electronic structures and 

energetics of native point defects and of impurities 

(Si, Ti, B, moisture) in Pr 2 O 3 and, to some extent, also 

in PrO x and in Pr 2 Si 2 O 7 , as obtained from ab initio total 

energy calculations. We introduce the concept of 

Silicon-related Nitrogen-Coordinated Oxygen (SiNCO) 

which we then use to explain the origin of fixed charge 

in classical SiO 2 films thermally grown on Si substrates 

and in high-k dielectrics deposited on Si substrates. 

(7) Paving the Way for Wireless Gigabit Networking 

J.-P. Ebert, E. Grass, R. Irmer, G. Fettweis, 

R. Kraemer 

IEEE Communication Magazine, GCN (Global 

Communications Newsletters) 43(4), 27 (2005) 

Wired LANs soared to the gigabit level some years 

ago, and terabit networks are in place for wide area 

networking. However, in terms of data rate, wireless 

short-range networks tend to lag one generation behind 

wired LANs. The recent second generation of 

wireless short-range networks offers transmission 

rates of up to 54 Mb/s. The third wireless LAN ge- 


neration is under development and will materialize in 

the IEEE 802.11n standard in about two years. IEEE 

802.11n WLANs will offer a few hundred megabits per 

second, but the performance gap from wired networks 

remains. The recently started project Wireless Gigabit 

with Advanced Multimedia (WIGWAM) aims to close 

this gap with a heterogeneous 1 Gb/s fourth-generation 

system based on high-data-rate orthogonal 

OFDM transmission, MIMO, and efficient MAC protocol 

techniques. 

(8) Preferred Orientation and Anisotropic Growth 

in Polycrystalline ZnO:Al Films Prepared by 

Magnetron Sputtering 

F. Fenske, B. Selle, M. Birkholz 

Japanese Journal of Applied Physics Letters 44, 

L662 (2005) 

A thorough growth study of thin polycrystalline ZnO: 

Al samples prepared by DC magnetron sputtering is 

presented. The atomic areal density as a function of 

deposition time t was determined by Rutherford backscattering 

(RBS), from which a growth rate G(t) can be 

defined. It was found, that in the initial stages of film 

growth G(t) increases with increasing deposition time 

up to a thickness of about 300 nm, although the process 

conditions were kept constant. In addition, the 

preferred orientation of each sample, as characterized 

by a < 00.l> fiber texture, was quantified by evaluating 

the texture index J for each sample. The course of J(t) 

was identified to concomitantly increase with G(t). The 

variation of both, growth rate and preferred orientation, 

with deposition time is interpreted to be caused by 

an anisotropic growth velocity of ZnO grains. It seems 

that such a close correlation between growth rate and 

texture has not been observed so far. 

(9) SiGe:C BiCMOS-Technology for 77-81 GHz 

Automotive Radar Applications 

G.G. Fischer 

Micromaterials and Nanomaterials 4, 54 (2005) 

The introduction of radar sensors into the modern car 

will lead to significant improvements of comfort (parking 

aid) and security (collision warning). Although systems 

with 24 GHz carrier frequency are already in use 

their maximum car park penetration cannot surpass 

7 % because of regulatory issues. Therefore, a switchover 

to 77 – 81 GHz until 2014 is mandatory. 


132 


Recent improvements in the high-frequency performance 

of SiGe:C hetero bipolar transistors (HBT) allow 

Si microelectronics to advance into areas previously 

restricted to compound semiconductor devices and 

make it a strong competitor for the application in 

77 GHz and 79 GHz voltage controlled oscillators (VCO) 

– the core circuits of high-frequency radar sensors. 

VCOs manufactured with IHP’s 0.25 µm SiGe:C BiCMOS 

technology showed good functionality around 77 GHz. 

Further research includes improving output power and 

tests of the stability and reliability of the devices under 

the requirements defined by customer specifications. 

With the funding of the German Ministry of Education 

and Research (BMBF) the joint research project KOKON 

(www.kokon-project.com) was started October 2004 

to develop and integrate technologies (with focus on 

SiGe circuits) for 77/79 GHz radar sensors. The IHP – 

a member of the Leibniz Association – is partner in the 

KOKON consortium. 

(10) Direct Evidence of Internal Schottky Barriers 

at NiSi Precipitates in Si by Electron 

Holography 

P. Formanek, M. Kittler 

Journal of Applied Physics 97, 063707 (2005) 

Thin NiSi 2 precipitates in n-type Si were analyzed by 

electron holography. A phase shift of the electron wave 

was observed around the precipitate and gives direct 

evidence about the existence of an internal Schottky 

barrier. The barrier at the interface between the precipitate 

and the Si matrix, doped with 4x10 14 cm -3 phosphorus, 

was estimated to yield about 90 mV. This value 

is about five times smaller than the dark barrier. 

The lowering of the barrier can be explained as a consequence 

of excess charge carriers generated by the 

incident electron beam. 

(11) Application of Electron Holography to Extended 

Defects 


Physica Status Solidi C2(6), 1878 (2005) 

Thin NiSi 2 precipitates in n-type Si were analyzed by 

electron holography. A phase shift of the electron wave 

was observed around the precipitate and gives direct 

evidence about the existence of an internal Schottky 

barrier. The barrier at the interface between the precipitate 

and the Si matrix, doped with 4x10 14 cm -3 phosphorus, 

was estimated to be about 90 mV. This value 


is about five times smaller than the dark barrier. The 

lowering of the barrier can be explained as a consequence 

of excess charge carriers generated by the 

incident electron beam. Additional artifacts like variation 

of mean inner potential, dead layers, and dynamical 

diffraction are discussed as well. 

(12) Potential and Limitation of Electron Holography 

in Si Research 



We report on electron holography as a promising candidate 

for diagnostics in future silicon technology and 

research. The electron holography determines the local 

phase shift of the electron wave passing through a 

sample. The phase is proportional to the 2D projected 

electrostatic potential in the sample and thus reveals 

p-n junctions and, indirectly, doping. We demonstrate 

detection of sub-monolayer boron layers in Si and 

SiGe, measurement of Ge concentration in SiGe and 

qualitative 2D oxygen mapping in SiO 2 /Si structures 

with 0.5 nm resolution, and comparison of doping in 

two bipolar transistors with different base implant. Resolution 

and noise limits are discussed. 

(13) Spectroscopic Ellipsometry for In-Line Process 

Control of SiGe:C HBT Technology 

O. Fursenko, J. Bauer, P. Zaumseil, D. Krüger, 

A. Goryachko, Y. Yamamoto, K. Köpke , B. Tillack 



Spectroscopic ellipsometry (SE) was successfully applied 

for in-line thickness and composition control 

of graded SiGe:C heterojunction bipolar transistors 

(HBTs). We have calculated a thickness of Si-cap and 

SiGe:C base, split into the gradient and plateau part 

and Ge content in the plateau. The procedure included 

the creation of databases for the refractive index dispersion 

of all components of HBT stacks using simple 

one-layer structures, with thickness and composition 

calibrated by X-ray diffractometry (XRD). These databases 

(e.g. SiGe:C optical constants vs. Ge content) 

were applied for thickness and composition characterization 

of graded HBTs with different profile shapes. 

The difference between SE and XRD for the estimation 

of the main structural parameters is discussed. Finally, 

the suitability of SE for measuring wafer uniformity 

of HBT layer thickness and composition was demons-

trated, allowing a proper and efficient fine-tuning of 

the epitaxial growth process. 

(14) A DC-10 GHz Amplifier With Digital Offset 

Correction 

H. Gustat 



This work presents a SiGe:C wideband amplifier with a 

binary CMOS counter for digital offset adjustment. The 

application of the radix

134 


de precipitation in nitrogen-doped silicon, the results 

clearly demonstrate that Ostwald ripening takes place 

during annealing of N-doped silicon wafers at 1000 °C 

and 1100°C. The higher the nitrogen doping and the 

higher the temperature the faster the oxide precipitates 

grow and the faster they split into two fractions. 

One fraction is growing at the expense of the other. 

(19) Oxygen Precipitation in Nitrogen Doped Silicon 

G. Kissinger, T. Müller, A. Sattler, W. Häckl, 

M. Weber, U. Lambert, A. Huber, P. Krottenthaler, 

H. Richter, W. von Ammon 


Nitrogen doping of CZ silicon results in an early formation 

of large precipitate nuclei during crystal cooling, 

which are stable at 900 °C. These are prone to develop 

stacking faults and high densities of defects inside 

defect denuded zones of CZ silicon wafers. Simultaneous 

doping of FZ silicon with nitrogen and oxygen 

results in two main stages of precipitate nucleation 

during crystal cooling, an enhanced nucleation around 

800 °C, which is nitrogen induced, and a second enhancement 

around 600 °C, which depends on the concentration 

of residual oxygen on interstitial sites. A 

combined technique of ramping with 1 K/min from 500- 

1000 °C with a final anneal at 1000 °C for 2 h and lateral 

BMD measurement by SIRM provides a possibility to delineate 

v/G on nitrogen-doped silicon wafers. Surface 

segregation of nitrogen and oxygen during out-diffu- 

sion can explain the enhanced BMD formation in about 

10 µm depth and the suppressed BMD formation in 

about 40 µm depth below the surface. The precipitate 

growth is enhanced in regions where nitrogen is filled 

up again after a preceding out-diffusion. 

(20) Silicon-based Light Emission after Ion Implantation 

M. Kittler, T. Arguirov, A. Fischer, W. Seifert 

Optical Materials 27, 967 (2005) 

Electroluminescence of boron and phosphorus implanted 

samples has been studied for various implantation 

and annealing conditions. Phosphorus implantation is 

found to have a similar effect on light emission as boron 

implantation. The band-to-band luminescence of 

phosphorus implanted diodes is observed to increase 

by more than one order of magnitude upon rising 

the sample temperature from 80 K to 300 K and a 


maximum internal quantum efficiency of 2 % has been 

reached at 300 K. The remarkably high band-to-band 

luminescence is attributed to a high bulk Shockley- 

Read-Hall lifetime, likely promoted by the gettering action 

of the implanted phosphorus. The anomalous temperature 

behavior of the efficiency can be explained 

by a temperature dependence of the lifetime characteristic 

of shallow traps. 

(21) Silicon Based Light Emitters for On-Chip 

Optical Interconnects 

M. Kittler, T. Arguirov, W. Seifert, X. Yu, M. Reiche 


Electroluminescence of B and P implanted samples 

has been studied. P implantation is found to have a similar 

effect on light emission as B implant. The bandto-band 

(BB) luminescence of P implanted diodes is 

observed to increase by more than one order of magnitude 

upon rising the temperature and an internal efficiency 

of 2 % has been reached at 300 K. An efficiency 

larger than 5 % seems to be reachable. The strong 

BB line emission at 1.1 µm is attributed to high bulk 

SRH lifetime. The BB line escapes from the substrate 

below the p-n junction. It is not due to the implantationrelated 

defects/dislocations. The luminescence spectrum 

can be tailored to achieve dominance of the dislocation-related 

D1 line at about 1.5 µm. It is observed 

that a regular periodic dislocation network, formed by 

Si wafer direct bonding with a specific misorientation, 

exhibits even at 300 K only D1 photoluminescence. 

Such a dislocation network is believed to be a serious 

candidate to gain an efficient Si-based light emitter. 

(22) Advanced Activation of Ultra-Shallow Junctions 

Using Flash-assisted RTP 

W. Lerch, S. Paul, J. Niess, S. McCoy, T. Selinger, 

J. Gelpey, F. Cristiano, F Severac, M. Govelle, 

S. Boninelli, P. Pichler, D. Bolze 

Materials Science and Engineering B 124-125, 

24 (2005) 

A key issue associated with the continous reduction of 

dimensions of CMOS transistors is the realization of 

highly conductive, ultra-shallow junctions for source/ 

drain extensions. Millisecond annealing as an equipment 

technology provides and ultra-sharp temperature 

peak of 1.6 ms width which favors dopant activation but 

nearly suppresses dopant diffusion to form extremely 

shallow, highly electrically-activated junctions without

melting the substrate. On boron beamline implanted 

wafers the formation of junctions at peak temperatures 

ranging from 1275 up to 1325 ° C was investigated. 

In the special case of boron, silicon wafers deeply 

pre-amorphized with Ge were also used. The thermal 

stability of these boron profile distributions was evaluated 

by subsequent thermal anneals ranging from 

250 ˚C to 1050 °C with times from a few seconds to 

several hundred seconds From these experiments the 

deactivation/re-activation mechanism for subsequent 

annealing can be explained. All the junctions were 

analyzed by four-point probe measurements; selec- 

ted samples were analyzed by Hall-effect, secondary 

ion mass spectrometry (SIMS), and transmission electron 

microscopy (TEM). 

(23) Initial Stages of the Epitaxial Growth of 

Pr 2 O 3 on Si(111) Studied by LEED and STM 

L. Libralesso, T. Schröder, T.-L. Lee, J. Zegenhagen 

Surface Science 598, L347 (2005) 

The initial stages of the molecular beam epitaxy 

growth of Pr 2 O 3 on atomically clean Si(111) have been 

studied in ultra-high vacuum by low energy electron 

diffraction and scanning tunneling microscopy. At very 

low coverages, the oxide nuclei decorate the dimer 

rows of the silicon surface as line structure forming 

open triangles. At higher coverages, two-dimensional, 

equilateral, triangular islands with a fairly narrow size 

distribution and a well defined thickness are observed. 

Island nucleation occurs both at step edges and on the 

terraces. Upon coalescence at coverages beyond one 

monolayer, the surface is covered by a flat and pseudomorphic 

oxide film with a (111) surface unit cell. 

(24) Si Segregation into Pr 2 O 3 and La 2 O 3 High-k 

Gate Oxides 

G. Lippert, J. Dabrowski, V. Melnik, R. Sorge, 

Ch. Wenger, P. Zaumseil, H.-J. Müssig 

Applied Physics Letters 86(4), 042902 (2005) 

Pr and La oxide thin films were investigated in the 

context of their application as high-k dielectrics in 

Complementary Metal Oxide (CMOS) technology. 

The films were deposited by Molecular Beam Epitaxy 

(MBE) on bare and TiN-covered Si(001). The influence 

of growth and post-deposition annealing on the composition 

and electrical parameters was studied. We 

observed Si penetration from bare Si(001) into the 


growing film. Based on the results of capacitance-voltage 

(CV) measurements and ab initio calculations we 

conclude that Si is a source of defects responsible for 

leakage currents. 

(25) Preparation of Praseodymium Silicate Dielectrics 

with an Atomically Abrupt Interface 

on Si(100) 

G. Lupina, T. Schröder, J. Dabrowski, C. Wenger, 

A. Mane, G. Lippert, H.-J. Müssig, P. Hoffmann, 

D. Schmeisser 


Synchrotron radiation x-ray photoelectron spectroscopy 

was applied to study the solid state reaction between 

praseodymium and thin silicon dioxide layers on 

Si(100). Nondestructive depth profiling studies by varia- 

tion of the incident photon energy indicate after praseo- 

dymium deposition at room temperature the reaction 

of the upper silicon dioxide to praseodymium oxide and 

silicide. High-temperature annealing of films with an appropriate 

praseodymium / silicon dioxide ratio results 

in homogeneous praseodymium silicate films with an 

atomically abrupt interface. Ab initio calculations corroborate 

the results of the photoemis-sion study. 

(26) Modified Virtually Scaling Free Adaptive 

CORDIC Rotator Algorithm and Architecture 

K. Maharatna, S. Banerjee, E. Grass, M. Krstic, 

A. Troya 

IEEE Transactions on Circuits and Systems for 

Video Technology (CSVT) 15(11), 1463 (2005) 

In this paper, we proposed a novel Coordinate Rotation 

Digital Computer (CORDIC) rotator algorithm that 

converges to the final target angle by adaptively executing 

appropriate iteration steps while keeping the scale 

factor virtually constant and completely predictable. 

The new feature of our scheme is that, depending 

on the input angle, the scale factor can assume only 

two values, viz., 1 and 1/sqrt2, and it is independent 

of the number of executed iterations, nature of itera- 

tions, and word length. In this algorithm, compared to 

the conventional CORDIC, a reduction of 50 % iteration 

is achieved on an average without compromising 

the accuracy. The adaptive selection of the appro- 

priate iteration step is predicted from the binary representation 

of the target angle, and no further arithmetic 

computation in the angle approximation datapath 

is required. The convergence range of the proposed 


136 


CORDIC rotator is spanned over the entire coordinate 

space. The new CORDIC rotator requires 22 % less 

adders and 53 % less registers compared to that of 

the conventional CORDIC. The synthesized cell area 

of the proposed CORDIC rotator core is 0.7 mm 2 and 

its power dissipation is 7 mW in IHP in-house 0.25 µm 

BiCMOS technology. 

(27) A CMOS Process-Compatible Wet-Etching 

Recipe for the High-k Gate Dielectrics Pr 2 O 3 

and Pr 2-x Ti x O 3 

A.U. Mane, Ch. Wenger, T. Schröder, P. Zaumseil, 

G. Lippert, G. Weidner, H.-J. Müssig 

Journal of the Electrochemical Society 152(6), 

C399 (2005) 

The fabrication of complementary metal oxide semiconductor 

(CMOS) structures with praseodymium oxide 

(Pr 2 O 3 ) or titanium-doped praseodymium oxide 

(Pr 2-x Ti x O 3 ) (0x1) layers as integrated high-k gate dielec- 

trics requires the development of a process-compatible 

etching recipe. Different wet-etching processes 

in acid-based chemistry were evaluated and solu- 

tions of diluted sulfuric acid were identified as suitable 

etchants for Pr 2 O 3 and Pr 2-x Ti x O 3 layers on Si substrates. 

Metal-oxide-semiconductor stacks with poly-Si 

as the potential gate electrode were patterned with 

the help of tetramethyl ammonium hydroxide as the 

selective etchant attacking the poly-Si gate electrode 

material but not the underlying Pr-based high-k gate 

dielectric layers. 

(28) Process Integration of Pr-Based High-k Dielectrics 

A.U. Mane, C. Wenger, G. Lupina, T. Schröder, 

G. Lippert, R. Sorge, P. Zaumseil, G. Weidner, 

J. Dabrowski, H.-J. Müssig 

Microelectronic Engineering 82, 148 (2005) 

We present microprocessing compatibility of Pr-based 

high-k gate dielectrics for complementary metal-oxide-semiconductor 

(CMOS) devices. MOS structures 

integrated with boron-doped poly-Si and Pr-based 

oxides layers were deposited by molecular beam epitaxy 

(MBE) process. Reactive ion etching (RIE) with 

CF 4 /O 2 plasma was used to etch the poly-Si layer selectively. 

Diluted H 2 SO 4 based solutions was used to 

etch Pr-based oxides layers. Details of etch kinetics of 

Pr-based oxides layers, poly-Si and electrical properties 

of MOS devices are presented. 


(29) Electric-dipole Spin Resonance Signals Related 

to Extended Agglomerates of Interstitial 

in Silicon 

T. Mchedlidze, S. Binetti, A. Le Donne, S. Pizzini, 

M. Suezawa 


Three electric-dipole spin resonance (EDSR) signals 

from defects having C1h symmetry were detected in 

Czochralski-grown silicon (Cz-Si) samples. The signals 

labelled TU7, TU8 and TU9 were detected after subjecting 

of the samples to two-step annealing procedures 

at 450 °C and at 650 °C for prolonged times. 

Formation and structural evolution of large interstitial 

agglomerates known as rod-like defects (RLD) occur 

in Cz-Si during analogous annealing procedures. Comparison 

of the EDSR signal details with the formation 

peculiarities and the defect structures of the RLDs, inferred 

from previous investigations, allows assigning 

of the TU7, TU8 and TU9 spectra to the line-interstitial 

defects, the planar defects and the dislocation dipoles, 

respectively. Correlations of the EDSR signals 

and peculiarities in the PL spectra for the samples 

are reported. 

(30) Formation and Properties of Iron-Phosphorus 

and Iron-Phosphorus-Hydrogen Complexies 

in Silicon 

T. Mchedlidze 


Hitherto unreported ESR signal, labelled TU10, was 

detected after annealing of electron-irradiated silicon 

samples doped with phosphorus, iron and hydrogen. 

The ESR spectrum corresponds to a complex having 

monoclinic-I symmetry and S = 3/2 spin-state. Hyperfine 

structure of the TU10 spectrum suggests participation 

of two nucleus with spin I = 1/2 and 100 % 

abundance in the core of the related defect. Doping 

of samples with hydrogen-deuterium mixture revealed 

presence of one hydrogen atom in the complex. The 

second nucleus with I = 1/2 is apparently a phosphorus 

atom. Presence of single iron atom was verified by 

doping with iron heaving modified isotope content. An 

intensity of the previously reported TU6 signal, related 

to iron-phosphorus complex, was significantly suppressed 

in hydrogen-doped samples.

(31) Precipitation Enhancement of so Called Defect-Free 

Czochralski Silicon Material 

T. Müller, G. Kissinger, P. Krottenthaler, C. Seuring, 

R. Wahlich, W. von Ammon 


Thermal treatments to enhance precipitation like RTA, 

ramp anneal and argon anneal were performed on low 

oxygen 300 mm wafers without vacancy or interstitial 

agglomerates (so called defect-free material). Best results 

were achieved using high temperature argon anneal 

leading to a homogenous BMD and denuded zone 

formation. Furthermore the getter efficiency was positively 

tested by intentional Ni-contamination. 

Concepts to overcome the slip danger like improved 

support geometries and nitrogen codoping were also 

evaluated and are seen to be beneficial. 

(32) Enhanced Relaxation of SiGe Layers by He 

Implantation Supported by in situ Ultrasonic 

Treatments 

B. Romanjuk, V. Kladko, V. Melnik, V. Popov, 

V. Yukhymchuk, A. Gudymenko, Ya. Olikh, 

G. Weidner, D. Krüger 



Helium implantation-enhanced strain relaxation of SiGe 

layers grown pseudomorphically on Si substrates is an 

interesting alternative for the creation of strained Si 

CMOS structures. Here we demonstrate the applica- 

tion of additional in situ ultrasonic treatment (UST) during 

He ion implantation for the formation of relaxed 

Si 0.8 Ge 0.2 buffer layers. By Raman spectroscopy and 

X-ray diffraction we show increased relaxation of the 

SiGe layers under the influence of UST. A rectangular 

dislocation network with a high dislocation density 

of about 10 9 -10 10 cm -2 concentrated near the interface 

between the SiGe layer and the Si substrate is 

shown by TEM for 100 nm SiGe/Si heterostructures 

after heat treatment at 750 °C, 60 s. Application of 

ultrasonic waves during He implantation keeps a low 

surface roughness of about 0.5 nm. 

(33) High-Frequency SiGe:C HBTs With Elevated 

Extrinsic Base Regions 

H. Rücker, B. Heinemann, R. Barth, D. Knoll, 

P. Schley, R. Scholz, B. Tillack , W. Winkler 




This paper reports on the transistor design of highspeed 

SiGe HBTs with low parasitic resistances and 

capacitances. Elevated extrinsic base regions and a 

low-resistance collector design were integrated in a 

SiGe:C BiCMOS technology to simultaneously minimize 

base and collector resistances and base-collector 

capacitance. This technology features CML ring oscillator 

delays of 3.6 ps per stage for HBTs with f T /f max 

values of 190/243 GHz and a BV CEO of 1.9 V. 

(34) Titanium-Added Praseodymium Silicate 

High-k Layers on Si(001) 

T. Schröder, G. Lupina, J. Dabrowski, A. Mane, 

C. Wenger, G. Lippert, H.-J. Müssig 


Titanium-added praseodymium silicate layers on 

Si(001) are promising high-k insulators for siliconbased 

nanoelectronic devices. Synchrotron radiation 

x-ray photoelectron spectroscopy was applied to study 

the effect of titanium additives on the praseodymium 

silicate/Si system. Nondestructive depth profiling 

by variation of the photon energy shows that thermal 

annealing activates the diffusion of deposited titanium 

into the praseodymium silicate. A homogeneous praseodymium 

titanium silicate layer is formed that shows 

high-quality electrical properties. 

(35) Structure, Twinning Behaviour and Interface 

Composition of Epitaxial Si(111) Films 

on Pr 2 O 3 (0001)/Si(111) Support Systems 

T. Schröder, P. Zaumseil, G. Weidner, G. Lupina, 

C. Wenger, H.-J. Müssig, P. Stork, 


The structure of epitaxial Si overlayers on a hexagonal 

Pr 2 O 3 (0001)/Si(111) substrate system was investigated 

by a combination of x-ray reflectivity, specular 

x-ray diffraction, off-specular grazing incidence x-ray 

diffraction, and transmission electron microscopy. 

The Pr 2 O 3 film grows on the Si(111) substrate in the 

(0001)-oriented hexagonal phase matching the in-plane 

symmetry by aligning the [100] oxide along the bulk 

[01] Si direction. The hexagonal Pr 2 O 3 (0001) surface 

induces the growth of [111]-oriented cubic-Si epilayers 

exhibiting a microstructure which is composed of two 

types of domains. The ABC-stacked domains preserve 

the crystal orientation of the substrate, while the CBAstacked 

domains are rotated by 180°. A depth profile 

of the chemical composition of the epi-Si/Pr 2 O 3 / 


138 


Si(111) material stack was recorded by combining ionbeam 

sputtering techniques with x-ray photoelectron 

spectroscopy. 

(36) Structure and Strain Relaxation Mechanisms 

of Ultrathin Epitaxial Pr 2 O 3 Film on 

Si(111) 

T. Schröder, T.-L. Lee, L. Libralesso, I. Joumard, 

J. Zegenhagen, P. Zaumseil, C. Wenger, G. Lippert, 

J. Dabrowski, H.-J. Müssig 

Journal of Applied Physics 97(7), 074906 (2005) 

The structure of ultrathin epitaxial Pr 2 O 3 films on 

Si(111) was studied by synchrotron radiation-grazing 

incidence x-ray diffraction. The oxide film grows as 

hexagonal Pr 2 O 3 phase with its (0001) plane attached 

to the Si(111) substrate. The hexagonal (0001) Pr 2 O 3 

plane matches the in-plane symmetry of the hexagonal 

Si(111) surface unit cell by aligning the [1010] Pr 2 O 3 

along the [112] directions. The small lattice mismatch 

of 0.5 % results in the growth of pseudomorphic oxide 

films of high crystalline quality with an average domain 

size of about 50 nm. The critical thickness tc 

for pseudomorphic growth amounts to 3.0±0.5 nm. 

The relaxation of the oxide film from pseudomorphism 

to bulk behavior beyond t c causes the introduction of 

misfit dislocations, the formation of an in-plane small 

angle mosaicity structure, and the occurence of a phase 

transition towards a (111) oriented cubic Pr 2 O 3 film 

structure. The observed phase transition highlights 

the influence of the epitaxial interface energy on the 

stability of Pr 2 O 3 phases on Si(111). A mechanism is 

proposed which transforms the hexagonal (0001) into 

the cubic (111) Pr 2 O 3 epilayer structure by rearranging 

the oxygen network but leaving the Pr sublattice almost 

unmodified. 

(37) Impact of Low Temperature Hydrogenation 

on Recombination Activity of Dislocations 

in Silicon 

O.F. Vyvenko, M. Kittler, W. Seifert 


Silicon samples doped with gallium and intentionally 

contaminated with iron have been studied by means of 

electron beam current (EBIC), capacitance voltage (CV) 

and deep level transient spectroscopy (DLTS) methods. 

Reverse bias anneal (RBA) treatments at temperatures 

of 390-420 K were used to move hydrogen and dissolved 

iron atoms away from the surface. A new proce- 


dure was developed to find dislocations lying on desirable 

depth from the surface and to analyze the depth 

distribution of their recombination contrast. Iron contaminated 

dislocations do not noticeably change their 

recombination activity when kept in an electrical field 

as high as 104 V/cm at 420 K for several hours. This 

implies a tight binding of iron atoms at dislocations. 

The binding energy of iron with dislocations seems 

to be much larger than for Fe-Ga and H-Ga pairs. Low 

temperature hydrogenation of iron contaminated dislocations 

does not produce any passivation effect. In opposite, 

the recombination activity of the dislocations 

significantly increases after RBA treatment. 

(38) Recombination Activity and Electrical Levels 

of Dislocations in p-Type SiGe Structures: 

Impact of Copper Contamination and Hydrogenation 

O.F. Vyvenko, M. Kittler, W. Seifert, M.V. Trushin 

Physica Status Solidi C2 (6), 1852 (2005) 

Deep levels, associated with misfit dislocations in clean 

and copper contaminated p-type Si/Si 0.98 Ge 0.02 /Si structures, 

are under consideration. In the as-grown (noncontaminated) 

samples dislocations were found to exhibit 

a very low recombination activity, detectable with 

the electron-beam-induced current technique only at 

low temperatures. Deep-level-transient spectroscopy 

revealed a dislocation-related hole trap level at E t = E v 

+ 0.2 eV which was identified as band-like. The position 

of the observed level is close to the theoretically 

predicted hole trap state of the intrinsic stacking 

fault between a dissociated dislocation. Contamination 

with a low copper concentration (5 ppb) gave rise 

to a large increase of the recombination activity of 

the dislocations and to the appearance of another dislocation-related 

defect level at E t = E v + 0.32 eV. Hydrogenation 

of the copper contaminated sample by 

a treatment with an acid solution and subsequent reverse-bias 

anneal at 380 K resulted in the evolution of 

the levels of substitutional copper and its complexes 

with hydrogen. 

(39) MIM Capacitors Using Amorphous High-k 

PrTi x O y Dielectrics 

C. Wenger, R. Sorge, T. Schröder, A.U. Mane, 

G. Lippert, G. Lupina, J. Dabrowski, P. Zaumseil, 

H.-J. Müssig 

Microelectronic Engineering 80, 313 (2005)

Capacitor performance of amorphous PrTi x O y dielectric 

films deposited on TiN x metal electrodes to form MIM 

structures with Al top electrodes is demonstrated for 

the first time. The PrTi x O y capacitors were fabricated 

within the temperature budget of back end processes. 

Preliminary data on the composition of the dielectric layers 

and the interaction of water with the films was obtained 

by X-ray photoelectron spectroscopy (XPS). The I(V) 

and C(V) device characteristics are discussed. 

(40) A 117 GHz LC-Oscillator in SiGe:C BiCMOS 

Technology 

W. Winkler, J. Borngräber, B. Heinemann 

Materials Science in Semiconductor Processing 

8(1-3), 459 (2005) 

In this paper a voltage-controlled oscillator (VCO) is 

presented reaching oscillation frequencies well above 

100 GHz. The oscillator has been fabricated in a 200 GHz 

SiGe:C BiCMOS technology with 0.25 µm minimum feature 

size. In the design of the VCO two circuit approaches 

were considered. The first used transmissionlines 

in the resonator and the second used inductors 

above the silicon substrate. It is shown by simulation 

that by using inductors a higher oscillation frequency 

can be obtained. The fabricated oscillator has a tuning 

range from 113.2 to 117.2 GHz at a supply voltage of 

-3 V. This oscillation frequency is the highest reported 

so far for a silicon-based transistor technology. 

(41) High Resolution XRD Characterization of 

SiGeC Structures for High Frequency Microelectronics 

Applications 

P. Zaumseil 

Journal of Alloys and Compounds 401, 254 


It is demonstrated how high resolution X-ray diffractometry 

(XRD) in comparison to different other characterization 

techniques, reflectometry, spectroscopic ellipsometry, 

Auger electron spectroscopy, secondary ion 

mass spectroscopy, and transmission electron microscopy, 

can be used to analyze the layer properties of 

typical SiGeC hetero-bipolar transistor (HBT) structures. 

For three different HBTs the parameters of Si cap 

and total SiGeC layer thickness, and the maximum Ge 

content are measured and the error limits of the different 

techniques are discussed. The values obtained 

agree very well within the error limits. Concerning layer 

thickness an achievable accuracy of about 1 nm is 


realistic and reproducible in a routine process. The 

highest accuracy in Ge content determination of about 

0.5 % can be realized by XRD and well-calibrated spectroscopic 

ellipsometry. XRD measurements in small 

(0.5x0.5 mm 2 ) structures show comparable results 

with a laboratory source and synchrotron radiation. 

(42) A Complex X-Ray Characterization of Epitaxially 

Grown High-k Gate Dielectrics 

P. Zaumseil, T. Schröder 

Journal of Physics D 38, A179 (2005) 

Different x-ray techniques are used to characterize 

Pr 2 O 3 layers epitaxially grown on Si substrates. X-ray 

reflectometry is the preferred technique to determine 

the layer thickness and to detect and characterize 

possible interface layers. With standard x-ray diffraction 

(XRD), we found for 100 Si substrates that Pr 2 O 3 

grows in its cubic phase with the 110 direction perpendicular 

to the surface, while the hexagonal phase 

in 0001 orientation is preferred for 111 Si. In the thickness 

range of microelectronics applications, Pr 2 O 3 layers 

can be considered as well-ordered heteroepitaxial 

structures. The relaxation of the oxide layer from 

pseudomorphism to bulk behaviour was studied in the 

technologically important thickness range(1-10 nm) by 

synchrotron radiation grazing incidence XRD. 

(43) Structural Characterization of Epitaxial 

Si/Pr 2 O 3 /Si(111) Heterostructures 

P. Zaumseil, T. Schröder, G. Weidner 


The use of heteroepitaxial Si/Pr 2 O 3 /Si(111) systems as 

semiconductor-insulator-semiconductor (SIS) stacks in 

future applications requires a detailed structural characterization. 

We used X-ray reflectivity (XRR) to control 

layer thickness and interface roughness, standard 

X-ray diffraction (XRD) to analyze the Pr 2 O 3 phase, orien- 

tation and crystal perfection, and grazing incidence 

XRD to study the thin epitaxial Si top layer. Transmission 

electron microscopy (TEM) was used to prove 

the results by direct imaging on a microscopic scale. 

Pr 2 O 3 grows epitaxially in its hexagonal phase and 

(0001) orientation on Si(111) substrates. An epitaxial 

Si overgrowth in (111) orientation and good perfection 

is possible, but such Si layers exhibit two stacking 

twins, one with the same in-plane orientation as the 

substrate and one rotated by 180° around the Si [111] 

direction. 


140 


(44) FTIR Spectroscopic System with Improved 

Sensitivity 

V.D. Akhmetov, H. Richter 

Proc. DRIP XI, 37 (2005) 

(45) Optimization of Anti-reflective Coatings for 

Lithography Applications 

J. Bauer, S. Virko, B. Kuck, T. Grabolla, V. Melnik, 

O. Fursenko, W. Mehr 

Proc. SPIE 5835, 263 (2005) 


Lithography Application 

J. Bauer, S. Virko, B. Kuck, T. Grabolla, V. Melnik, 

O. Fursenko, W. Mehr 

GMM-Fachberichte, 177 (2005) 

(47) A Low-Power, 10 Gs/s Track-and-Hold Amplifier 

in SiGe BiCMOS Technology 

Y. Borokhovych, H. Gustat, B. Tillack, B. Heinemann, 

Y. Lu, W.-M. Lance Kuo, X. Li, R. Krithi- 

vasan, J.D. Cressler 

Proc. ESSCIRC, 263 (2005) 

(48) Area Efficient Hardware Implementation of 

Elliptic Curve Cryptography by Iteratively 

Applying Karatsuba‘s Method 

Z. Dyka, P. Langendörfer 

Proc. Design Automation and Test (DATE), 70 


(49) Enhanced GALS Techniques for Datapath Applications 

E. Grass, F. Winkler, M. Krstic, A. Julius, C. Stahl, 

M. Piz 

Integrated Circuit and System Design, 15 th Int. 

Workshop PATMOS, Berlin Springer Verlag, 581 


(50) NOR/OR Register Based ECL Circuits for 

Maximum Data Rate 

H. Gustat, J. Borngräber 

Proc. BCTM, 90 (2005) 

(51) System-Level Simulation of a Noisy Phase- 

Locked Loop 

F. Herzel 

Proc. 13 th European Gallium Arsenide and other Semiconductor 

Application Symposium, 193 (2005) 


(52) Frequency Synthesis for 60 GHz OFDM Systems 

F. Herzel, M. Piz, E. Grass 

Proc.10 th International OFDM Workshop, 303 


(53) Combination of Optical Measurements and 

Precipitation Theory to Overcome the Obstacles 

of Detection Limits 

G. Kissinger, T. Müller, A. Sattler, W. Häckl, P. Krottenthaler, 

T. Grabolla, H. Richter, W. von Ammon 

Proc. DRIP XI, 67 (2005) 

(54) Dislocation Engineering for a Si-Based Light 

Emitter at 1.5 µm 

M. Kittler, M. Reiche, T. Arguirov, W. Seifert, X. Yu 

Technical Digest IEDM, 1027 (2005) 

(55) A Low-Cost SiGe:C BiCMOS Technology with 

Embedded Flash Memory and Complementary 

LDMOS Module 

D. Knoll, A. Fox, K.-E. Ehwald, R. Barth, A. Fischer, 

B. Heinemann, H. Rücker, P. Schley, R. Scholz, 

F. Korndörfer, B. Senapati, V.E. Stikanov, B. Tillack, 

W. Winkler, Ch. Wolf, P. Zaumseil 


(56) BIST Testing for GALS Systems 

M. Krstic, E. Grass 

Proc. 8 th EUROMICRO Conference on Digital System 

Design - Architecture, Methods and Tools 

(DSD), 10 (2005) 

(57) Request-driven GALS Technique for Wireless 

Communication System 

M. Krstic, E. Grass, C. Stahl 

Proc. IEEE International Symposium on Asynchronous 

Circuits and Systems (ASYNC), 76 (2005) 

(58) Privacy and Convenient Up Time of Mobile 

Devices: An Antagonism? 

P. Langendörfer 

Proc. Research Trends in Science and Technology 

(RTST), Abstract book, 3 (2005) 

(59) More Privacy in Context-aware Platforms: 

User Controlled Access Right Delegation 

Using Kerberos 

P. Langendörfer, K. Piotrowski

Proc. 4 th WSEAS International Conference on Information 

Security, Communications and Computers 

(ISCOCO), 542 (2005) 

(60) Charged Location Aware Services 

P. Langendörfer, K. Piotrowski, M. Maaser 

Proc. IEEE International Conference on Mobile 

Business (ICMB), 116 (2005) 

(61) Implementation Independent Profiling of 

SDL Specifications 

P. Langendörfer, M. Lehmann 

Proc. Software Engineering, 155 (2005) 

(62) Is the IEEE 802.11 MAC Layer Suitable for 

Car-to-Car Communication ? 

W. Lohmann, J.-P. Ebert, M. Grade, A. Lübke, 

R. Kraemer 

Proc. 1 st Workshop on Wireless Vehicular Communications 

and Services for Breakdown Support 

and Car Maintenance (W-CarsCare‘05), 28 


(63) A 8-bit, 12 GSample/sec SiGe Track-and- 

Hold Amplifier 

Y. Lu, W-M. L. Kuo, X. Li, R. Krithivasan, J.D. 

Cressler, Y. Borokhovych, H. Gustat, B. Tillack, 

B. Heinemann 


(64) Automated Negotiation of Privacy Contracts 

M. Maaser, P. Langendörfer 

Proc. 29 th Annual International Computer Software 

and Applications Conference, 505 (2005) 

(65) An Efficient Strategy of Processing Distributed 

Location Based Events 

O. Maye 

Proc. IEEE International Conference on Pervasive 

Services (ICPS‘05), 218 (2005) 

(66) The Impact of Channel Engineering on the 

Performance and Reliability of LDMOS Transistors 

N.R. Mohapatra, K.-E. Ehwald, R. Barth, H. Rücker, 

D. Bolze, P. Schley, D. Schmidt, H.-E. Wulf 

Proc. ESSDERC, 481 (2005) 


(67) Design of Wireless Systems Utilizing 

Scratchpad Memories 

G. Panic, Z. Stamenkovic, K. Tittelbach-Helmrich, 

J. Lehmann, G. Schoof 

Proc. IP Based SoS Design (IP-SOC), 221 (2005) 


K. Piotrowski, P. Langendörfer, M. Maaser, 

G. Spichal, P. Schwander 

Proc. International Workshop on Wireless Information 

Systems (WIS-2005), 33 (2005) 

(69) Plasma Etching of Carbon Hard Mask Stacks 

for Sub-100nm Technologies 

H.H. Richter, K.A. Pears, M. Markert, S. Günther, 

S. Marschmeyer, H. Silz, G. Weidner, H. Kirmse, 

W. Neumann 

Proc. 12. Bundesdeutsche Fachtagung Plasmatechnologie,132 


(70) A Class AB 6 th Order Log-Domain Filter in 

BiCMOS with 100-500 MHz Tuning Range 

K. Schmalz, M.A. Teplechuk, J.I. Sewell 

Proc. European Conference on Circuit Theory 

and Design (ECCTD) II, 111 (2005) 

(71) Hazard Detection in GALS Wrapper: A Case 

Study 

C. Stahl, W. Reisig, M. Krstic 

Proc. 5 th Int. Conf. on Application of Currency to 

System Design (ASCD), 234 (2005) 

(72) A Fully Integrated 60 GHz LNA in SiGe:C 

BiCMOS Technology 

Y. Sun, J. Borngräber, F. Herzel, W. Winkler 

Proc. IEEE Bipolar/BiCMOS Circuits and Technology 

(BCTM), 14 (2005) 

(73) Atomic Layer Processing for Doping of SiGe 

B. Tillack, Y. Yamamoto, D. Bolze, B. Heinemann, 

H. Rücker, J. Murota, W. Mehr 

Proc. 1 st International Workshop on New Group 

IV Semiconductor Nanoelectronics, Program & 

Abstracts, 11 (2005) 

(74) Atomic Control of SiGe Epitaxy and Doping 

B. Tillack, Y. Yamamoto, K.-D. Bolze, B. Heinemann, 

H. Rücker, D. Knoll, D. Wolansky, J. Murota, 

W. Mehr 



142 

Proc. of the 4 th International Conference on Silicon 

Epitaxy and Heterostructures (ICSI-4), Program 

& Abstracts, 82 (2005) 

(75) Low-Complexity Initialization of Adaptive 


G. Wang, R. Kraemer 

Proc. 5 th IEEE International Symposium on Signal 

Processing and Information Technology 

(IEEE ISSPIT 2005), 694 (2005) 

(76) Low-Power 71 GHz Static Frequency Divider 

in SiGe:C HBT Technology 

L. Wang, J. Borngräber, G. Wang, Z. Gu, A. Thiede 

International Microwave Symposium (IEEE 

MTT-S) P. (2005) 

(77) 60 GHz Circuits in SiGe HBT Technology 

W. Winkler 

Proc. Compound Semiconductor IC Symposium 

(CSICS),109 (2005) 

(78) Millimeter-Wave Integrated Circuits in SiGe:C 


W. Winkler 

Proc. Microwave Workshop and Exhibition (MWE 

2005), 459 (2005) 

(79) A Fully Integrated BiCMOS PLL for 60 GHz 


W. Winkler, J. Borngräber, B. Heinemann, F. Herzel 

Proc. International Solid State Circuits Conference 

(ISSCC 2005), 406 (2005) 

(80) Chemical Vapor Phase Etching of Polycrystalline 

Selective to Epitaxial SiGe 

Y. Yamamoto, B. Tillack, K. Köpke, O. Fursenko 

Proc. 4 th International Conference on Silicon Epitaxy 

and Heterostructures (2005) 

(81) P Doping Control During SiGe:C Epitaxy 

Y. Yamamoto, B. Tillack, K. Köpke, R. Kurps 

Proc. of the 4 th International Conference on Silicon 

Epitaxy and Heterostructures, 200 (2005) 


(82) X-Ray Reflectivity Characterization of Thin 

Film and Multilayer Structures 

P. Zaumseil 

Materials for Information Technology / E. Zschech, 

C. Whelan, T. Mikolajick. – Berlin, Springer Verlag 

(2005)

Eingeladene Vorträge 

Invited Presentations 

(1) Atomic-Scale Properties of High-k Dielectric 

for CMOS: ab-initio Study of Pr-based 

Materials 

J. Dabrowski, A. Fleszar 

69. Annual Meeting of the DPG, Berlin, March 

04-09, 2005, Germany 

(2) Pseudopotential Studies of Pr Oxides: Electronic 

Properties, Native Defects and Impurities 


ESF Exploratory Workshop on: Rare Earth Oxide 

Thin Films: Growth, Characterization and Applications, 

San Remo, May 11-13, 2005, Italy 

(3) On Emerging Automotive Safety by Sensorbased 

Assistance Technology 

J. deMeer 

Berlin – Prague – Vienna - European Competence 

and Vision for Future Transport Technologies 

– Workshop on Automotive Technologies, 

Brussels, September 22, 2005, Belgium 

(4) Berichterstattung aus NI27b IT Sicherheitstechnologie 

J. deMeer 

DIN Normenausschuß Informationstechnik NI27 

– IT Sicherheitstechnologien und NI37 – Biometrie 

und Sicherheit, Frankfurt (Oder), Septem- 

ber 15-16, 2005, Germany 

(5) On Automotive Safety Related to IST 7 th 

Framework Programme 

J. deMeer 

TSB - Arbeitskreis Verkehrstelematik & Logistik, 

Berlin, May 11, 2005, Germany 

(6) Körpernahe Funknetze zur Fernüberwachung 

des Gesundheitszustandes von Patienten 

J.-P. Ebert, D. Dietterle 

14. Sommertagung der Berliner Chirurgischen 

Gesellschaft, September 01, 2005, Frankfurt 

(Oder) 

Eingeladene Vorträge Invited Presentations 

(7) SiGe:C BiCMOS-Technologie für 77-81 GHz 

Radarsysteme im Automobilbau 

G.G. Fischer 

MicroCar 2005, Leipzig, June 22, 2005, Germany 

(8) Electron Holography in Si Research 


2 nd Sino-German Symposium “The Silicon Age”, 

Cottbus, September 22, 2005, Germany 

(9) European Research Institutes of Excellence 

H.G. Grimmeiss, W. Mehr 

University Madrid, October 2005, Spain 

(10) Defects in Large Diameter CZ Silicon 

G. Kissinger 



(11) Silicon-Based Light Emission after Ion Implantation: 

Role of Defects and of Crystalline 

Perfection 

M. Kittler 

CNR-IMM Bologna, February 2, 2005, Italy 

(12) Self Organized Pattern Formation of Biomolecules 

at Si Surfaces 

M. Kittler, X. Yu, O.F. Vyvenko, M. Birkholz, W. Seifert, 

M. Reiche, T. Wilhelm, T. Arguirov, A. Wolff, 

W. Fritzsche, M. Seibt 

E-MRS Spring Meeting, Strasbourg, May 31 – 

June 03, 2005, France 

(13) Location Based Services and Requirements 

on Positioning and Communication 

R. Kraemer 

Workshop on Positioning, Navigation and Communication 

2005 (WPNC‘05), Hanover, March 17, 

2005, Germany 

(14) Am Anfang gab es nur eine Idee 

R. Kraemer 

Workshop Science2Market-Tag, Frankfurt (Oder), 

November 02, 2005, Germany 

(15) From RFID to Flexible Sensor Networks, 

Models, Concepts, and Architectures 

R. Kraemer 

International Workshop on Radio Frequency Identification 

(RFID) and Wireless Sensors, Kanpur, 

November 11-13, 2005, India 


Eingeladene Vorträge Invited Presentations 

(16) A Highly Integrated Gbit Communication 

System in the 60 GHz Band 

R. Kraemer 

15 th Meeting of the WWRF, Paris, December 

08-09, 2005, France 

(17) IHP – Europäisches Forschungs- und Innovationszentrum 

für drahtlose Kommunikation 

W. Mehr 

Technologietag „Halbleiterelektronik und Informationstechnologie 

in Mitteldeutschland“, Berlin, 

June 15, 2005, Germany 

(18) SiGe-Technologien für Schaltkreise und Systeme 

der drahtlosen Kommunikation 

W. Mehr 

Forschungsseminar, TFH Wildau, December 2005, 

Germany 

(19) IHP – Auf dem Weg zum europäischen Innovationszentrum 

W. Mehr 

Workshop Science2Market-Tag, Frankfurt (Oder), 

November 02, 2005, Germany 

(20) SiGe HBT Integration in CMOS for Radio Frequency 

Applications 

W. Mehr, B. Tillack, D. Knoll, B. Heinemann, 

H. Rücker 



(21) Solid Phase Reaction Growth of Rare Earth 

Oxides 

H.-J. Müssig 

ESF Exploratory Workshop on: Rare Earth Oxide 

Thin Films: Growth, Characterization and Applications, 

San Remo, May 11-13, 2005, Italy 

(22) Dielectrics for Future Si-based Device Technology 

T. Schröder 

International Max-Planck Research Summer School 

Interfaces of Oxides, Stuttgart, August 4-8, 2005, 

Germany 

(23) Preparation and Properties of Heteroepitaxial 

Praseodymium Oxide Films on Si(001) 

and Si(111): Basic Research for Industrial 

Applications 

144 


T. Schröder, P. Zaumseil, C. Wenger, G. Lippert, 

G. Lupina, H.-J. Müssig 

Materialwissenschaftliches Seminar, Bremen, 

February 10, 2005, Germany 

(24) Si-basierte Photovoltaik: Gegenwart und 

Zukunftsperspektiven 

W. Seifert, M. Kittler 

Innovationstag Energie 2005, BTU Cottbus, 

June 01-02, 2005, Germany 

(25) Atomically Controlled Processing for Si and 

SiGe Micro- and Nanotechnology 

B. Tillack, Y. Yamamoto, B. Heinemann, H. Rücker, 

D. Knoll, J. Murota 

Nanoscience 2005, Lichtenwalde, October 05-08, 


(26) Atomic Layer Processing for Doping of SiGe 

B. Tillack, Y. Yamamoto, D. Bolze, B. Heinemann, 

H. Rücker, J. Murota, W. Mehr 

1 st International Workshop on New Group IV 

Semiconductor Nanoelectronics, Sendai, May 27- 

28, 2005, Japan 

(27) Atomic Control of SiGe Epitaxy and Doping 

B. Tillack, Y. Yamamoto, K.-D. Bolze, H. Rücker, 

B. Heinemann, D. Knoll, D. Wolansky, J. Murota, 

W. Mehr 

4 th International Conference on Silicon Epitaxy and 

Heterostructures, Awaji Island, Hyogo, May 23-26, 

2005, Japan 

(28) 60 GHz Circuits in SiGe HBT Technology 

W. Winkler 

Compound Semiconductor IC Symposium 

(CSICS), Palm Springs, October 30, 2005, USA 

(29) Millimeter-Wave Integrated Circuits in SiGe: 

C BiCMOS Technology 

W. Winkler 

MWE 2005, Microwave Workshop and Exhibition 

2005, Yokohama, November 09-11, 2005, 

Japan 

(30) Impacts on Contact Resistance for 0.25 µm 

AI-BEOL 

D. Wolansky 

Applied Materials PVD & MOCVD User Workshop, 

Dresden, May 11, 2005, Germany

Vorträge 

Presentations 

(1) FTIR Study of Precipitation of Implanted Nitrogen 

in CZ-Si Annealed under High Hydrostatic 

Pressure 

V.D. Akhmetov , A. Misiuk, H. Richter 

11 th GADEST Conference, Giens, September 25-30, 

2005, France 

(2) FTIR Spectroscopic System with Improved 

Sensitivity 

V.D. Akhmetov, H. Richter 

DRIP XI, Beijing, September 15-19, 2005, China 

(3) Pressure – Induced Transformations of Nitrogen 

Implanted into Silicon 

V.D. Akhmetov, A. Misiuk, A. Barcz, H. Richter 



(4) Application of Photoluminescence for Silicon 

Materials Research 

T. Arguirov, M. Kittler, W. Seifert, X. Yu, M. Reiche 



(5) Untersuchungen am Wacker-Granalien-Block 

mit EBIC, DLTS und PL 

T. Arguirov, G. Jia, W. Seifert, M. Kittler 

Arbeitstreffen ASIS-Verbundprojekt, Ochsenfurt, 

March 2005, Germany 

(6) Silicon-based Light Emission Devices 

T. Arguirov, M. Kittler, W. Seifert, X. Yu 



(7) Spatially and Spectrally Resolved Photoluminescence 

for Characterization of Multicrystalline 

Silicon 

T. Arguirov, W. Seifert, G. Jia, M. Kittler 

Arbeitstreffen ASIS-Verbundprojekt, Ochsenfurt, 

March 2005, Germany 


Lithography Application 

J. Bauer, O. Fursenko, S. Virko, T. Grabolla, 

B. Kuck, V. Melnik, W. Mehr 

Vorträge Presentations 

21. European Mask and Lithography Conference 

EMLC, Dresden, January 31 - February 03, 2005, 

Germany 

(9) Swing Curves: High NA Effect and Determination 

of Optical Constants 

J. Bauer, U. Haak, A Woroniecki, M. Szuggars 

TEL Process Seminar, Dresden, June 03, 2005, 

Germany 

(10) Technologische Anwendungen von Excimer- 

und CO 2 -Impulslasern 

H. Beyer, W. Roß, P. Schmidt 

Laser in der Feinbearbeitung, Laserverbund Berlin-Brandenburg, 

Teltow, October 22, 2005, Germany 

(11) Untersuchung zur Immobilisierung von Biomolekülen 

auf Halbleiteroberflächen mit der 

Methode der Röntgenreflektometrie 

M. Birkholz 

Joint Lab der Brandenburgisch-Technischen Universität 

Cottbus, June 28, 2005, Germany 

(12) Perspektiven zur Untersuchung von Biomaterialien 

durch Immobilisierung auf CMOS/ 

BiCMOS-Höchstfrequenz-Bauteilen 

M. Birkholz 

Fachbereich Physik der Freien Universität Berlin, 


(13) A Low-Power, 10 Gs/s Track-and-Hold Amplifier 

in SiGe BiCMOS Technology 

Y. Borokhovych, H. Gustat, B. Tillack, Y. Lu, 

B. Heinemann, W.-M. Lance Kuo, X. Li, R. Krithivasan, 

J.D. Cressler 

ESSCIRC 2005, Grenoble, September 12-16, 


(14) ADS RFDE Simulation: An Overview 

P.K. Datta 

4 th Workshop High-Performance SiGe:C BiCMOS 

for Wireless, Tutorial, Frankfurt (Oder), September 


(15) EUSAT – On Automotive Safety Technology – 

A Derived WINcell Middleware Application 

J. deMeer 

Galileo Anwendungszentrum Berlin-Brandenburg – 

Technologiestiftung Berlin, July 25, 2005, Germany 



(16) Berichterstattung aus EU EUSAT Project 

Preparation 

J. deMeer 

Technologiestiftung Innovationszentrum Berlin 

(TSB) 

Workshop on Berlin-Prag-Wien-European Competence 

and Vision for Future Transport Technologies 

to IST, 7 th Framework Programme, Berlin, 

July 28, 2005, Germany 

(17) Berichterstattung vom QoS-MW Workshop 

J. deMeer 

IWQoS - Quality of Service Workshop 2005, Passau, 


(18) Feature Demonstration of PLASMA – the IHP 

Mobile Business Platform 

J. deMeer 

IWQoS - Quality of Service Workshop 2005, Passau, 


(19) WINcell Projektberichterstattung 

J. deMeer 

Meeting of BMBF Wachstumskern XML: City to 

the Topic: Plattform für Intelligente Kollaborationsportale 

PINK EADS Berlin, June 07, 2005, 

Germany 

(20) Berichterstattung vom GI Middlewareforum 

J. deMeer 

Coordination Meeting of National GI Regional 

Group Chairs 

Technical University of Brandenburg, Cottbus, 


(21) Electronic Assistance for Automation Processing 

– Advances 

J. deMeer 

EU STREP RESIDUAL 2 nd Project Preparation 

Meeting, Berlin, May 03-04, 2005, Germany 

(22) Digital Rights Management 

J. deMeer 

4 th (Spring) Workshop of GI Regionalgruppe Berlin, 

Schutzrechte für Inhalte und Software, TU 

Berlin, April 12, 2005, Germany 

(23) Electronic Assistance for Automation Processing 

– Foundations 

J. deMeer 

146 


EU STREP RESIDUAL 1 st Project Preparation Meeting, 

due to FP6-2002-IST-C, Berlin, January 31 - 

February 02, 2005, Germany 

(24) Berichterstattung aus Normungsprojekten 

J. deMeer 

Regular Meeting DIN NI17.3 on Maschinenlesbare 

Reisedokumente, Berlin, February 08, 


(25) Interdisziplinäre Entwicklung Interaktiver 

Mobiler Sensorsysteme 

J. deMeer 

Graduiertenkolleg der TU Berlin, 2005, Germany 

(26) BASUMA – Body Area System for Ubiquitous 

Multimedia Application 

J.-P. Ebert, D. Dietterle 

Treffen des Vereins Brandenburgischer Ingenieure 

und Wirtschaftler, June 02, 2005, Frankfurt (O.) 

(27) Potential and Limitation of Electron Holography 

in Si Research 




(28) Measurement Errors in Phase Images due to 

Noise and Limited Resolution 

P. Formanek 

Microscopy Conference, Davos, August 28 – 

September 02, 2005, Switzerland 

(29) Technology Monitoring for Quality Assurance 

T. Grabolla, P. Schley 


for Wireless, Frankfurt (Oder), September 21, 


(30) Asynchronous Circuit Design Techniques: An 

Overview 

E. Grass 

GALS Workshop, Humboldt Universität zu Berlin, 

January 21, 2005, Germany 

(31) Implementation Aspects of Gbit/s Communication 

Systems in the 60 GHz Band 

E. Grass, F. Herzel, M. Piz, Y. Sun, R. Kraemer 

Wireless World Research Forum (WWRF) / WG5, 

San Diego, July 07-08, 2005, USA

(32) Enhanced GALS Techniques for Datapath Applications 

E. Grass, F. Winkler, M. Krstic, A. Julius, C. Stahl, 

M. Piz 

PATMOS 2005, Leuven, September 20-23, 2005, 

Belgium 

(33) Draft PHY Proposal for 60 GHz WPAN 

E. Grass, M. Piz, F. Herzel, R. Kraemer 

IEEE 802.15 Meeting, Vancouver, November 2005, 

Canada 

(34) Components for High-speed A/D Converters 

H. Gustat 




(35) NOR/OR Register Based ECL Circuits for 

Maximum Data Rate 

H. Gustat, J. Borngräber 

2005 IEEE Bipolar/BiCMOS Circuits and Technology 

(BCTM 2005), Santa Barbara, October 10-11, 

2005, USA 

(36) System-Level Simulation of a Noisy Phase- 

Locked Loop 

F. Herzel, M. Piz 

35 th European Microwave Conference 2005, Paris, 

October 03-04, 2005, France 

(37) 60 GHz Transceiver Components 

F. Herzel, M. Piz 




(38) Frequency Synthesis for 60 GHz OFDM Systems 

F. Herzel, M. Piz, E. Grass 

10 th International OFDM Workshop, Hamburg, 

August 31 - September 1, 2005, Germany 

(39) Annealing Behavior of New Nitrogen Infrared 

Absorption Peaks in Cz Silicon 

H. Inoue, M. Nakatsu, K. Tanahashi, H. Yamada- 

Kaneta, H. Ono, V.D. Akhmetov, O. Lysytskiy, 

H. Richter 




(40) As-grown Defects in Germanium Studied by 

Brewster Angle LST and Etching 

G. Kissinger 

2 nd CADRES Germanium Workshop, Brussels, 

December 12, 2005, Belgium 

(41) Oxygen Precipitation in Nitrogen Doped Silicon 

G. Kissinger, T. Müller, A. Sattler, U. Lambert, 

W. Häckl, M. Weber, A. Huber, P. Krottenthaler, 

H. Richter, W. von Ammon 



(42) A Contribution to Oxide Precipitate Nucleation 

in Nitrogen Doped Silicon 

G. Kissinger, U. Lambert, M. Weber, F. Bittersberger, 

T. Müller, H. Richter, W. von Ammon 

Oxford Meeting on Nitrogen in Silicon, December 

08, 2005, UK 

(43) Future Silicon Wafers 

G. Kissinger 

Siltronic AG, Burghausen, December 16, 2005, 

Germany 

(44) Combination of Optical Measurements and 

Precipitation Theory to Overcome the Obstacles 

of Detection Limits 

G. Kissinger, T. Müller, A. Sattler, W. Häckl, P. Krottenthaler, 

T. Grabolla, H. Richter, W. von Ammon 


(45) Si Based Light Emitters 

M. Kittler 



(46) Dependence of Electrical and Optical Properties 

of Si on Defects and Impurities 

M. Kittler 

SiWEDS Fall Meeting, Seoul, October 13-14, 2005, 

Korea 

(47) Dislocation Engineering for a Silicon-Based 

Light Emitter at 1.5 µm 

M. Kittler, M. Reiche, T. Arguirov, W. Seifert, X. Yu 

International Electron Devices Meeting (IEDM 

2005), Washington, December 05-12, 2005, 

USA 



(48) Si-Based Light Emission after Ion Implantation 

M. Kittler, T. Arguirov, A. Fischer, W. Seifert, X. Yu 

3 rd Optoelectronic and Photonic Winter School 

Optical Interconnects, Trento, February 27 – 

March 04, 2005, Italy 

(49) Silicon Based Light Emitters for On-Chip 

Optical Interconnects 

M. Kittler, T. Arguirov, W. Seifert, X. Yu, M. Reiche 



(50) Arbeitsergebnisse des IHP und IHP/BTU 

Joint Lab zum ASiS-Projekt 

M. Kittler, W. Seifert, T. Arguirov, G. Jia, Q. Wie, 

O. Vyvenko 

Arbeitstreffen ASiS-Verbundprojekt, Ochsenfurt, 

September 2005, Germany 

(51) Regular Dislocation Networks in Si as a Tool 

for Nanostructure Devices 

M. Kittler, X. Yu et al. 

Optics East, SPIE-Symposium 6003, Boston, October 

23-26, 2005, USA 

(52) SiGe:C BiCMOS Technology Development for 

High Speed and Low Cost Applications 

D. Knoll 

Philips Research Leuven, June 29, 2005, Belgium 

(53) IHP‘s 0.25 µm BiCMOS Technologies 

D. Knoll 




(54) A Low-Cost SiGe:C BiCMOS Technology with 

Embedded Flash Memory and Complementary 

LDMOS Module 

D. Knoll, A. Fox, K.-E. Ehwald, B. Heinemann, R. 

Barth, A. Fischer, H. Rücker, P. Schley, R. Scholz, 

F. Korndörfer, B. Senapati, V.E. Stikanov, B. Tillack, 

W. Winkler, Ch. Wolf, P. Zaumseil 




148 


(55) Integrating Mobile Devices into E-business 

Architectures: Open Issues and Potential 

Solutions 

R. Kraemer, P. Langendörfer 

DECUS IT-Symposium 2005, Neuss, April 05, 


(56) Wireless Engines: Ein vertikales Verfahren 

zur Entwicklung neuer drahtloser Kommunikationssysteme 

R. Kraemer 

University of Paderborn, June 07, 2005, Germany 

(57) GALS Technique for Wireless Communication 

Systems 

M. Krstic 

GALS Workshop, Humboldt Universität zu Berlin, 

January 21, 2005, Germany 

(58) BIST Testing for GALS Systems 

M. Krstic, E. Grass 

8 th EUROMICRO Conference on Digital System 

Design – Architecture, Methods and Tools (DSD 

2005), Porto, August 30- September 03, 2005, 

Portugal 

(59) Request-driven GALS Technique for Wireless 

Communication System 

M. Krstic, E. Grass, C. Stahl 

IEEE International Symposium on Asynchronous 

Circuits and Systems (ASYNC) 2005, New York, 

March 14-16, 2005, USA 

(60) Schutz der Privatsphäre im mobilen Internet: 

Ein Systemansatz 


TU Braunschweig, October 04, 2005, Germany 

(61) Low Power Security Means: Key to Privacy 

in Context-aware Systems 


Florida International University, Miami, 2005, 

USA 

(62) Schutz der Privatsphäre im Wireless Internet 


Marie-Curie-Gymnasium Wittenberge, November 

04, 2005, Germany

(63) Privacy and Convenient Up Time of Mobile 

Devices: An Antagonism? 


Research Trends in Science and Technology 

(RTST 2005), Beirut, March 07, 2005, Lebanon 

(64) More Privacy in Context-aware Platforms: 

User Controlled Access Right Delegation 

Using Kerberos 

P. Langendörfer, K. Piotrowski 

4 th WSEAS International Conference on Information 

Security, Communications and Computers (ISCO- 

CO 2005), Puerto De La Cruz, December 16-18, 

2005, Spain 


P. Langendörfer, K. Piotrowski, M. Maaser 

4 th International Conference on Mobile Business 

(ICMB 2005), Sydney, July 11-13, 2005, Australia 

(66) Implementation Independent Profiling of 

SDL Specifications 

P. Langendörfer, M. Lehmann 

Software Engineering, Essen, March 08-11, 




Applying Karatsuba‘s Method 

P. Langendörfer, Z. Dyka 

Design Automation and Test 2005 (DATE 2005), 

München, March 07-11, 2005, Germany 






E-MRS Spring Meeting 2005, Strasbourg, May 31 

– June 03, 2005, France 






18. Treffen der Nutzergruppe RTP, Reutte, November 

10, 2005, Austria 


(70) Is the IEEE 802.11 MAC Layer Suitable for 

Car-to-Car Communication? 

W. Lohmann, J.-P. Ebert, M. Grade, A. Lübke, 

R. Kraemer 

1 st Workshop on Wireless Vehicular Communications 

and Services for Breakdown Support and 

Car Maintenance (W-CarsCare‘05), Nicosia, April 

10, 2005, Cyprus 

(71) A 8-bit, 12 GSample/sec SiGe Track-and- 

Hold Amplifier 

Y. Lu, W.-M. L. Kuo, X. Li, R. Krithivasan, J.D. 

Cressler, Y. Borokhovych, H. Gustat, B. Tillack, 

B. Heinemann 




(72) Titanium Added Praseodymium Silicate Layers 

on Si(001) for High-k Dielectrics Applications 

G. Lupina, J. Dabrowski, T. Schröder, C. Wenger, 

G. Lippert, A. Mane, R. Sorge, G. Weidner, H.-J. 

Müssig, D. Schmeißer 

69. Annual Meeting of the DPG, Berlin, March 


(73) Praseodymium Silicate Layers for High-k Dielectric 

Applications – Physical and Electrical 

Characterization 

G. Lupina, T. Schröder, J. Dabrowski, C. Wenger, 

A. Mane, G. Lippert, H.-J. Müssig 

MIGAS International Summer School on Advanced 

Microelectronics, Autrans, June 11-17, 


(74) Automated Negotiation of Privacy Contracts 

M. Maaser, P. Langendörfer 

The 29 th Annual International Computer Software 

and Applications Conference, Edinburgh, 

July 25-28, 2005, UK 

(75) An Efficient Strategy of Processing Distributed 

Location Based Events 

O. Maye 

IEEE International Conference on Pervasive 

Services 2005 (ICPS‘05), Santorini, July 11-14, 

2005, Greece 



(76) Formation and Properties of Iron-Phosphorus 

and Iron-Phosphorus-Hydrogen Complexies 

in Silicon 

T. Mchedlidze 



(77) Novel Si Technologies – New Defects. How 

to Study them with Traditional Methods? 

T. Mchedlize 

Technical University of Brandenburg, Cottbus, 

April 05, 2005, Germany 

(78) Spin Resonance Related to Defects in Silicon: 

New Defects and New Technique 

T. Mchedlize 

Hahn-Meitner-Institute, Berlin, July 06, 2005, 

Germany 

(79) SiGe Technology for Radio Frequency Applications 

W. Mehr 

German-Russian Workshop on SiGe BiCMOS Technologies 

and Circuits, Moscow, November 24, 

2005, Russia 

(80) The Impact of Channel Engineering on the 

Performance and Reliability of LDMOS Transistors 

N.R. Mohapatra, K.-E. Ehwald, R. Barth, H. Rücker, 

D. Bolze, P. Schley, D. Schmidt, H.-E. Wulf 

ESSDERC 2005, Grenoble, September 12-16, 


(81) Precipitation Enhancement of so Called Defect-Free 

Czochralski Silicon Material 

T. Müller, G. Kissinger, P. Krottenthaler, C. Seuring, 

R. Wahlich, W. von Ammon 



(82) Atomically Controlled CVD Technology for 

Future Si-based Devices 

J. Murota, M. Sakuraba, B. Tillack 

207 th Electrochemical Society Meeting, Quebec, 

May 15-20, 2005, Canada 

150 


(83) Design of Wireless Systems Utilizing 

Scratchpad Memories 

G. Panic, Z. Stamenkovic, K. Tittelbach-Helmrich, 

J. Lehmann, G. Schoof 

IP Based SoC Design (IP-SOC 2005), Grenoble, 

December 07-08, 2005, France 

(84) Effect of Fluorine on the Activation and 

Diffusion Behaviour of Boron Implanted 

Preamorphized Silicon 

S. Paul, W. Lerch, B. Colombeau, N.E.B Covern, 

F. Christiano, S. Boninelli, D. Bolze 

18. Treffen der Nutzergruppe RTP, Reutte, November 

10, 2005, Austria 

(85) Effect of Flourine on the Activation and Diffusion 

Behaviour of Preamorphized Silicon 

S. Paul, W. Lerch, B. Colombeau, N.E.B Covern, 

F. Christiano, S. Boninelli, D. Bolze 

The 8 th International Workshop on the Fabrication, 

Characterization and Modeling of Ultra Shallow 

Junctions in Semiconductors, Daytona Beach, 

June 5-8, 2005, USA 


K. Piotrowski, P. Langendörfer, M. Maaser, 

G. Spichal, P. Schwander 

4 th International Workshop on Wireless Information 

Systems (WIS-2005), Miami, May 24-28, 


(87) Si/SiGe Double Barrier Resonant Tunneling 

Diode 

P. Racec, U. Wulf, G. Kissinger, H. Richter 

Nanoscience 2005, Lichtenwalde, October 06-08, 


(88) Silicon Wafer Bonding Using Deposited and 

Thermal Oxide: A Comparative Study 

I. Radu, R. Singh, M. Reiche, B. Kuck, T. Grabolla, 

U. Gösele, B. Tillack, S. Christiansen 


May 15-20, 2005, Canada 

(89) Silicon Wafer Bonding Using Various Oxide 

Layers: PE TEOS Versus Thermal Oxide 

I. Radu, R. Singh, S. Christiansen, M. Reiche, 

U. Gösele, B. Kuck, T. Grabolla, B. Tillack 


May 15-20, 2005, Canada

(90) Plasma Etching of Carbon Hard Mask Stacks 

for Sub-100 nm Technologies 

H.H. Richter, K.A. Pears, M. Markert, S. Günther, 

S. Marschmeyer, H. Silz, G. Weidner, H. Kirmse, 

W. Neumann 

12. Bundesdeutsche Fachtagung Plasmatechnologie, 

Braunschweig, March 21-23, 2005, Germany 

(91) 0.13 µm BiCMOS Development 

H. Rücker 




(92) SiGe BiCMOS Technology 

H. Rücker 




(93) Circuit Design in SiGe BiCMOS Technology 

K. Schmalz 




(94) A Class AB 6 th Order Log-Domain Filter in 

BiCMOS with 100-500 MHz Tuning Range 

K. Schmalz, M.A. Teplechuk, J.I. Sewell 

2005 European Conference on Circuit Theory 

and Design (ECCTD 2005), Cork, August 29 – 

September 01, 2005, Ireland 

(95) MPW and Prototyping Service 

R.F. Scholz 




(96) MPW and Foundry Service 

R.F. Scholz 

German-Russian Workshop on SiGe BiCMOS 

Technologies and Circuits, Moscow, November 

24, 2005, Russia 

(97) Materialien für die Mikroelektronik – auf 

Entdeckungsreise im Nanokosmos 

T. Schröder 

Tag der offenen Tür, IHP Frankfurt (Oder), September 

03, 2005, Germany 


(98) Von der Mikro- zur Nanoelektronik: Eine 

Herausforderung an moderne Materialien 

T. Schröder 

Verein Brandenburgischer Ingenieure und Wirtschaftler 

e.V. und des Elektrotechnischen Vereins 

e.V. Frankfurt (Oder), October 13, 2005, 

Germany 

(99) Lattice Matching Approaches for High Quality 

S-I-S Structures 

T. Schröder 

Physikalisches Kolloquium der BTU Cottbus, November 

15, 2005, Germany 

(100) Epitaxial Silicon/Praseodymium Oxide/Silicon 

Heterostructures: Lattice Matching Approaches 

for Alternative SOI Structures 

T. Schröder, H.-J. Müssig 

Project Meeting Siltronic AG Burghausen, June 


(101) Heteroepitaxial Silicon/Pr 2 O 3 /Silicon Sandwich 

Structures for Nanoelectronics Applications 

T. Schröder, P. Zaumseil, C. Wenger, G. Lippert, 

G. Lupina, H.-J. Müssig, L. Libralesso, J. Zegenhagen 

DPG Frühjahrstagung, Berlin, March 04-09, 


(102) Growth, Structure and Electric Properties 

of Epitaxial Si/Pr 2 O/Si 3 (111) Heterostructures 

T. Schröder, P. Zaumseil, G. Weidner, C. Wenger, 

G. Lippert, A. Mane, J. Dabrowski, H.-J. Müssig 



(103) Modern X-Ray Diffraction Techniques for 

Technology Relevant Materials Systems: The 

Example of Ultra-Thin Praseodymium Oxide 

Layers on Silicon for Nanoelectronics Applications 

T. Schröder, P. Zaumseil 

Berlin-Brandenburg Workshop High-Resolution 

X-Ray Scattering Techniques for Nanostructured 

Materials, Potsdam, February 04, 2005, Germany 



(104) Hazard Detection in GALS Wrapper: A Case 

Study 

C. Stahl, W. Reisig, M. Krstic 

5 th Int. Conf. on Application of Currency to System 

Design (ACSD 2005), St. Malo, June 06-09, 


(105) ADS Stand Alone Design Kit 

Y. Sun 


for Wireless, Tutorial, Frankfurt (Oder), September 


(106) A Fully Integrated 60 GHz LNA in SiGe:C 


Y. Sun, J. Borngräber, F. Herzel, W. Winkler 


(BCTM 2005), Santa Barbara, Octo- 

ber 10-11, 2005, USA 

(107) IHP Technology Development – Status and 

Overview 

B. Tillack 

Philips Research Leuven, June 28, 2005, Belgium 

(108) High-Performance SiGe:C BiCMOS for Wireless 

and Broadband Communication: Technology, 

MPW and Prototyping, Applications: 

Introduction 

B. Tillack 




(109) Impact of Low Temperature Hydrogenation 

on Recombination Activity of Dislocations 

in Silicon 

O.F. Vyvenko, M. Kittler, W. Seifert 

11 th GADEST Conference 2005, Giens, September 

25-30, 2005, France 

(110) Low-Complexity Initialization of Adaptive 


G. Wang, R. Kraemer 

5 th IEEE International Symposium on Signal 

Processing and Information Technology (IEEE 

ISSPIT 2005), Athens, December 18-21, 2005, 

Greece 

152 


(111) Low-Power 71 GHz Static Frequency Divider 

in SiGe:C HBT Technology 

L. Wang, J. Borngräber, G. Wang, Z. Gu, A. Thiede 

IEEE MTT-S 2005, International Microwave Symposium, 

Long Beach, June 12-17, 2005, USA 

(112) High Performance PrTiO 3-x MIM Capacitors 

for RF Applications 

C. Wenger, R. Sorge, A. Mane, T. Schröder, 

G. Lippert, H.-J. Müssig 

DPG Frühjahrstagung, Berlin, March 04-09, 


(113) MIM Capacitors Using Amorphous High-k 

PrTi x O y Dielectrics 

C. Wenger, R. Sorge, T. Schröder, A.U. Mane, 

G. Lippert, G. Lupina, J. Dabrowski, P. Zaumseil, 

H.-J. Müssig 

INFOS 2005, Leuven, June 22-24, 2005, Belgium 

(114) Radar Circuits 

W. Winkler 




(115) Millimeter-Wave Integrated Circuits in SiGe 


W. Winkler 

German-Russian Workshop on SiGe BiCMOS 

Technologies and Circuits, Moscow, Novem- 

ber 24, 2005, Russia 

(116) A Fully Integrated BiCMOS PLL for 60 GHz 


W. Winkler, J. Borngräber, B. Heinemann, F. Herzel 

International Solid State Circuits Conference 

(ISSCC 2005), San Francisco, February 06-10, 


(117) Chemical Vapor Phase Etching of Polycrystalline 

Selective to Epitaxial SiGe 

Y. Yamamoto, B. Tillack, K. Köpke, O. Fursenko 



2005, Japan

(118) P Doping Control During SiGe:C Epitaxy 

Y. Yamamoto, B. Tillack, K. Köpke, R. Kurps 



2005, Japan 

(119) Silicon Light Emitting Diodes Prepared by 

Ion Implantation 

Y. Yeromenko, T. Arguirov, M. Kittler, W. Seifert, 

J. Reif 

69. Jahrestagung der DPG-Halbleiterphysik, Berlin, 

March 04-09, Germany 

(120) Properties of Dislocation Networks Formed 

by Si Wafer Direct Bonding 

X. Yu, T. Arguirov, M. Kittler, W. Seifert, M. Ratzke, 

M. Reiche 


(121) Tutorial: High Resolution X-Ray Diffraction 

P. Zaumseil 

6 th Autumn School on X-Ray Scattering from Surfaces 

and Thin Layers, Smolenice, September 

18, 2005, Slovakia 

(122) Structural Characterization of Epitaxial 

Si/Pr 2 O 3 /Si(111) Heterostructures 

P. Zaumseil, T. Schröder, G. Weidner 



Berichte 

Reports 

(1) Spatially and Spectrally Resolved Photoluminescence 

for Characterization of Multicrystalline 

Silicon 

T. Arguirov, W. Seifert, G. Jia, M. Kittler 

Progress Report, Project ASIS, March 2005 

(2) Untersuchungen am Wacker-Granalien-Block 

mit EBIC, DLTS und PL 

T. Arguirov, G. Jia, W. Seifert, M. Kittler 

Progress Report, Project ASIS, September 2005 

Berichte Reports 

(3) Ab inito Investigation of Pr-Related Dielectrics 

for CMOS Technology 

J. Dabrowski 

Progress Report, NIC project hfo06, Neumann 

Institute for Computing (NIC), 2005 

(4) Ab Initio Investigation of High-k Dielectrics 

for CMOS Technology Development 


Progress Report and Application for Project 

Extension, Neumann Institute for Computing, 

2005 

(5) Tragfähige Architekturenprinzipien 

C. Deist, P. Langendörfer 

Project: Wireless Internet Zellular, 2005 

(6) Spezifikation der Anwendung (final) 

C. Deist, P. Langendörfer 

Project: Wireless Internet Zellular, 2005 

(7) BASUMA Teilvorhaben, Gesamtarchitektur, 

Protokollstapel und Digitalteil der IMC 

J.-P. Ebert 

BASUMA Project, Progress Report January 01 – 

June 30, 2005 

(8) Präsentation der IHP-Technologie und des 

Projektstatus 

G.G. Fischer 

IHP – Infineon Kokon Project-Meeting Septem- 

ber 20, 2005 

(9) A VCO with Output Buffer for 77 GHz Automotive 

Radar 

S. Glisic 

IHP – Infineon Kokon Project, 2005 

(10) Intermediate Report 

G. Kissinger 

Project IHP – Siltronic AG, May 2005 

(11) Final Report 

G. Kissinger 

Project IHP – Siltronic AG, December 2005 

(12) Evaluation of the Feasibility of Flow Pattern 

Defect Etching of Germanium 

G. Kissinger 

Cooperation with Umicore, October 25, 2005 


Berichte Reports 

(13) Arbeitsergebnisse des IHP und IHP/BTU 

JointLab zum ASIS-Projekt 

M. Kittler, W. Seifert, T., Arguirov, G. Jia, Q. Wei, 

O. Vyvenko 

Progress Report, Project ASIS, September 2005 

(14) Middleware Spezifikation (final) 

P. Langendörfer et al. 

Project Wireless Internet Zellular, 2005 

(15) Abschlußbericht Feldtest, Empfehlungen 

B. Lehmann, P. Langendörfer 

Project Wireless Internet Zellular, 2005 

(16) Pr 2 O 3 -added Al 2 O 3 Dielectrics for Future 

DRAM Technologies 

G. Lippert, H.-J. Müssig 

Zwischenbericht an Infineon zur Machbarkeitsstudie, 

October 2005 

(17) Zwischenbericht 1. Halbjahr 2005 

H. Maass, P. Langendörfer 

Wireless Internet ad hoc, 2005 

(18) Research Report on Power Consumption, Deliverable 

D3.3.4 

M. Methfessel, F.-M. Krause, K. Tittelbach-Helmrich 

EU-Project WINDECT, No. STP 506 746, February 


(19) Firmware for WLAN Chipset, Deliverable D5.3 

M. Methfessel, K. Tittelbach-Helmrich 

EU-Project WINDECT, No. STP 506 746, March 


(20) Strukturelle und elektrische Eigenschaften 

heteroepitaktischer Si/Pr 2 O 3 /Si(111) Schichtsysteme 

T. Schröder 

Zwischenbericht an Siltronic zur Machbarkeitsstudie, 

March 2005 

(21) Bewertung heteroepitaktischer Si/Pr 2 O 3 / 

Si(111) – Schichtsysteme alternative SOI- 

Strukturen 

T. Schröder 

Abschlussbericht zur Machbarkeitsstudie für Siltronic, 

November 25, 2005 

154 


(22) Strukturelle und elektrische Eigenschaften 

heteroepitaktischer Si/Pr 2 O 3 /Si(111) Schichtsysteme 

T. Schröder 

Abschlußbericht zur Machbarkeitsstudie für Siltronic, 

November 2005 

(23) Integration and Test Plan for Data Phase, 

Deliverable D6.1 

K. Tittelbach-Helmrich, A. Ettefagh 

EU-Project WINDECT, No. STP 506 746, June 


(24) Test Report for WLAN Telephone Terminals 

Chipset, Deliverable D4.2 

K. Tittelbach-Helmrich, M. Krstic, N. Fiebig, 

M. Methfessel 

EU-Project WINDECT, No. STP 506 746, May 


(25) Test Report for WLAN Access Point Chipset, 

Deliverable D5.2 

K. Tittelbach-Helmrich, M. Krstic, N. Fiebig, 

M. Methfessel 

EU-Project WINDECT, No. STP 506 746, May 


(26) Driver for WLAN Chipset, Deliverable D4.3 

K. Tittelbach-Helmrich, M. Zessack, M. Methfessel 

EU-Project WINDECT, No. STP 506 746, March 

2005

Monographien 

Monographs 

(1) Thin Film Analysis by X-Ray Scattering 

M. Birkholz with contribution by P. F. Fewster 

and C. Genzel 

Weinheim, Wiley-VCH (2005) 

(2) Gettering and Defect Engineering in Semiconductor 

Technology XI, GADEST 2005 

Ed.: B. Pichaud, A. Claverie, D. Alquier, H. Richter, 

M. Kittler 

Proc. of the 11th International Autumn Meeting, 

Giens, September 25-30, 2005, France, Solid 

State Phenomena 108-109 (2005) 

(3) Proceedings of the Second International 

SiGe Technology and Device Meeting (IST- 

DM 2004), Kleist-Forum Frankfurt (Oder), 

Germany, May 16-19: From Materials and 

Process Technology to Device and Circuit 

Design 

Ed.: E. Kasper, B. Tillack, J. Murota, G. Fischer 

Materials Science in Semiconductor Processing 

8, 1-3 (2005) 

(4) The Silicon Age 

Ed.: M. Kittler, D. Yang 

Proc. 2 nd Sino-German Symposium Cottbus, Germany, 

September 22 (2005) 

Dissertation 

Dissertation 

(1) TEM-Holographie and Bauelementestrukturen 

der Mikroelektronik 

P. Formanek 

BTU Cottbus 2005 

Monographien 

Dissertation / Diplom 

Monographs 

Dissertation / Diploma 

Diplomarbeiten/Masterarbeiten/ 

Bachelorarbeiten 

Diploma Theses/Master Theses/ 

Bachelor Theses 

(1) Anwendung der EBIC-Methode auf Probleme 

der Si-Materialforschung 

G. Jia 


(2) Evaluierung von Firewall-Ansätzen für Handheld 

Devices 

M. Lehmann 


(3) Kohlenstoff als nichtdotierendes Element 

in SiGe-Schichten auf Silizium-Substrat 

S. Lischke 


(4) Automatische Verifizierung von SPICE-Model- 

len in Perl 

T. Mausolf 

FH Brandenburg 2005 

(5) Weiterentwicklung eines Verfahrens zur 

Bestimmung der optischen Konstanten von 

Fotolacken mittels Swingkurven in der Fotolithografie 

M. Szuggars 

TFH Wildau 2005 

(6) Effizientes Implementierungsmodell von 

SDL-Spezifikationen in eingebetteten Systemen 

G. Wagenknecht 


(7) SPICE-Modellierung vertikaler Bipolartransistoren 

eines CMOS-Prozesses 

C. Wipf 

FH Brandenburg 2005 

(8) Einfluss der Beugung auf Swingkurven der 

Fotolithografie 

A. von Woroniecki 

TFH Wildau 2005 


Patente Patents 

Patente 

Patents 

156 

(1) Verfahren und Vorrichtung zur Niedertemperaturepitaxie 

auf einer Vielzahl von Halbleitersubstraten 

T. Grabolla, B. Tillack, G. Ritter 

PCT-Patentanmeldung IHP.256.PCT am 

10.05.2005, AZ: PCT/EP2005/052123 

(2) GALS-Schaltung und Verfahren zum Betrieb 

einer GALS-Schaltung 

E. Grass, M. Krstic, F. Winkler 

DE-Patentanmeldung IHP.268.05, am 12.09.05, 

AZ: 10 2005 044 115.7 

(3) Vertikaler Bipolartransistor 

B. Heinemann, H. Rücker, J. Drews, S. Marschmeyer 



(4) Versetzungsbasierter Lichtemitter 

M. Kittler, T. Arguirov, W. Seifert 





Applying Karatsuba’s Method 

P. Langendörfer, Z. Dyka 


AZ: 05 090 052.1 

(6) Halbleiterbauelement mit Gegensignalschaltung 

zum Vermeiden von Übersprechen 

elektronischer Baugruppen 

Gu. Lippert, Ge. Lippert 

PCT-Patentanmeldung IHP.251.PCT am 08.04.05, 

AZ: PCT/EP2005/051569 

(7) Kondensatorstruktur mit stabilisiertem Praseodymoxid-Dielektrikum 

G. Lippert, J. Dabrowski, C. Wenger, H.-J. Müssig 




(8) Ätzverfahren für MOS-Schichtstrukturen mit 

praseodymoxidhaltigem Dielektrikum 

H.-J. Müssig, A. Mane, C. Wenger, G. Lippert 



(9) MIM/MIS-Struktur mit Praseodymtitanat 

oder Praseodymoxid als Isolatormaterial 

H.-J. Müssig, G. Lippert, C. Wenger 



(10) Verfahren zur Herstellung einer Praseodymsilikat-Schicht 

und nach dem Verfahren 

hergestelltes Substrat 

H.-J. Müssig, J. Dabrowski, G. Lippert, G. Lupina, 

C. Wenger 



(11) Kondensator mit dielektrischer Schicht aus 

praseodymhaltigem Mischoxid 

H.-J. Müssig, J. Dabrowski, G. Lippert, T. Schröder, 

C. Wenger 



(12) Method and Apparatus for the Determination 

of the Concentration of Impurities in 

a Wafer 

H. Richter, V. Akhmetov, O. Lysytskiy 



(13) Verringerte Übersprache zwischen benachbarten 

Frequenzbereichen in einem elektronischen 

Bauelement mit einem Verstärker 

oder Mischer und abstimmbarer Impedanzanpassung 

L. Wang, W. Winkler, G. Wang 


AZ: 10 2005 044 856.9


Notizen Notices 

157

Wegbeschreibung zum IHP 

Directions to IHP 

158 

per Flugzeug 

- Vom Flughafen Berlin-Tegel mit der Buslinie X9 bis 

Bahnhof Berlin-Zoologischer Garten (19 Minuten); 

dann mit dem RegionalExpress RE 1 bis Frankfurt 

(Oder) Hauptbahnhof (ca. 1 Stunde 20 Minuten). 

- Vom Flughafen Berlin-Schönefeld mit dem Airport- 

Express oder der S-Bahnlinie S 9 bis Bahnhof Berlin-Ostbahnhof 

(19 bzw. 32 Minuten); dann mit dem 

RegionalExpress RE 1 bis Frankfurt (Oder) Hauptbahnhof 

(ca. 1 Stunde). 

- Vom Flughafen Berlin-Tempelhof mit der U-Bahnlinie 

U 6 Richtung Alt-Tegel bis zur Haltestelle Friedrichstraße 

(11 Minuten); umsteigen in den Regional- 

Express RE 1 bis Frankfurt (Oder) Hauptbahnhof 

(ca. 1 Stunde 15 Minuten). 

per Bahn 

- Von den Berliner Bahnhöfen Zoologischer Garten, 

Friedrichstraße, Alexanderplatz oder Ostbahnhof 

mit dem RegionalExpress RE 1 bis Frankfurt 

(Oder) Hauptbahnhof. 

per Auto 

- Über den Berliner Ring auf die Autobahn A 12 in Richtung 

Frankfurt (Oder)/Warschau; Abfahrt Frankfurt 

(Oder)-West, an der Ampel links in Richtung Beeskow 

und dem Wegweiser „Technologiepark Ostbrandenburg“ 

folgen. 

per Straßenbahn in Frankfurt (Oder) 

- Ab Frankfurt (Oder) 

Hauptbahnhof mit 

der Linie 4 in Richtung 

Markendorf Ort 

bis Haltestelle Technologiepark 

(14 Minuten). 

A12 

1 

by plane 


- From Berlin-Tegel Airport take the bus X9 to the railway 

station Berlin-Zoologischer Garten (19 minutes); 

then take the RegionalExpress RE 1 to Frankfurt 

(Oder) Hauptbahnhof (appr. 1 hour 20 minutes). 

- From Berlin-Schönefeld Airport take the Airport- 

Express or the S-Bahn line S 9 to the railway station 

Berlin Ostbahnhof (19 resp. 32 minutes); then 

take the RegionalExpress RE 1 to Frankfurt (Oder) 

Hauptbahnhof (appr. 1 hour). 

- From Berlin-Tempelhof Airport take the subway line 

U 6 in the direction Alt-Tegel to the station Friedrichstraße 

(11 minutes); there transfer to the RegionalExpress 

RE 1 to Frankfurt (Oder) Hauptbahnhof 

(appr. 1 hour 15 minutes). 

by train 

- Take the train RegionalExpress RE 1 from the Berlin 

railway stations Zoologischer Garten, Friedrichstraße, 

Alexanderplatz or Ostbahnhof to Frankfurt 

(Oder) Hauptbahnhof. 

by car 

Frankfurt (Oder) - West 

Turn left 

at the traffi c ligths 

in the direction of 

Beeskow 

- Take the highway A 12 from Berlin in the direction 

Frankfurt (Oder)/Warschau (Warsaw); take 

exit Frankfurt (Oder) -West, at the traffic lights 

turn right in the direction Beeskow and follow the 

signs to "Technologiepark Ostbrandenburg". 

by tram in Frankfurt (Oder) 

- Take the Tram 4 from railway station Frankfurt 

(Oder) Hauptbahnhof in the direction Markendorf 

Ort to Technologiepark (14 minutes). 

2 

intersection. 

turn left onto 

“Müllroser Chaussee“ 

Berlin Warsaw 

3 

direction 

Frankfurt (Oder) 

left again at the 

intersection toward 

“Technologiepark Ostbrandenburg“

Impressum/Imprint 

Herausgeber/Publisher 

IHP GmbH – Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik 

Postadresse/Postbox 

Postfach 1466/Postbox 1466 

15204 Frankfurt (Oder) 

Deutschland/Germany 

Besucheradresse/Address for visitors 



Deutschland/Germany 

Telefon/Fon +49.335.56 25 0 

Telefax/Fax +49.335.56 25 300 

E-Mail ihp@ihp-microelectronics.com 

Internet www.ihp-microelectronics.com 

Redaktion/Editors 

Dr. Wolfgang Kissinger/Heidrun Förster 

Gesamtherstellung/Production in design and layout 

Publishers an der Oder 

Ferdinandstraße15 


Telefon/Fon +49.335.414590 

Telefax/Fax +49.335.4145923 

E-Mail info@publishers-oder.de 

Internet www.publishers-oder.de 

Bildnachweise/Photocredits 

IHP, Winfried Mausolf, Heinz Köhler, Andreas Schenk 

Soweit nicht anders vermerkt, liegt das Copyright für die selbst erstellten 

Texte und Abbildungen von IHP-Mitarbeitern allein beim IHP. 



IHP GmbH – Innovations for High Performance Microelectronics/Institut 

für innovative Mikroelektronik 



Germany 

Phone +49.335.56 25 0 

Fax +49.335.56 25 300 

www.ihp-microelectronics.com 

Member of the Leibniz Association

Annual Report 2005 (PDF 4.3 MB) - IHP Microelectronics

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