Annual Report 2004 (PDF 4.3 MB) - IHP Microelectronics
Annual Report 2004 (PDF 4.3 MB) - IHP Microelectronics
Annual Report 2004 (PDF 4.3 MB) - IHP Microelectronics
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<strong>Annual</strong> <strong>Report</strong> <strong>2004</strong><br />
JAHRESBERICHT <strong>2004</strong> | INSTITUT FÜR INNOVATIVE MIKROELEKTRONIK
Impressum/Imprint<br />
Herausgeber/Publisher<br />
<strong>IHP</strong> GmbH – Innovations for High Performance <strong>Microelectronics</strong>/Institut für innovative Mikroelektronik<br />
Postadresse/Postbox<br />
Postfach 1466/Postbox 1466<br />
15204 Frankfurt (Oder)<br />
Deutschland/Germany<br />
Besucheradresse/Address for visitors<br />
Im Technologiepark 25<br />
15236 Frankfurt (Oder)<br />
Deutschland/Germany<br />
Telefon / Phone +49.335.56 25 0<br />
Telefax / Fax +49.335.56 25 300<br />
E-Mail ihp@ihp-microelectronics.com<br />
Internet www.ihp-microelectronics.com<br />
Redaktion/Editors<br />
Dr. Wolfgang Kissinger/Heidrun Förster<br />
Gesamtherstellung/Production in design and layout<br />
Publishers an der Oder<br />
Ferdinandstraße 15<br />
15230 Frankfurt (Oder)<br />
Telefon/ Phone +49.335.41 45 90<br />
Telefax / Fax +49.335.41 45 923<br />
E-Mail info@publishers-oder.de<br />
Internet www.publishers-oder.de<br />
Bildnachweise/Photocredits<br />
<strong>IHP</strong> GmbH; Winfried Mausolf; Publishers an der Oder; Timo Röder<br />
Soweit nicht anders vermerkt, liegt das Copyright für die selbst erstellten Texte und Abbildungen von <strong>IHP</strong>-<br />
Mitarbeitern allein bei der <strong>IHP</strong> GmbH.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT
<strong>Annual</strong> <strong>Report</strong> <strong>2004</strong><br />
JAHRESBERICHT <strong>2004</strong> | INSTITUT FÜR INNOVATIVE MIKROELEKTRONIK
Vorwort Foreword<br />
Das <strong>IHP</strong> konzentriert sich auf die Erforschung und Entwicklung<br />
innovativer Lösungen für die drahtlose und<br />
Breitbandkommunikation. Als Leibniz-Institut verfolgt es<br />
langfristige Zielstellungen und verbindet dabei Grundlagenforschung<br />
mit angewandter Forschung. Es versteht<br />
sich als ein europäisches Forschungs- und Innovationszentrum,<br />
dass grundlegende Ergebnisse bis zu industriell<br />
relevanten Prototypen weiterführt.<br />
Das vertikale Forschungskonzept des <strong>IHP</strong> beinhaltet<br />
die Entwicklung neuer Lösungen unter Einbeziehung<br />
mehrerer Ebenen der Wertschöpfung. Dabei setzt das<br />
Institut gezielt seine aufeinander abgestimmten Kompetenzen<br />
im System Design, dem Design von Hochfrequenzschaltungen,<br />
der Halbleitertechnologie sowie<br />
der Materialforschung für die Mikroelektronik ein. Eine<br />
weitere wichtige Besonderheit ist die Pilotlinie mit ihren<br />
sehr leistungsfähigen BiCMOS-Technologien. Sie<br />
ermöglicht dem <strong>IHP</strong> und seinen Partnern, Prototypen<br />
mit hervorragenden Leistungsparametern und mit integrierten<br />
zusätzlichen Funktionalitäten zu realisieren.<br />
Im vergangenen Jahr konnte die Zusammenarbeit des<br />
Institutes mit der Industrie, die Teilnahme an nationalen<br />
und europäischen Verbundprojekten sowie die Kooperation<br />
mit den regionalen Hochschulen in Cottbus,<br />
Wildau und Berlin wesentlich ausgebaut werden. Ebenso<br />
wuchs die Anzahl von Firmen, Forschungseinrichtungen<br />
und Hochschulen, die Technologien des <strong>IHP</strong> über<br />
den MPW und Prototyping Service für ihre Forschungs-<br />
und Entwicklungsarbeiten nutzen.<br />
Mit dem Ausbau dieser Kooperationen ist es dem <strong>IHP</strong><br />
gelungen, die für seine Forschungsprogramme erforderlichen<br />
Drittmittel einzuwerben. Von großer Bedeutung<br />
für die längerfristige Entwicklung des Institutes<br />
ist die im Jahr <strong>2004</strong> begonnene Modernisierung seiner<br />
Ausrüstungsbasis mit Hilfe des Europäischen Fonds für<br />
regionale Entwicklung.<br />
Die in diesem Bericht dargestellten internationalen<br />
Spitzenleistungen wurden durch die engagierte Arbeit<br />
unserer Mitarbeiterinnen und Mitarbeiter möglich. Ihnen<br />
gilt unser besonderer Dank. Ebenso danken wir der<br />
Brandenburgischen Landesregierung und der Bundesregierung<br />
für ihre außerordentliche Unterstützung.<br />
2<br />
Frankfurt (Oder), Mai 2005<br />
Wolfgang Mehr<br />
Wiss.-Techn. Geschäftsführer<br />
Manfred Stöcker<br />
Admin. Geschäftsführer<br />
Prof. Dr. Wolfgang Mehr<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
The <strong>IHP</strong> concentrates on<br />
the research and development<br />
of solutions for wireless<br />
and broadband communication.<br />
As a Leibniz<br />
Institute it pursues longterm<br />
goals and in doing so<br />
connects basic research<br />
with applied research. It<br />
sees itself as a European<br />
research and innovation<br />
center which develops basic<br />
results into prototypes<br />
relevant for industry.<br />
<strong>IHP</strong>’s vertical research concept entails the development<br />
of new solutions considering several levels of the valueadded<br />
chain. To this end the institute specifi cally aims at<br />
utilizing its harmonized competencies in system design,<br />
the design of RF circuits, semiconductor technology as<br />
well as materials research for microelectronics. Another<br />
important feature is the pilot line with its very high performance<br />
BiCMOS technologies, which enables the <strong>IHP</strong> to<br />
realize prototypes with excellent performance parameters<br />
and additionally integrated functionalities.<br />
Last year the institute managed to intensify its cooperation<br />
with industry and regional universities in Cottbus,<br />
Wildau and Berlin, and to take part in national and<br />
European joint projects. At the same time there was<br />
a growth in the number of companies, research centers<br />
and universities using <strong>IHP</strong>’s technologies via MPW<br />
and Prototyping Service for their research and development<br />
projects.<br />
By intensifying such cooperation, the <strong>IHP</strong> succeeded in<br />
acquiring the third-party funding needed for its research<br />
programs. What is of particular signifi cance for the longterm<br />
development of the Institute is the modernization<br />
of its basic equipment, which began in <strong>2004</strong> with the<br />
help of the European Regional Development Fund.<br />
The international first-rate performance presented in<br />
this report is attributable to the dedication of <strong>IHP</strong>’s<br />
employees, which is why we would like to pay them our<br />
particular thanks. We would equally like to thank the<br />
regional government of Brandenburg and the federal<br />
government for their exceptional support.
Vorwort/Foreword<br />
Aufsichtsrat/Supervisory Board<br />
Wissenschaftlicher Beirat/Scientific Advisory Board<br />
Das <strong>IHP</strong> auf einen Blick/<strong>IHP</strong> in a Nutshell<br />
Das Jahr <strong>2004</strong>/Update <strong>2004</strong><br />
Angebote und Leistungen/Deliverables and Services<br />
Forschung des <strong>IHP</strong>/<strong>IHP</strong>’s Research<br />
Ausgewählte Projekte/Selected Projects<br />
Drahtloses Internet/Wireless Internet<br />
Technologieplattform/Technology Platform<br />
Materialien für die Mikroelektronik/Materials<br />
for <strong>Microelectronics</strong><br />
Gemeinsames Labor <strong>IHP</strong>/BTU – <strong>IHP</strong>/BTU Joint Lab<br />
Konferenzen und Workshops/Conferences and<br />
Workshops<br />
Zusammenarbeit und Partner/Collaborators and<br />
Partners<br />
Gastwissenschaftler und Seminare/Guest Scientists<br />
and Seminars<br />
Publikationen/Publications<br />
Nachdrucke ausgewählter Publikationen/<br />
Reprints of Selected Publications<br />
Erschienene Publikationen/<br />
Published Papers<br />
Eingeladene Vorträge/Invited Presentations<br />
Vorträge/Presentations<br />
Berichte/<strong>Report</strong>s<br />
Monografien/Monographs<br />
Patente/Patents<br />
Inhaltsverzeichnis<br />
Seite<br />
Contents<br />
Page<br />
2<br />
4<br />
5<br />
6<br />
8<br />
16<br />
24<br />
28<br />
29<br />
38<br />
50<br />
58<br />
62<br />
66<br />
70<br />
74<br />
75<br />
124<br />
134<br />
136<br />
143<br />
145<br />
146<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 3
Aufsichtsrat Supervisory Board<br />
Aufsichtsrat<br />
Konstanze Pistor<br />
Vorsitzende<br />
Ministerium für Wissenschaft, Forschung und Kultur<br />
Land Brandenburg<br />
MinDirig Dr. Wolf-Dieter Lukas<br />
Stellvertretender Vorsitzender<br />
Bundesministerium für Bildung und Forschung<br />
Prof. Dr. Helmut Gabriel<br />
Freie Universität Berlin<br />
Dr. Harald Richter<br />
<strong>IHP</strong><br />
Prof. Dr. Ernst Sigmund<br />
Brandenburgische Technische Universität Cottbus<br />
Dr. Wolfgang Winkler<br />
<strong>IHP</strong><br />
MinR Gerhard Wittmer<br />
Ministerium der Finanzen<br />
Land Brandenburg<br />
Bis 30. November <strong>2004</strong><br />
Staatssekretär Dr. Christoph Helm<br />
Vorsitzender<br />
Ministerium für Wissenschaft, Forschung und Kultur<br />
Land Brandenburg<br />
MinDir Dr. Peter Krause<br />
Stellvertretender Vorsitzender<br />
Bundesministerium für Bildung und Forschung<br />
4<br />
Supervisory Board<br />
Konstanze Pistor<br />
Chair<br />
Ministry of Science, Research and Culture<br />
State of Brandenburg<br />
Dr. Wolf-Dieter Lukas<br />
Deputy<br />
Federal Ministry of Education and Research<br />
Prof. Helmut Gabriel<br />
Freie Universität Berlin<br />
Dr. Harald Richter<br />
<strong>IHP</strong><br />
Prof. Ernst Sigmund<br />
Technical University of Brandenburg, Cottbus<br />
Dr. Wolfgang Winkler<br />
<strong>IHP</strong><br />
Gerhard Wittmer<br />
Ministry of Finance<br />
State of Brandenburg<br />
Until November 30, <strong>2004</strong><br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Undersecretary of State Dr. Christoph Helm<br />
Chair<br />
Ministry of Science, Research and Culture<br />
State of Brandenburg<br />
Dr. Peter Krause<br />
Deputy<br />
Federal Ministry of Education and Research
Wissenschaftlicher Beirat<br />
Prof. Dr. Hermann G. Grimmeiss<br />
Vorsitzender<br />
Department of Solid State Physics<br />
Lund University, Schweden<br />
Dr. Jürgen Arndt<br />
Stellvertretender Vorsitzender<br />
ATMEL Germany GmbH, Heilbronn<br />
Prof. Dr. Ignaz Eisele<br />
Fakultät für Elektrotechnik und Informationstechnik<br />
Universität der Bundeswehr München<br />
Prof. Dr. Christian Enz<br />
CSEM SA, Neuchatel, Schweiz<br />
Prof. Dr. Ulrich Rohde<br />
Synergy Microwave Corporation, USA<br />
Dr. Josef Winnerl<br />
Infineon Technologies AG, München<br />
Prof. Dr. Günter Zimmer<br />
Fraunhofer IMS, Duisburg<br />
Leitung<br />
Prof. Dr. Wolfgang Mehr<br />
Wissenschaftlich-Technischer Geschäftsführer<br />
Manfred Stöcker<br />
Administrativer Geschäftsführer<br />
Wissenschaftlicher<br />
Beirat<br />
Scientifi c Advisory Board<br />
Prof. Hermann G. Grimmeiss<br />
Chair<br />
Department of Solid State Physics<br />
Lund University, Sweden<br />
Dr. Jürgen Arndt<br />
Deputy<br />
ATMEL Germany GmbH, Heilbronn<br />
Prof. Ignaz Eisele<br />
Department of Electrical Engineering and Information<br />
Technology, University of the Bundeswehr, Munich<br />
Prof. Christian Enz<br />
CSEM SA, Neuchatel, Switzerland<br />
Prof. Ulrich Rohde<br />
Synergy Microwave Corporation, USA<br />
Dr. Josef Winnerl<br />
Infineon Technologies AG, Munich<br />
Prof. Günter Zimmer<br />
Fraunhofer IMS, Duisburg<br />
Management<br />
Prof. Wolfgang Mehr<br />
Director<br />
Manfred Stöcker<br />
Administrative Director<br />
Scientific Advisory<br />
Board<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 5
Das <strong>IHP</strong> auf einen Blick<br />
<strong>IHP</strong> in a Nutshell
Das Institut<br />
- Gegründet 1983; 1991 Neugründung aus einem<br />
früheren Akademieinstitut mit langjähriger Erfahrung<br />
in der Mikroelektronik auf Silizium-Basis<br />
- ca. 200 Mitarbeiter aus 16 Ländern<br />
- Mitglied der Leibniz-Gemeinschaft<br />
Aufgabe<br />
- Wirkung als Europäisches Forschungs- und Innovationszentrum<br />
für drahtlose Kommunikationstechnologien<br />
- Stärkung der Wettbewerbsfähigkeit der deutschen<br />
und europäischen Mikroelektronik- und Kommunikationsforschung<br />
- Erhöhung der Attraktivität der Region als Hochtechnologiestandort<br />
Strategie<br />
- Wertschöpfung durch Innovation<br />
- Konzentration auf drahtlose und Breitbandkommunikation<br />
- Entwicklung zukunftsorientierter Technologien,<br />
Schaltkreise und Systeme bis zu Prototypen<br />
- Strategische Partnerschaften<br />
Infrastruktur<br />
- Vollständige Innovations-Kette vom Material bis zu<br />
Systemen, einschließlich Pilotlinie mit 0,25 (0,13)-µm-<br />
BiCMOS-Technologien<br />
Kompetenzen<br />
- Systeme für die drahtlose Kommunikation<br />
- HF-Schaltkreisentwurf<br />
- Erweiterung von Silizium-CMOS-Technologien für<br />
neue Funktionen<br />
- Materialien für die Mikroelektronik-Technologie<br />
Das <strong>IHP</strong> auf einen Blick <strong>IHP</strong> in a Nutshell<br />
The Institute<br />
- Founded in 1983; Re-established in 1993 as a successor<br />
institution to the former institute of the<br />
East German Academy with extensive experience<br />
in silicon microelectronics<br />
- 200 employees from 16 countries<br />
- Member of the Leibniz Association<br />
Mission<br />
- To act as a European Research- and Innovation<br />
Center for wireless communication technologies<br />
- To strengthen the competitive position of the German<br />
and European microelectronic and communication<br />
research<br />
- To enhance the attractiveness of the region as a<br />
location for high technology<br />
Strategy<br />
- To create value through innovation<br />
- To focus on solutions for wireless and broadband<br />
communications<br />
- Development of forward-looking technologies, circuits<br />
and systems up to prototypes<br />
- Strategic partnerships<br />
Facilities<br />
- Complete innovation chain from materials to systems,<br />
including a pilot line with 0.25 (0.13) µm BiCMOS<br />
technologies<br />
Competencies<br />
- Systems for wireless communication<br />
- RF circuit design<br />
- Extension of silicon CMOS technologies for new<br />
functionalities<br />
- Materials for microelectronic technology<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 7
Das Jahr <strong>2004</strong><br />
Update <strong>2004</strong>
Im Jahr <strong>2004</strong> wurde die Forschungsarbeit des <strong>IHP</strong> entsprechend<br />
der erarbeiteten Strategie in den drei Forschungsprogrammen<br />
„Drahtloses Internet“, „Technologieplattform“<br />
und „Materialien für die Mikroelektronik“<br />
erfolgreich weitergeführt.<br />
Spitzenleistungen wie z.B. eine sehr leistungsstarke<br />
komplementäre BiCMOS-Technologie und Schlüsselkomponenten<br />
für 60-GHz-Anwendungen fanden bereits<br />
starke internationale Beachtung und zeigen das<br />
Potential des <strong>IHP</strong>.<br />
Im Jahr <strong>2004</strong> gelang in allen Programmen eine Verbesserung<br />
der Kooperation sowie der nationalen und<br />
internationalen Vernetzung der Forschung.<br />
Von besonderem Wert ist das große Interesse der Industrie<br />
an den Arbeiten des <strong>IHP</strong>. Davon zeugen die<br />
<strong>2004</strong> eingeworbenen 5,1 Mio. Euro Drittmittel mit einem<br />
Industrieanteil von etwa 50% ebenso wie zahlreiche<br />
Arbeitsbesuche von Industrievertretern am <strong>IHP</strong><br />
sowie von <strong>IHP</strong>-Mitarbeitern bei der Industrie.<br />
Ausser durch zahlreiche Anwender aus Universitäten<br />
und Forschungseinrichtungen wird der Multiprojekt Wafer<br />
(MPW) und Prototyping Service des <strong>IHP</strong> ebenfalls<br />
von einer großen Anzahl Firmen für deren Forschungen<br />
und Entwicklungen genutzt.<br />
Im Jahr <strong>2004</strong> arbeitete das <strong>IHP</strong> in mehreren nationalen<br />
Verbundprojekten, so z.B. BASUMA, Wireless Internet-<br />
Ad Hoc, Wireless Internet-Zellular, Mobile Internet Business,<br />
WIGWAM, KOKON und SOBSI.<br />
Innerhalb des 6. Rahmenprogrammes der EU ist das<br />
<strong>IHP</strong> in den Projekten PULSERS und WINDECT tätig.<br />
Die Kooperation mit Hochschulen, insbesondere im Land<br />
Brandenburg und in Berlin, wurde deutlich erweitert:<br />
Der Ausbau eines gemeinsamen Kompetenzzentrums für<br />
Halbleitermaterialien und -technologien im Rahmen des<br />
<strong>IHP</strong>/BTU Joint Lab wird auch in seiner zweiten Phase als<br />
Forschungsprojekt im Rahmen des Hochschul- und Wissenschaftsprogramms<br />
gefördert. Die Forschungsinhalte<br />
der Kooperation mit der BTU wurden <strong>2004</strong> neu strukturiert<br />
und mit den Forschungszielen des <strong>IHP</strong> abgeglichen.<br />
Mit der TFH Wildau wurde die Kooperation in Forschung<br />
und Lehre weiter ausgebaut. Eine Kooperationsvereinbarung<br />
mit der TU Berlin ist in Vorbereitung.<br />
Das Jahr <strong>2004</strong> Update <strong>2004</strong><br />
In the year <strong>2004</strong> the research of the <strong>IHP</strong> was continued<br />
according to the designed strategy successfully<br />
in the three research programs ”Wireless Internet“,<br />
”Technology Platform“ and ”Materials for <strong>Microelectronics</strong>“.<br />
Top results such as a very high performance complementary<br />
BiCMOS technology and key components for<br />
60 GHz applications already received strong international<br />
attention and show the potential of the <strong>IHP</strong>.<br />
In <strong>2004</strong> an improvement in cooperation as well as the<br />
national and international networking of the research<br />
was noted in all the programs.<br />
The particular interest of the industry in <strong>IHP</strong>‘s research<br />
is from special value. This is refl ected in the 5.1 million<br />
euros in third-party funding with an industrial portion<br />
of approximately 50% obtained in <strong>2004</strong>, as well as the<br />
numerous visits to the <strong>IHP</strong> made by representatives of<br />
the industry and the visits made by <strong>IHP</strong> staff to industrial<br />
companies.<br />
In addition to many users from universities and research<br />
institutes, the <strong>IHP</strong> Multi-Project Wafer (MPW)<br />
and Prototyping Service is also being used by an large<br />
number of companies for their research and development.<br />
In <strong>2004</strong>, the <strong>IHP</strong> worked on a number of national cooperative<br />
projects, for instance BASUMA, Wireless<br />
Internet-Ad Hoc, Wireless Internet-Zellular, Mobile<br />
Internet Business, WIGWAM, KOKON and SOBSI.<br />
The <strong>IHP</strong> is working on the projects PULSERS and WIN-<br />
DECT within the EU’s Sixth Framework Programme.<br />
Cooperation with universities, especially in the states<br />
of Berlin and Brandenburg, was expanded signifi cantly:<br />
The expansion of a joint competence center for semiconductor<br />
materials and technologies in the framework<br />
of the <strong>IHP</strong>/BTU Joint Lab will also be subsidized in its<br />
second phase as a research project as part of the University<br />
and Science Program. The contents of the research<br />
cooperations with the BTU were restructured in<br />
<strong>2004</strong> and attuned to the <strong>IHP</strong> research objectives. The<br />
cooperation in research and teachings was intensifi ed<br />
with the TFH Wildau. A cooperation agreement is being<br />
prepared with the TU Berlin.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 9
Das Jahr <strong>2004</strong> Update <strong>2004</strong><br />
An diesen Hochschulen halten <strong>IHP</strong>-Mitarbeiter Vorlesungen<br />
und betreuen Diplomanden bzw. Doktoranden.<br />
Eine wissenschaftliche Kooperation mit der Europa-<br />
Universität Viadrina wurde mit dem Projekt „Mobile<br />
Internet Business“ begonnen.<br />
Das <strong>IHP</strong> war im Jahr <strong>2004</strong> aktiv an der Organisation<br />
von zehn internationalen Tagungen auf seinen Arbeitsgebieten<br />
beteiligt, von denen drei in Frankfurt (Oder)<br />
stattfanden.<br />
Durch Mittel des EFRE-Strukturfonds ist es dem <strong>IHP</strong><br />
möglich, die technologische Ausrüstung, die erforderlichen<br />
Testsysteme und die Entwurfssoftware für das<br />
0,13-µm-Strukturniveau aufzubauen. Mit der Realisierung<br />
dieser Investitionen wurde begonnen.<br />
Zur Schaffung und zum Erhalt von Arbeitsplätzen in<br />
der Region gibt es mehrere Aktivitäten zur Vorbereitung<br />
von Ausgründungen aus dem <strong>IHP</strong> und zur Unterstützung<br />
von Ansiedlungsplänen für Mikroelektronik-<br />
Firmen.<br />
Wissenschaftliche Ergebnisse<br />
10<br />
Drahtloses Internet: Systeme und Anwendungen<br />
Die erfolgreiche Einwerbung von Drittmitteln ermöglichte<br />
ein deutliches personelles Wachstum in diesem<br />
Forschungsprogramm. Im Rahmen der existierenden<br />
Teilprogramme wurden inhaltliche Erweiterungen vorgenommen,<br />
so z.B. wurden die Arbeiten zu Low Power<br />
durch Sensornetze und Anwendungen und die Arbeiten<br />
zu High-Performance Systemen in Richtung Radar und<br />
Satellitenkommunikation erweitert.<br />
Beispiele für Ergebnisse im Jahr <strong>2004</strong> sind:<br />
1. Erarbeitung integrierter Lösungen für Systeme zur<br />
drahtlosen Kommunikation mit hohen Datenraten.<br />
Durch das Projekt 5-GHz-WLAN Modems wurden im<br />
Herbst <strong>2004</strong> erste Design-Umgebungen (Link-Emulator)<br />
für Applikationsentwicklungen bereitgestellt.<br />
Für die 60 GHz / 1 Gbps WLAN Lösung sind alle<br />
HF-Komponenten entwickelt und erste Prototypen<br />
verfügbar. Hier ist insbesondere die PLL (Phase<br />
Locked Loop) hervorzuheben, die als weltweit erste<br />
SiGe-PLL für 60 GHz gilt.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
<strong>IHP</strong> staff members hold lectures and advise students<br />
and graduate students at these universities.<br />
A scientific cooperation with the European University<br />
Viadrina was initiated with the ”Mobile Internet Business“<br />
project.<br />
In <strong>2004</strong>, the <strong>IHP</strong> participated in the organization of 10<br />
international conferences in its fields. Three of these<br />
were held in Frankfurt (Oder).<br />
With funding from the EU Regional Development Fund,<br />
it has been possible for the <strong>IHP</strong> to set up the technological<br />
equipment, the necessary testing systems and<br />
the design software for the 0.13 µm structure level.<br />
The realization of this investment has been initiated.<br />
To create and maintain jobs in the region there are a<br />
number of activities being prepared for spin-offs from<br />
the <strong>IHP</strong> and to support the settlement activities for<br />
microelectronics companies.<br />
Scientifi c Results<br />
Wireless Internet: Systems and Applications<br />
The success in obtaining third-party funding allowed<br />
for significant growth in personnel in this research program.<br />
In the framework of the existing sub-program<br />
expansions in the content were made, for instance,<br />
the work on low power was expanded by sensor networks<br />
and applications, the work on high-performance<br />
systems was expanded in the direction of radar and<br />
satellite communication.<br />
Examples of results in <strong>2004</strong> were:<br />
1. Development of integrated solutions for systems<br />
for wireless communication with high data rates.<br />
In the autumn of <strong>2004</strong>, initial design environments<br />
(link emulator) for application developments were<br />
provided by the 5 GHz WLAN modems project.<br />
All the RF components and initial prototypes were<br />
developed for the 60 GHz/1 Gbps WLAN solution.<br />
The PLL (Phase Locked Loop) deserves special<br />
mention in this regard; it is the first SiGe PLL for<br />
60 GHz in the world.
2. Arbeiten zu Radarsensoren.<br />
Für Radarsensoren wurden erste aktive und passive<br />
Mischer präpariert. Die Arbeiten zu 78 GHz-<br />
Sensoren werden im Rahmen des Projektes KOKON<br />
weitergeführt. Hier sind erste sehr gute Ergebnisse<br />
bei LNA (Low Noise Amplifier) und VCO (Voltage<br />
Controlled Oscillator) erzielt worden.<br />
3. Entwicklung von Middleware für innovative Anwendungen<br />
der drahtlosen Kommunikation.<br />
Die Konzepte zur Security und Privacy wurden fertiggestellt<br />
und erfolgreich getestet. Encryption-<br />
Prozessoren wurden erfolgreich gefertigt und getestet.<br />
4. Erarbeitung integrierter Lösungen für die Leistungsverstärkung<br />
bei hohen Frequenzen.<br />
Integrierte Leistungsverstärker mit LDMOS erlauben<br />
den Einsatz sowohl für WLANS als auch für<br />
Bluetooth ohne externe Bauelemente, was dem<br />
Nutzer einen deutlichen Wettbewerbsvorteil bietet.<br />
5. Erarbeitung eines integrierten Wireless Bus Systems<br />
für medizinische Anwendungen.<br />
Erste Ergebnisse im Projekt BASUMA wurden mit<br />
der Realisierung der MAC (Medium-Access-Control)-Protokolle<br />
und des Basisband-Transmitters<br />
erzielt. Eine Zusammenarbeit mit der BTU Cottbus<br />
im Bereich der Betriebssysteme soll ein neues<br />
Basissystem für mobile Sensoren realisieren.<br />
6. Im Projekt UWB wurden alle Basiskomponenten für<br />
ein pulsbasiertes UWB-System realisiert. Die Anwendung<br />
soll im Projekt BASUMA erfolgen.<br />
7. Es wurden Prozessor-Bibliotheken für verschiedene<br />
Projekte mit den lizenzfreien Prozessoren ASPI-<br />
DA und LEON-2 realisiert. Während der Prozessor<br />
ASPIDA völlig asynchron ist, handelt es sich beim<br />
LEON um einen 32-Bit-RISC Prozessor.<br />
8. Neu wurde in <strong>2004</strong> mit Arbeiten zu schnellen Analog/Digital-Wandlern<br />
begonnen.<br />
Das Jahr <strong>2004</strong> Update <strong>2004</strong><br />
2. Work with radar sensors.<br />
The fi rst active and passive mixers were prepared<br />
for radar sensors, the work on 78 GHz sensors will<br />
be continued within the framework of the KOKON<br />
project. Here, very good initial results have been<br />
obtained in LNA (Low Noise Amplifier) and VCO<br />
(Voltage Controlled Oscillator).<br />
3. Development of middleware for innovative applications<br />
in wireless communication.<br />
The concepts for security and privacy were completed<br />
and successfully tested. Encryption processors<br />
were successfully produced and tested.<br />
4. Development of integrated solutions for amplification<br />
in high frequencies.<br />
Integrated amplifiers with LDMOS can be used in<br />
both WLANS as well as for Bluetooth without external<br />
components, which allows users a significant<br />
competitive advantage.<br />
5. Development of an integrated wireless bus system<br />
for medical applications.<br />
Initial results in the BASUMA project were attained<br />
with the realization of the MAC (Medium Access<br />
Control) protocols and the baseband transmitter.<br />
Cooperation with the BTU Cottbus in the area of<br />
operating systems will develop a new base system<br />
for mobile sensors.<br />
6. In the UWB project all the basic components for a<br />
pulse-based UWB system were realized. The application<br />
will be made in the BASUMA project.<br />
7. Processor libraries for various projects with the<br />
license-free processors ASPIDA and LEON-2 were<br />
realized. While the processor ASPIDA is completely<br />
asynchronous, LEON is a 32-Bit RISC processor.<br />
8. New in <strong>2004</strong> was the commencement of work on<br />
fast analog/digital converters.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 11
Das Jahr <strong>2004</strong> Update <strong>2004</strong><br />
Technologieplattform für drahtlose und Breitbandkommunikation<br />
Die vorhandenen 0,25-µm-BiCMOS-Technologien wurden<br />
im Jahr <strong>2004</strong> weiterentwickelt und durch zusätzliche<br />
Module mit neuen Funktionen erweitert.<br />
Mit der ausrüstungs- und technologieseitigen Vorbereitung<br />
der 0,13-µm-BiCMOS-Technologie wurde begonnen.<br />
Der Vorbereitung dieser Technologie dienten auch<br />
Entwicklungen neuer Konzepte für schnelle HBTs.<br />
12<br />
Beispiele für Ergebnisse im Jahr <strong>2004</strong> sind:<br />
1. Integration extrem schneller, komplementärer Hetero-Bipolartransistoren.<br />
Es gelang erneut, Weltrekord-Werte für die Gatterverzögerungszeiten<br />
siliziumbasierter Transistoren<br />
zu erreichen. So wurden für npn-Transistoren mit<br />
maximalen Transit- bzw. Schwingfrequenzen von<br />
f T /f max = 300/250 GHz und Durchbruchspannungen<br />
von BV CE0 = 1,8 V Gatterverzögerungen von 3,2 ps<br />
erreicht. Für pnp-Transistoren wurde bei f T /f max =<br />
135/140 GHz und BV CE0 = 2,5 V mit 5,9 ps ebenfalls<br />
ein neuer Weltrekord erzielt.<br />
Ausserdem wurde eine Lösung zur Verbindung von<br />
Hochgeschwindigkeits-HBTs und Dünnschicht-SOI-<br />
Substraten (Silicon-On-Insulator) erarbeitet. Erstmals<br />
wurden HBTs mit Grenzfrequenzen f T und f max<br />
oberhalb von 200 GHz auf CMOS-kompatiblen SOI-<br />
Substraten integriert.<br />
2. Weiterentwicklung des kostengünstigen 0,25-µm-<br />
SiGe:C-Prozesses (Value-Prozess).<br />
Für den Prozess wurde im Jahr <strong>2004</strong> eine Leistungssteigerung<br />
durch zusätzliche Hetero-Bipolartransistoren<br />
mit Grenzfrequenzen von f T /f max =<br />
130/150 GHz (zuvor 75/95 GHz) erreicht (eine Zusatzmaske<br />
erforderlich).<br />
3. Demonstration einer Technologie mit integriertem<br />
Flash Speicher.<br />
Eine Technologie mit 1-Mbit-Flash-Speicher, integriert<br />
in eine 0,25-µm-BiCMOS, wurde entwickelt.<br />
Das Integrationskonzept ist modular und erfordert<br />
nur vier zusätzliche Maskenebenen. Besonderheit<br />
der <strong>IHP</strong>-Lösung ist die einfache Integration von<br />
Flash in eine leistungsfähige BiCMOS (Value Prozess)<br />
bei insgesamt geringen Kosten.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Technology Platform for Wireless and Broadband<br />
The 0.25 µm BiCMOS technologies were further developed<br />
in <strong>2004</strong> and expanded by new functions with<br />
additional modules.<br />
Preparations for the equipment and technology of the<br />
0.13 µm BiCMOS technology were begun. The preparation<br />
of this technology also serves the development<br />
of new concepts for fast HBTs.<br />
Examples of results in <strong>2004</strong> were:<br />
1. Integration of extremely fast, complementary hetero-bipolar<br />
transistors.<br />
We again succeeded in attaining a world-record value<br />
for the gate-delay times of silicon-based transistors.<br />
For npn-transistors with maximum transit and<br />
oscillation frequencies of f T /f max = 300/250 GHz<br />
and breakdown voltages of BV CE0 = 1.8 V gate-delays<br />
of 3.2 ps were attained. For pnp-transistors a<br />
new world record of 5.9 ps was also attained with<br />
f T /f max = 135/140 GHz and BV CE0 = 2.5 V.<br />
In addition, a solution for the connection of highspeed<br />
HBTs and thin-layer-SOI-substrates (Silicon-<br />
On-Insulator) was developed. For the first time<br />
HBTs with maximum frequencies of f T and f max over<br />
200 GHz were integrated on CMOS-compatible<br />
SOI-substrates.<br />
2. Further development of cost-effective 0.25 µm<br />
SiGe:C processes (Value process).<br />
An increase in performance was achieved for the<br />
process in <strong>2004</strong> with additional hetero-bipolar<br />
transistors with maximum frequencies of f T /f max =<br />
130/150 GHz (previously 75/95 GHz) (an additional<br />
mask is required).<br />
3. Demonstration of a technology with integrated<br />
flash memory.<br />
A technology with 1 Mbit flash memory, integrated<br />
in a 0.25 µm BiCMOS, was developed. The integration<br />
principle is modular and requires only four<br />
additional mask levels. A unique feature of the <strong>IHP</strong><br />
solution is the simple integration of flash in a powerful<br />
BiCMOS (Value process) with low overall<br />
costs.
4. Weltweite Nutzung der <strong>IHP</strong>-Technologien durch<br />
MPW und Prototyping Service.<br />
Die regelmäßigen Technologie-Shuttles am <strong>IHP</strong> ermöglichen<br />
Industriepartnern, Hochschulen und anderen<br />
Forschungseinrichtungen die Präparation innovativer<br />
Entwicklungsmuster und Prototypen. Derzeit<br />
arbeiten Designer aus mehr als 50 Einrichtungen<br />
mit dem Design-Kit des <strong>IHP</strong>. Seit Januar <strong>2004</strong><br />
werden <strong>IHP</strong>-Technologien zusätzlich im Rahmen des<br />
Europractice Services angeboten. Von den derzeitigen<br />
Nutzern ist mehr als die Hälfte aus der Industrie.<br />
Mehr als zwei Drittel der Nutzer stammen aus<br />
Deutschland und Europa.<br />
5. B<strong>MB</strong>F-Projekt KOKON.<br />
In diesem B<strong>MB</strong>F-Verbundprojekt testen deutsche<br />
Automobilhersteller (DaimlerChrysler) und die Halbleiterindustrie<br />
(Bosch, Infineon und Atmel) gemeinsam<br />
die Integration und Zuverlässigkeit von Si-Millimeterwellen-Schaltkreisen<br />
(MMIC) für die Anwendung<br />
als Radar-Sende/Empfangseinheit (Anti-Kollisions-<br />
Radar, Nahbereichs-Radar) im Frequenzbereich<br />
76-81 GHz. Aufgaben des <strong>IHP</strong> in diesem Projekt<br />
sind das Design von 78-GHz-VCO (spannungsgesteuerte<br />
Oszillatoren) und die Realisierung von<br />
Hochfrequenzmessungen.<br />
Materialien für die Mikroelektronik-Technologie<br />
Die technologieorientierte Materialforschung des <strong>IHP</strong><br />
wurde im Jahr <strong>2004</strong> weiter ausgebaut. Es erfolgten inhaltliche<br />
Strukturierungen, Erweiterungen und Neuaufnahmen<br />
von Projekten. Beispiele dafür sind die Projekte<br />
zur siliziumbasierten Lichtemission sowie Projekte<br />
zur Verbindung der Mikroelektronik mit der Biologie<br />
und der Medizin.<br />
Beispiele für Ergebnisse im Jahr <strong>2004</strong> sind:<br />
1. Grundlagenuntersuchungen zu neuen Isolator-Materialien<br />
hoher Dielektrizitätskonstante auf Basis von<br />
Praseodym.<br />
Neben Praseodymoxid wurden im Rahmen eines<br />
DFG-Projektes Schichten aus Praseodym-Silikat<br />
als Isolator bzw. als Pufferschicht für Praseodymoxid<br />
entwickelt. Durch Hinzulegieren von Titan konnten<br />
die elektrischen Eigenschaften der Schichten<br />
Das Jahr <strong>2004</strong> Update <strong>2004</strong><br />
4. Worldwide use of <strong>IHP</strong> technologies by the MPW and<br />
Prototyping Service.<br />
The regular technology shuttles at <strong>IHP</strong> allow industrial<br />
partners, colleges and other research institutes<br />
to prepare innovative development samples<br />
and prototypes. Designers are currently working<br />
in more than 50 organizations with the <strong>IHP</strong> design<br />
kit. As of January <strong>2004</strong> <strong>IHP</strong> technologies have also<br />
been available in the framework of Europractice<br />
Services. More than half of the current users are<br />
from industry. More than two-thirds of the users<br />
are from Germany and Europe.<br />
5. B<strong>MB</strong>F KOKON Project.<br />
In this B<strong>MB</strong>F-cooperation project German automobile<br />
producer (DaimlerChrysler) and the semiconductor<br />
industry (Bosch, Infineon and Atmel) are jointly testing<br />
the integration and reliability of Si-millimeterwave<br />
integrated circuits (MMIC) for the application<br />
as radar transmitter/receiver units (anti-collision<br />
radar, close-range radar) in the frequency range<br />
76-81 GHz. <strong>IHP</strong>’s task in this project is the design<br />
of 78 GHz VCO (voltage-controlled oscillators) and<br />
the realization of high-frequency measurements.<br />
Materials for <strong>Microelectronics</strong> Technology<br />
In <strong>2004</strong>, the technology oriented materials research<br />
at <strong>IHP</strong> was intensifi ed. New projects commenced and<br />
the contents of others restructured and expanded. Examples<br />
of these include projects for silicon-based light<br />
emission and projects for linking microelectronics with<br />
biology and medicine.<br />
Examples of results in <strong>2004</strong> were:<br />
1. Basic research for new insulators of higher permittivity<br />
on the basis of praseodymium.<br />
Along with praseodymium oxide, layers of praseodymium<br />
silicate were developed as an insulator<br />
and as a buffer layer for praseodymium oxide in a<br />
DFG-project. By alloying titanium the electrical properties<br />
of the layers could be improved and a higher<br />
stability against atmospheric influences could be<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 13
Das Jahr <strong>2004</strong> Update <strong>2004</strong><br />
14<br />
verbessert und eine höhere Stabilität gegenüber<br />
atmosphärischen Einflüssen erreicht werden. Es<br />
wurden Schichten hergestellt, die bei einer äquivalenten<br />
Oxiddicke von 1,2 nm einen Leckstrom von<br />
nur 10 -2 A/cm 2 zeigen, der um zwei Größenordnungen<br />
kleiner ist als der für 2008 von der ITRS prognostizierte.<br />
2. Beginn einer Machbarkeitsstudie zum experimentellen<br />
Nachweis, ob und unter welchen Bedingungen<br />
es möglich ist, großflächige und defektfreie<br />
alternative Silicon-On-Insulator (SOI)-Strukturen<br />
mittels Molekularstrahlepitaxie (<strong>MB</strong>E) zu erzeugen.<br />
Im Mittelpunkt der Untersuchungen steht das System<br />
Praseodymoxid/Silizium.<br />
3. Bewertung der Eignung einer siliziumbasierten<br />
Lichtemission auf der Basis von ionenimplantierten<br />
LEDs für die optische Datenübertragung auf<br />
Schaltkreisen.<br />
Erreicht wurden Werte für die interne Quanteneffizienz<br />
bei Raumtemperatur von ca. 1% bei Bor-Implantation<br />
und 2% bei Phosphor-Implantation.<br />
Durch Einbeziehung von SiGe-Schichten soll die<br />
Wellenlänge der Lichtemission auf 1,5 µm verschoben<br />
werden. Wesentlicher Vorteil des am <strong>IHP</strong> untersuchten<br />
Verfahrens ist es, dass es kompatibel<br />
zu existierenden Silizium-Technologien ist und das<br />
der Betrieb der Lichtemitter mit Spannungen von<br />
1-2 V möglich ist.<br />
4. Beginn mit Forschungsarbeiten, welche die Verbindung<br />
elektronischer und biologischer Technologien<br />
zum Ziel haben.<br />
Es wurde mit der Arbeit an einem durch die VW-<br />
Stiftung finanzierten Verbundprojekt begonnen,<br />
das die definierte selbstorganisierte Anlagerung<br />
von Biomolekülen an Silizium-Grenzflächen untersucht.<br />
Ausserdem wurde eine Studie zum Thema<br />
„Zusammenarbeit der Materialforschung mit Biologie<br />
und Medizin“ erarbeitet.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
attained. Layers were produced which displayed a<br />
leakage current of only 10 -2 A/cm 2 with an equivalent<br />
oxide thickness of 1.2 nm; this is two magnitudes<br />
smaller than predicted by the ITRS for 2008.<br />
2. Beginning of a feasibility study to prove experimentally<br />
whether, and under what conditions, it is possible<br />
to create large area and defect-free alternative<br />
Silicon-On-Insulator (SOI) structures by means<br />
of molecular beam epitaxy (<strong>MB</strong>E). The focus of the<br />
experiment is on the praseodymium oxide/silicon<br />
system.<br />
3. Evaluation of the suitability of a silicon-based light<br />
emission on the basis of ion-implanted LEDs for the<br />
optical data transmission in integrated circuits.<br />
Values for the internal quantum efficiency at room<br />
temperature of approx. 1% with boron implantation<br />
and 2% with phosphorus implantation were obtained.<br />
By including SiGe layers, the wavelength of<br />
the light emission should be shifted to 1.5 µm. The<br />
most important advantage of the process investigated<br />
by <strong>IHP</strong> is that it is compatible with existing<br />
silicon technologies and the operation of the light<br />
emitter is possible with 1-2 volts.<br />
4. Commencement of research which aims at linking<br />
electronic and biological technologies.<br />
The work on a VW Foundation sponsored cooperation<br />
project began. The project will investigate the<br />
defi ned, self-organized deposit of biomolecules on<br />
silicon interfaces. In addition, a study on the subject<br />
“Cooperation of materials research with biology and<br />
medicine” was developed.
Das Jahr <strong>2004</strong> Update <strong>2004</strong><br />
Brandenburgs Ministerpräsident Matthias Platzeck (Mitte) bei seinem Besuch am 6. August <strong>2004</strong> mit Frankfurts Oberbürgermeister Martin<br />
Patzelt (links) und dem <strong>IHP</strong>-Geschäftsführer Prof. Dr. Wolfgang Mehr (rechts).<br />
Brandenburg’s Prime Minister Matthias Platzeck (centre) at a visit on August 6, <strong>2004</strong> along with Frankfurt’s Mayor Martin Patzelt (left)<br />
and the Director of <strong>IHP</strong>, Prof. Wolfgang Mehr (right).<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 15
Angebote und Leistungen<br />
Deliverables and Services
Multiprojekt Wafer (MPW)<br />
und Prototyping Service<br />
Das <strong>IHP</strong> bietet seinen Kunden und Partnern Zugriff auf<br />
seine leistungsfähige 0,25-µm-SiGe:C-BiCMOS-Technologien.<br />
Die Technologien sind insbesondere für Anwendungen<br />
im oberen GHz-Bereich geeignet, so z.B. für die drahtlose-<br />
und Breitbandkommunikation oder Radar. Sie<br />
bieten integrierte HBTs mit Grenzfrequenzen bis zu<br />
220 GHz und integrierte HF LDMOS Bauelemente mit<br />
Durchbruchspannungen bis zu 26 V einschließlich komplementärer<br />
Bauelemente.<br />
Verfügbar sind folgende vier Technologien:<br />
SG25H1: Eine Hochleistungs-Technologie mit npn-<br />
HBTs bis zu f T /f max = 180/220 GHz.<br />
SG25H2: Eine komplementäre Hochleistungs-Technologie<br />
mit npn-HBTs ähnlich SG25H1<br />
und zusätzlichen pnp-HBTs mit f T /f max =<br />
90/125 GHz.<br />
SG25H3: Eine Technologie mit mehreren npn-HBTs,<br />
deren Parameter von einer höheren HF<br />
Performance (f T /f max = 110/190 GHz) zu<br />
höheren Durchbruchspannungen bis zu 7 V<br />
reichen.<br />
SGB25VD: Eine kostengünstige Technologie mit mehreren<br />
npn-Transistoren mit Durchbruchspannungen<br />
bis zu 7 V. Eine Besonderheit<br />
dieser Technologie sind zusätzliche integrierte<br />
komplementäre HF LDMOS Bauelemente<br />
mit Durchbruchspannungen bis zu<br />
26 V.<br />
Die Technologiefamilie SGC25 des <strong>IHP</strong> (SGC25A,<br />
SGC25B, SGC25C) wird weiterhin genutzt, aber derzeit<br />
durch die neue Familie SG25H mit verbesserten<br />
Parametern und zusätzlichen Leistungen ersetzt.<br />
Ausserdem entwickelt das <strong>IHP</strong> eine 0,13-µm-BiCMOS-<br />
Technologie als nächste Generation.<br />
Es finden technologische Durchläufe nach einem festen,<br />
unter www.ihp-microelectronics.com verfügbaren<br />
Zeitplan statt.<br />
Angebote und<br />
Leistungen<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Multiproject Wafer (MPW)<br />
and Prototyping Service<br />
<strong>IHP</strong> offers customers and partners access to its powerful<br />
0.25 µm SiGe:C BiCMOS technologies.<br />
The technologies are suited to applications in the higher<br />
GHz bands (e.g. for wireless, broadband, radar).<br />
They offer integrated HBTs with cut-off frequencies<br />
of up to 220 GHz and RF LDMOS devices with breakdown<br />
voltages up to 26 V, including complementary<br />
devices.<br />
The following four technologies are available:<br />
Deliverables and<br />
Services<br />
SG25H1: A high-performance technology with npn-<br />
HBTs up to f T /f max = 180/220 GHz.<br />
SG25H2: A complementary high-performance technology<br />
with npn-HBTs comparable to<br />
SG25H1 and additional pnp-HBTs with<br />
f T /f max = 90/125 GHz.<br />
SG25H3: A technology with a set of npn-HBTs,<br />
ranging from a higher RF performance<br />
(f T /f max = 110/190 GHz) to higher breakdown<br />
voltages up to 7 V.<br />
SGB25VD: A cost-effective technology with a set of<br />
npn-HBTs up to a breakdown voltage of 7 V.<br />
A distinctive feature of this technology is<br />
additional integrated complementary RF<br />
LDMOS devices with breakdown voltages<br />
up to 26 V.<br />
<strong>IHP</strong>’s SGC25-family of technologies (SGC25A, SGC25B,<br />
SGC25C) is still running but is currently being replaced<br />
by the new SG25H-family with improved parameters<br />
and additional features.<br />
In addition, the <strong>IHP</strong> is developing a 0.13 µm BiCMOS<br />
technology as next generation.<br />
Runs start on a regular basis. The schedule is available<br />
at www.ihp-microelectronics.com.<br />
17
Angebote und<br />
Leistungen<br />
Ein Cadence-basiertes Design-Kit für Mischsignale ist<br />
verfügbar. Wiederverwendbare Schaltungsblöcke und<br />
IPs des <strong>IHP</strong> für die drahtlose und Breitbandkommunikation<br />
können zur Unterstützung von Kundendesigns<br />
verwendet werden.<br />
In den folgenden Tabellen sind die wesentlichen Parameter<br />
der für MPW und Prototyping angebotenen Technologien<br />
dargestellt:<br />
1. 0,25-µm-Hochleistungs-SiGe:C-BiCMOS-Technologie<br />
(SG25H1).<br />
18<br />
Bipolar Section<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
A cadence-based mixed signal design kit is available.<br />
<strong>IHP</strong>’s reusable blocks and IPs for wireless and broadband<br />
can support customer designs.<br />
Technical key-parameters of the technologies offered<br />
for MPW and Prototyping are:<br />
1. High-Performance 0.25 µm SiGe:C BiCMOS-<br />
Technology (SG25H1).<br />
Parameter Value<br />
A E<br />
0.18 x 0.84 µm 2<br />
Peak fmax 220 GHz<br />
Peak fT 180 GHz<br />
BVCE0 1.9 V<br />
VA 40<br />
�<br />
CMOS Section (0.25 µm)<br />
200<br />
Passives<br />
Deliverables and<br />
Services<br />
Core Supply Voltage 2.5 V<br />
nMOS Vth 0.6 V<br />
IDsat 540 µA/µm<br />
Ioff 3 pA/µm<br />
pMOS Vth -0.56 V<br />
IDsat 230 µA/µm<br />
Ioff 3 pA/µm<br />
MIM Capacitor 1 fF/µm2 N + Poly Resistor 210 �/[]<br />
P + Poly Resistor 280 �/[]<br />
High Poly Resistor 1600 �/[]<br />
Varactor C /C max min<br />
3<br />
Inductor Q@2.4 GHz 12 (1 nH), 6 (15 nH)<br />
Inductor Q@5.8 GHz 16 (1 nH), 10 (2 nH)
2. Komplementäre 0,25-µm-Hochleistungs-SiGe:C-<br />
BiCMOS-Technologie (SG25H2).<br />
Diese Bauelemente ersetzen den Bipolarteil von<br />
SG25H1. Der CMOS-Teil und die passiven Bauelemente<br />
sind identisch mit SG25H1.<br />
3. 0,25-µm-SiGe:C-BiCMOS-Technologie mit mehreren<br />
npn-HBTs im Bereich von hoher HF Performance<br />
bis zu höheren Durchbruchspannungen<br />
(SG25H3).<br />
Parameter High<br />
Performance<br />
Bipolar Section<br />
Die Bauelemente ersetzen den Bipolarteil von SG25H1.<br />
Der CMOS-Teil und die passiven Bauelemente sind identisch<br />
mit SG25H1.<br />
Angebote und<br />
Leistungen<br />
High<br />
Performance SHP<br />
Deliverables and<br />
Services<br />
2. Complementary High-Performance 0.25 µm<br />
SiGe:C BiCMOS (SG25H2).<br />
Parameter npn pnp<br />
Bipolar Section<br />
A E<br />
0.21 x 0.84 µm 2<br />
Peak fmax 180 GHz 125 GHz<br />
Peak fT 180 GHz 90 GHz<br />
BVCE0 1.9 V 2.5 V<br />
VA 40 30<br />
� 160 100<br />
Replaces bipolar section of SG25H1; CMOS section<br />
and passives are identical to SG25H1.<br />
3. 0.25 µm SiGe:C BiCMOS with a set of npn-HBTs,<br />
ranging from high RF performance to higher<br />
breakdown voltages (SG25H3).<br />
Medium<br />
Voltage<br />
High<br />
Voltage<br />
AE 0.21 x 0.84 µm2 0.42 x 0.84 µm2 0.21 x 0.84 µm2 0.21 x 0.84 µm2 Peak fmax 190 GHz 140 GHz 140 GHz 80 GHz<br />
Peak fT 110 GHz 120 GHz 45 GHz 25 GHz<br />
BVCE0 2.0 V 2.3 V 5 V 7 V<br />
VA 30 30 30 30<br />
� 150 150 150 150<br />
Replaces bipolar section of SG25H1; CMOS section<br />
and passives are identical to SG25H1.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 19
Angebote und<br />
Leistungen<br />
20<br />
n-LDMOS p-LDMOS<br />
n-LDMOS 23 n-LDMOS 13 n-LDMOS<br />
I10****<br />
p-LDMOS 8 p-LDMOS 12<br />
BV DSS * 26 V 16 V 11.5 V -11 V -13.5 V<br />
I ** Dsat 140 µA/µm<br />
(V = 1.5 V)<br />
GS<br />
Ileakage < 15 pA/µm<br />
(V = 20 V)<br />
DS<br />
Deliverables and<br />
Services<br />
4. 0,25-µm-SiGe:C-BiCMOS-Technologie mit Bauelementen<br />
für höhere Spannungen (SGB25VD).<br />
Die Technologie enthält neben HBTs auch komplementäre<br />
HF LDMOS Bauelemente. In den folgenden zwei<br />
Tabellen sind wichtige Parameter zusammengefaßt.<br />
140 µA/µm<br />
(V GS = 1.5 V)<br />
< 15 pA/µm<br />
(V DS = 10 V)<br />
175 µA/µm<br />
(V GS = 1.5 V)<br />
< 15 pA/µm<br />
(V DS = 8 V)<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
4. 0.25 µm SiGe:C BiCMOS with High-Voltage Devices<br />
(SGB25VD).<br />
In addition to HBTs the technology also has complementary<br />
RF LDMOS. Key parameters are summarized<br />
in the following two tables.<br />
High<br />
Performance Standard<br />
85 µA/µm<br />
(V GS = -1.5 V)<br />
< 50 pA/µm<br />
(V DS = -8 V)<br />
High<br />
Voltage<br />
Parameter<br />
Bipolar Section<br />
AE 0.5 x 0.9 µm2 Peak fmax 95 GHz 90 GHz 70 GHz<br />
Peak fT 75 GHz 45 GHz 25 GHz<br />
BVCEO 2.4 V 4.0 V 7.0 V<br />
BVCBO > 7 V > 15 V > 20 V<br />
VA >50 V >80 V >100 V<br />
�<br />
CMOS Section (0.25 µm)<br />
190<br />
Passives<br />
Core Supply Voltage 2.5 V<br />
nMOS Vth 0.61 V<br />
IDsat 570 µA/µm<br />
Ioff 3 pA/µm<br />
pMOS Vth -0.51 V<br />
IDsat 290 µA/µm<br />
Ioff 3 pA/µm<br />
MIM Capacitor 1 fF/µm2 P + Poly Resistor 310 �/[]<br />
High Poly Resistor 2000 �/[]<br />
Varactor C /C max min<br />
3<br />
Inductor Q@2.4 GHz 12 (1 nH), 6 (15 nH)<br />
Inductor Q@5.8 GHz 16 (1 nH), 10 (2 nH)<br />
90 µA/µm<br />
(V GS = -1.5 V)<br />
< 50 pA/µm<br />
(V DS = -8 V)<br />
RON 11 �mm 7 �mm 7.5 �mm 16 �mm 11.5 �mm<br />
Peak f *** max 40 GHz 43 GHz 46 GHz 21 GHz 22 GHz<br />
Peak f *** T 19 GHz 23 GHz 21 GHz 8 GHz 11 GHz<br />
*:@100 pA/µm **:@V = 5 V ***:@V = 4 V ****: substrate isolated<br />
DS DS
Design Kit<br />
Die Design Kits unterstützen eine Cadence Mischsignal-<br />
Plattform:<br />
- Design Framework II (Cadence 4.4.6)<br />
- Verhaltens-Beschreibung (Verilog HDL)<br />
- Logische Synthese und Optimierung (VHDL/HDL<br />
Compiler, Design Compiler/Synopsys, Power Compiler/Synopsys)<br />
- Test Generation/Synthetisierer/Test Compiler (Synopsys)<br />
- Simulation (RF: SpectreRF, Analog: SpectreS, Verhaltens-Beschreibung/Digital:Leapfrog/NC-Affirma/Verilog-XL/ModelSim)<br />
- Platzieren und verbinden (Silicon Ensemble und<br />
Preview)<br />
- Layout (Virtuoso Editor-Cadence)<br />
- Verifizierung (Diva and Assura: DRC/LVS/Extract/<br />
Parasitic Extraction)<br />
- ADS-Support über RFDE/RFIC mit dynamischem<br />
Link zu Cadence ist verfügbar<br />
- Ein eigenständiges ADS Kit einschließlich Momentum<br />
Substrate Layer File wird unterstützt, jedoch<br />
ohne Layout-Unterstützung.<br />
Transfer von Technologien und<br />
Technologie-Modulen<br />
Das <strong>IHP</strong> bietet den Transfer seiner 0,25-µm-BiCMOS-<br />
Technologien und Technologiemodule (HBT, LDMOS) an.<br />
Die technologischen Parameter entsprechen weitgehend<br />
den oben für MPW und Prototyping genannten.<br />
Für die Technologie SGB25VD sind ausserdem Bauelemente<br />
mit höherer als der genannten Performance<br />
verfügbar.<br />
Verfügbare Blöcke und Designs für<br />
die drahtlose und Breitbandkommunikation<br />
Zur Unterstützung von Kundendesigns bietet das <strong>IHP</strong><br />
Schaltungsblöcke und Schaltungen für Lösungen im<br />
Bereich drahtlose und Breitbandkommunikation an:<br />
Angebote und<br />
Leistungen<br />
Design Kit<br />
The design kits support a Cadence mixed signal platform:<br />
- Design Framework II (Cadence 4.4.6)<br />
- Behavioral Modeling (Verilog HDL)<br />
- Logic Synthesis and Optimization (VHDL/HDL Compiler,<br />
Design Compiler/Synopsys, Power Compiler/<br />
Synopsys)<br />
- Test Generation/Synthesizer/Test Compiler (Synopsys)<br />
- Simulation (RF: SpectreRF, Analog: SpectreS, Behavioral/Digital:<br />
Leapfrog/NC-Affi rma/Verilog-XL/<br />
ModelSim)<br />
- Place and Route (Silicon Ensemble and Preview)<br />
- Layout (Virtuoso Editor - Cadence)<br />
- Verifi cation (Diva and Assura: DRC/LVS/Extract/<br />
Parasitic Extraction)<br />
- ADS-support via RFDE/RFIC dynamic link in Cadence<br />
is available<br />
- A standalone ADS Kit including Momentum substrate<br />
layer file is supported but without layout<br />
support.<br />
Transfer of Technologies and<br />
Technology Modules<br />
Deliverables and<br />
Services<br />
<strong>IHP</strong> offers its 0.25 µm BiCMOS technologies and technology<br />
modules (HBT-Modules, LDMOS-Modules) for<br />
transfer.<br />
The technological parameters comply to a large extent<br />
with the parameters described above for MPW and<br />
Prototyping. In the case of SGB25VD, devices with a<br />
higher performance are available.<br />
Available Blocks and Designs for<br />
Wireless and Broadband<br />
To support customer designs, <strong>IHP</strong> offers a wide range<br />
of blocks and designs for wireless and broadband<br />
solutions:<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 21
Angebote und<br />
Leistungen<br />
22<br />
Deliverables and<br />
Services<br />
- Bluetooth Transceiver und Komponenten wie LNAs,<br />
Mischer, VCOs, Teiler, Prescaler, Demodulatoren,<br />
Frequenzsynthesizer und Zwischenfrequenz-Verstärker<br />
- 2,4-GHz-Single-Chip PA/LNA/RX/TX-Switch in hybrider<br />
Technologie<br />
- 5-GHz-(IEEE 802.11a, HiperLAN/2)-Single-Chip-<br />
Transceiver und Komponenten wie z.B. 5 GHz<br />
VCOs, Polyphasenfilter, Zwischenfrequenz Abwärts-<br />
Mischer, spannungsgesteuerte Verstärker, aktive<br />
Basisband-Filter, Synthesizer, I2C-Bus Interface;<br />
vollständiger Single-Chip IP-Block<br />
- UWB Pulsgenerator; UWB LNA<br />
- 24-GHz-Mischer, 24-GHz-VCO<br />
- Statische und dynamische Teilerschaltungen bis zu<br />
60-GHz; 60-GHz-LNA, PLL, Mischer und VCO<br />
- 76-GHz-LC-Oscillator<br />
- SPW (Signal Processing Worksystem) und MAT-<br />
LAB-Modelle für einen digitalen Basisband-Prozessor<br />
für ein IEEE 802.11a-konformes Modem einschliesslich<br />
der Einheiten für Synchronisation und<br />
Kanalschätzung<br />
- Designs für Basisband-Verarbeitung (Viterbi Decoder,<br />
FFT/IFFT Prozessor, CORDIC Prozessor)<br />
- Synthetisierbares VHDL Modell des kompletten<br />
IEEE 802.11a OFDM Basisband-Prozessors einschliesslich<br />
der Synchronisation und Kanalschätzung<br />
- Ein abstraktes SDL-Modell des MAC-Layer für ein<br />
IEEE 802.11a-kompatibles Modem mit Testbenches<br />
für verschiedene Anwendungs-Szenarien<br />
- Echtzeit-Implementierung des MAC-Layer für ein<br />
IEEE 802.11a-kompatibles Modem für eingebettete<br />
Anwendungen, bestehend aus einem auf MIPS-<br />
oder ARM-Prozessoren laufenden C-Programm, sowie<br />
einem speziellen Hardware-Beschleuniger<br />
- Ein abstraktes SDL-Modell der MAC-Layer für ein<br />
HiperLAN/2-kompatibles Modem mit Testbenches<br />
für verschiedene Szenarien der Implementierung<br />
- Ein abstraktes SDL-Modell für IEEE 802.15.3 und<br />
IEEE 802.15.4<br />
- 5-GHz-Link-Emulator und Entwicklungsumgebung<br />
für WLAN<br />
- TCP/IP-Prozessor einschließlich Hardware-Beschleuniger.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
- Bluetooth transceivers and components, such as<br />
LNAs, mixer, VCOs, dividers, prescalers, demodulators,<br />
frequency synthesizers, and IF amplifiers<br />
- Hybrid 2.4 GHz single-chip PA/LNA/RX/TX-switch<br />
- 5 GHz (IEEE 802.11a, HiperLAN/2) single-chip<br />
transceiver and components, such as 5 GHz VCOs,<br />
polyphase fi lters, IF down mixers, gain controlled<br />
amplifi ers, active baseband fi lters, synthesizer, and<br />
I 2 C-Bus interface; full single-chip IP block<br />
- UWB puls generator; UWB LNA<br />
- 24 GHz mixer, 24 GHz VCO<br />
- Static and dynamic divider circuits for up to 60 GHz;<br />
60 GHz LNA, PLL, mixer, VCO<br />
- 76 GHz LC-oscillator<br />
- SPW (Signal Processing Worksystem) and MATLAB<br />
models of a digital baseband processor for an IEEE<br />
802.11a compliant modem, including the synchronization<br />
and channel estimation units<br />
- Designs for baseband processing (Viterbi decoder,<br />
FFT/IFFT processor, CORDIC processor)<br />
- Synthesizable VHDL model of the complete IEEE<br />
802.11a OFDM baseband processor including synchronization<br />
and channel estimation<br />
- Abstract SDL model of MAC layer for IEEE 802.11a<br />
compliant modem with testbenches for various deployment<br />
scenarios<br />
- Realtime implementation of the MAC layer for an<br />
IEEE 802.11a compliant modem for embedded<br />
applications consisting of a C-program running on<br />
MIPS or ARM processors, and a dedicated hardware<br />
accelerator<br />
- Abstract SDL model of MAC layer for HiperLAN/2<br />
compliant modem with testbenches for various deployment<br />
scenarios<br />
- Abstract SDL model for IEEE 802.15.3 and IEEE<br />
802.15.4<br />
- 5 GHz link emulator and WLAN design/debug kit<br />
- TCP/IP-processor including hardware accelerator.
Unterstützung bei Prozess-Modulen<br />
Das <strong>IHP</strong> bietet Unterstützung bei der Realisierung spezieller<br />
Prozess-Module für Forschung und Entwicklung<br />
und für Prototyping bei geringen Volumina für Standard-Prozess-Module<br />
und Prozess-Schritte.<br />
Verfügbar sind u.a. folgende Prozess-Module:<br />
- Standard-Prozesse (Implantation, Ätzen, CMP und Abscheidung<br />
von Standard-Schichten und Schichtstapeln<br />
wie thermisches SiO , PSG, Si N , Al, TiN, W)<br />
2 3 4<br />
- Standard- und Niedertemperatur-Epitaxie (Si, Si:C,<br />
SiGe, SiGe:C)<br />
- Optische Lithographie (i-Linie und 248 nm bis hinab<br />
zu 100 nm Strukturgröße)<br />
- Verkürzte Prozessabläufe.<br />
Fehleranalyse und Diagnostik<br />
Das <strong>IHP</strong> bietet Unterstützung bei der Ausbeuteerhöhung<br />
durch Fehleranalyse mit modernen Ausrüstungen<br />
wie z.B. AES, AFM, FIB, LST, REM, SIMS, STM<br />
und TEM.<br />
Für weitere Informationen wenden Sie sich bitte an:<br />
Dr. Wolfgang Kissinger<br />
<strong>IHP</strong> GmbH<br />
Im Technologiepark 25<br />
15236 Frankfurt (Oder), Germany<br />
Email kissinger@ihp-microelectronics.com<br />
Telefon +49 335 56 25 410<br />
Telefax +49 335 56 25 222<br />
Angebote und<br />
Leistungen<br />
Process Module Support<br />
Deliverables and<br />
Services<br />
<strong>IHP</strong> offers support for advanced process modules for<br />
research and development purposes and small volume<br />
prototyping for standard process modules and process<br />
steps.<br />
Process modules available include:<br />
- Standard processes (implantation, etching, CMP<br />
and deposition of standard layers and layer stacks<br />
such as thermal SiO , PSG, Si N , Al, TiN, W)<br />
2 3 4<br />
- Standard and low-temperature epitaxy (Si, Si:C,<br />
SiGe, SiGe:C)<br />
- Optical lithography (i-line and 248 nm down to 100 nm<br />
structure size)<br />
- Short-flow processing.<br />
Failure Mode Analysis and Diagnostics<br />
<strong>IHP</strong> offers support for yield enhancement through failure<br />
mode analysis with state-of-the-art equipment,<br />
including AES, AFM, FIB, LST, SEM, SIMS, STM and<br />
TEM.<br />
For more information please contact:<br />
Dr. Wolfgang Kissinger<br />
<strong>IHP</strong> GmbH<br />
Im Technologiepark 25<br />
15236 Frankfurt (Oder), Germany<br />
Email kissinger@ihp-microelectronics.com<br />
Phone +49 335 56 25 410<br />
Fax +49 335 56 25 222<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 23
Forschung des <strong>IHP</strong><br />
<strong>IHP</strong>’s Research
Das <strong>IHP</strong> arbeitet an drei eng miteinander verbundenen<br />
Forschungsprogrammen. Gemeinsames Ziel ist<br />
die Schaffung innovativer Lösungen für Anwendungen<br />
in den Bereichen drahtlose und Breitbandkommunikation.<br />
So verfügt das Institut über eine Pilotlinie für seine<br />
eigenen Forschungs- und Entwicklungsprojekte sowie<br />
für die Präparation von Chips für Projekte und Entwicklungen<br />
Dritter. Eine weitere Besonderheit ist das vertikale<br />
Forschungskonzept des <strong>IHP</strong> unter Nutzung der<br />
zusammenhängenden und aufeinander abgestimmten<br />
Kompetenzen des Institutes auf den Gebieten System<br />
Design, Design von Hochfrequenzschaltungen, Halbleitertechnologie<br />
und Materialforschung.<br />
Die Forschung des <strong>IHP</strong> setzt ebenso auf die typischen<br />
Stärken eines Leibniz-Institutes: Sie ist charakterisiert<br />
durch eine langfristige, komplexe Arbeit, die Grundlagenforschung<br />
mit anwendungsorientierter Forschung<br />
verbindet.<br />
Die Realisierung der Forschungsprogramme erfolgt<br />
mit Hilfe eines regelmäßig aktualisierten Portfolios<br />
von Projekten. Die Aktualisierung erfolgt aufgrund inhaltlicher<br />
Erfordernisse sowie der Möglichkeiten für<br />
Kooperationen und Finanzierung. Projekte mit der Industrie<br />
und Drittmittelprojekte werden im Einklang mit<br />
den strategischen Zielen des <strong>IHP</strong> eingeworben.<br />
Im Folgenden werden wesentliche Zielstellungen der<br />
Forschungsprogramme des <strong>IHP</strong> beschrieben.<br />
Drahtloses Internet: Systeme und<br />
Anwendungen<br />
In diesem Programm werden komplexe Systeme für<br />
das drahtlose Internet in Form von Prototypen und Anwendungen<br />
untersucht und entwickelt. Ziel sind Hardware/Software-Systemlösungen<br />
auf hochintegrierten<br />
Single-Chips. Unser vertikaler Forschungsansatz zeigt<br />
sich auch in der Architektur der erarbeiteten Systeme.<br />
Im Wesentlichen optimieren wir die Wechselwirkung<br />
zwischen den Schichten und realisieren eine vertikale<br />
Migration der semantischen Elemente.<br />
Die drei Hauptforschungsrichtungen sind Systeme mit<br />
hoher Performance, Systeme mit geringem Energieverbrauch<br />
und Middleware für kontextabhängige Anwendungen.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Forschung des <strong>IHP</strong> <strong>IHP</strong>‘s Research<br />
<strong>IHP</strong> is working on three closely connected research<br />
programs. The joint objective is the creation of innovative<br />
solutions for wireless and broadband applications.<br />
The institute has a pilot line for its own research and<br />
development projects as well as for preparing chips<br />
for projects and developments of third parties. An additional<br />
speciality is <strong>IHP</strong>’s vertical research concept<br />
employing the associated and harmonized competences<br />
of the institute in the fields of system design,<br />
design of RF circuits, semiconductor technology and<br />
materials research.<br />
The research of the <strong>IHP</strong> is based on the typical<br />
strengths of a Leibniz Institute; it is dominated by<br />
long-term, complex efforts which connect basic research<br />
with application-oriented research.<br />
The realization of the programs is accomplished<br />
through a project portfolio which is regularly updated<br />
according to the content requirements as well as<br />
through opportunities for cooperations and outside<br />
funding. Industry and grant projects are acquired in<br />
such a manner as to serve the strategic goals of <strong>IHP</strong>.<br />
Significant goals of <strong>IHP</strong>’s research programs are specified<br />
below.<br />
Wireless Internet: Systems and<br />
Applications<br />
This program investigates and develops complex systems<br />
for wireless Internet as prototypes and applications<br />
with the objective to find solutions for Hardware/<br />
Software systems on highly integrated single chips.<br />
Our vertical approach is also reflected in the architecture<br />
of the addressed systems. Basically, we optimize<br />
interlayer interaction and perform vertical migrations<br />
of semantic elements.<br />
The three major directions of research are systems<br />
with high performance, systems with low power consumption<br />
and middleware systems for context sensitive<br />
applications.<br />
25
Forschung des <strong>IHP</strong> <strong>IHP</strong>‘s Research<br />
Für drahtlose Systeme mit hoher Performance ist es<br />
das Ziel, alle Funktionen eines drahtlosen PDA auf ein<br />
Chip zu integrieren. Dabei sollen Datenraten bis 1 Gbps<br />
bei Trägerfrequenzen bis zu 60 GHz erreicht werden.<br />
Die Forschung zu Systemen mit geringem Energieverbrauch<br />
hat zum Ziel, Sensornetze auf einem Chip zu<br />
realisieren. Typische Anwendungen dafür sind Body-<br />
Area Netze für medizinische Anwendungen oder Wellness.<br />
Die Forschung zu kontextabhängigen Middleware-<br />
Systemen betrifft insbesondere auch die Erhaltung<br />
der Privatsphäre und die Sicherheit bei der Nutzung<br />
mobiler Endgeräte. Darüber hinaus wird die symmetrische<br />
bzw. asymmetrische Verteilung von Ressourcen<br />
zwischen Endgeräten und Servern im Gesamtsystem<br />
untersucht.<br />
Technologieplattform für drahtlose<br />
und Breitbandkommunikation<br />
In diesem Programm sollen Technologien mit zusätzlichen<br />
Funktionen entwickelt werden, insbesondere<br />
durch die Erweiterung industrieller CMOS-Technologien<br />
mit integrierten Modulen. Die Hauptforschungsrichtungen<br />
in diesem Programm sind Technologien mit hoher<br />
Performance, kostengünstige Technologien und System-on-Chip,<br />
sowie die Sicherung des Zugriffs interner<br />
und externer Designer auf die Technologien des <strong>IHP</strong>.<br />
Die Forschung in Richtung Technologien hoher Performance<br />
zielt auf extrem schnelle SiGe:C-HBTs, einschließlich<br />
komplementärer Bauelemente und neuer<br />
Bauelementekonzepte für Anwendungen bei Frequenzen<br />
bis oberhalb 100 GHz.<br />
Zielstellung der Forschung für kostengünstige Technologien<br />
ist es, kostengünstige BiCMOS-Technologien<br />
zu entwickeln und darin zusätzliche Module wie<br />
HF LDMOS, Flash und passive Bauelemente zu integrieren.<br />
Gegenwärtig wird der Zugriff auf die 0,25-µm-<br />
BiCMOS-Technologien gesichert. Für die entsprechenden<br />
technologischen Durchläufe in der Pilotlinie in<br />
Frankfurt (Oder) existiert ein fester Zeitplan.<br />
Eine neue 0,13-µm-BiCMOS-Technologie ist in Entwicklung.<br />
26<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
The goal for high-performance wireless systems is to<br />
integrate all functionalities of a wireless PDA on a single<br />
chip. The targets are to achieve a data rate of up<br />
to 1 Gbps at carrier frequencies of up to 60 GHz.<br />
The research on systems with low energy consumption<br />
is directed towards sensor networks on single<br />
chips. Typical applications are body-area networks for<br />
health care or wellness.<br />
Research in context-sensitive middleware systems<br />
addresses privacy and security questions in using mobile<br />
devices. Moreover we investigate symmetrical and<br />
asymmetrical resource distribution between client and<br />
server parts of the overall system.<br />
Technology Platform for Wireless<br />
and Broadband<br />
The aim of this program is to develop value-added<br />
technologies, preferably BiCMOS technologies, by<br />
modular extension of industrial CMOS processes with<br />
integrated modules. The major directions of the research<br />
in this program are technologies with a high<br />
performance, low-cost technologies including systemon-chip,<br />
and the provision of technology access for internal<br />
and external designers.<br />
The research towards high-performance technologies<br />
targets ultrafast SiGe:C HBTs, including complementary<br />
devices and new device concepts, for applications<br />
at frequencies of 100 GHz and more.<br />
The aim of the research for low-cost technologies is<br />
to develop low-cost BiCMOS and to integrate additional<br />
modules such as RF LDMOS, Flash and passive<br />
devices.<br />
Access is provided to the 0.25 µm BiCMOS technologies<br />
currently available. Runs in <strong>IHP</strong>’s pilot line in<br />
Frankfurt (Oder) start on a regular basis.<br />
A new 0.13 µm SiGe:C BiCMOS technology is under<br />
development.
Materialien für die Mikroelektronik-<br />
Technologie<br />
Die Materialforschung am <strong>IHP</strong> hat die Integration neuer<br />
Materialien in die Technologie zum Ziel, um so zusätzliche<br />
oder bessere Funktionalitäten zu erreichen.<br />
Außerdem bereitet die Materialforschung neue Forschungsgebiete<br />
am <strong>IHP</strong> vor.<br />
Derzeit ist die Auswahl und Fertigung von Isolatoren<br />
hoher Dielektrizitätskonstante ein Schwerpunkt der<br />
Materialforschung am <strong>IHP</strong>. Anwendungsspezifische<br />
Entwicklungen dieser Isolatoren für MIMs (Metall Isolator<br />
Metall), Speicher und CMOS werden gemeinsam<br />
mit den Technologen des <strong>IHP</strong> bzw. mit industriellen<br />
Partnern realisiert.<br />
Eine Anzahl kleinerer Projekte wird auf neuen und aussichtsreich<br />
erscheinenden Gebieten durchgeführt. Bei<br />
erfolgversprechenden Ergebnissen werden sie mit<br />
höherer Kapazität fortgesetzt. Beispiele für derartige<br />
Forschungsgebiete sind die Integration optischer<br />
Datenübertragung in der Mikroelektronik oder die Zusammenführung<br />
der Mikroelektronik mit der Biologie<br />
oder medizinischen Anwendungen.<br />
Auf den folgenden Seiten sind ausgewählte Projekte<br />
der Forschungsprogramme des <strong>IHP</strong> beschrieben.<br />
Forschung des <strong>IHP</strong> <strong>IHP</strong>‘s Research<br />
Materials for <strong>Microelectronics</strong> Technology<br />
Materials research at <strong>IHP</strong> targets the integration of<br />
new materials into the technology to achieve additional<br />
or better functionalities. It is also geared towards the<br />
preparation of new research fields at the institute.<br />
Currently, the selection and manufacturing of insulators<br />
with high permittivity is one focal point of <strong>IHP</strong>’s<br />
materials research. Application-specific developments<br />
of these insulators for MIMs (metal insulator metal),<br />
memory and CMOS are realized together with <strong>IHP</strong>’s<br />
technology department or with industrial partners.<br />
A spectrum of smaller projects is conducted in new<br />
and promising areas. In successful cases they are<br />
then worked on with increased capacity. Examples of<br />
promising research areas include the integration of<br />
optical data transmissions in microelectronics and the<br />
combination of microelectronics with biology or medical<br />
applications.<br />
On the following pages you will find a description of selected<br />
projects from <strong>IHP</strong>’s research programs.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 27
Ausgewählte Projekte<br />
Selected Projects
Drahtloses Internet/<br />
Wireless Internet<br />
Mobile Business Engine<br />
Im Rahmen des Projektes Mobile Business Engine wird<br />
eine Middleware-Plattform entwickelt, die die Realisierung<br />
kontext-sensitiver Dienste unterstützt, die sicher<br />
sind und die Privatsphäre garantieren.<br />
Das Zusammenwachsen von Mobilkommunikation und<br />
Internet bietet die Möglichkeit, neuartige Dienste, Arbeitsabläufe<br />
und Geschäftsmodelle zu realisieren. Eine<br />
möglichst weitreichende Nutzung der sich hieraus ergebenden<br />
Möglichkeiten kann nur dann erreicht werden,<br />
wenn die Entwicklung neuartiger Dienste auf einem<br />
ausreichend hohen Abstraktionsniveau erfolgt<br />
und wenn geschäftliche sowie private Daten gegen<br />
Abhören, Verfälschen, Missbrauch etc. geschützt werden.<br />
Durch den Einsatz geeigneter kryptographischer<br />
Massnahmen ist dies möglich, doch steigt dadurch der<br />
Energieverbrauch. Der Nutzer mobiler Endgeräte ist<br />
somit i.d.R. gezwungen, sich zwischen einer sicheren<br />
Kommunikation und der möglichst langen Verfügbarkeit<br />
seines Endgerätes zu entscheiden. Dieser Konflikt<br />
kann durch den Einsatz energieeffizienter Hardwarebeschleuniger<br />
für kryptographische Verfahren gelöst<br />
werden.<br />
Um eine sichere Kommunikation gewährleisten zu können,<br />
werden symmetrische und asymmetrische Verschlüsselungsverfahren<br />
benötigt. Die symmetrischen<br />
Verfahren werden zur Verschlüsselung der Daten eingesetzt,<br />
während die asymmetrischen Verfahren zur<br />
Authentisierung der Kommunikationspartner, zur Erzeugung<br />
digitaler Unterschriften und zum Austausch<br />
von Schlüsseln für symmetrische Verfahren eingesetzt<br />
werden. Im Bereich der symmetrischen Verfahren wird<br />
der Advanced Encryption Standard (AES) genutzt. Es<br />
gibt bisher keinen erfolgreichen Angriff, so dass AES<br />
eine lange Nutzungsdauer erlaubt. Ziel der Arbeiten<br />
war es, eine AES-Implementierung mit geringem Flächenbedarf<br />
zu erarbeiten, um so geringe Fertigungskosten<br />
zu gewährleisten. Die Parameter des AES-Hardwarebeschleunigers<br />
sind in Tabelle 1 dargestellt.<br />
Die elliptische Kurven-Kryptographie (ECC) wurde als<br />
asymmetrisches Verfahren gewählt, weil hier der Rechenaufwand<br />
deutlich geringer ist als beim Einsatz<br />
Ausgewählte Projekte<br />
Drahtloses Internet<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Mobile Business Engine<br />
Selected Projects<br />
Wireless Internet<br />
The Project Mobile Business Engine is developing a<br />
middleware platform for context aware services which<br />
provides the means to ensure secure communication<br />
as well as privacy of service users.<br />
The convergence of mobile communication and Internet<br />
allows new kind of services and business models to be<br />
realized and company employees, who are working remote,<br />
to be integrated. These opportunities can be exploited<br />
fully only if new services and applications can<br />
be developed at a suffi ciently high level of abstraction.<br />
In addition, business and private data have to be protected<br />
against eavesdropping, tampering, profi ling etc.<br />
Applying cryptographic means provides such security<br />
mechanisms but it also increases the energy consumption<br />
of the mobile devices signifi cantly. Thus, the user<br />
has to decide between a convenient uptime of the mobile<br />
device and a secure communication. This confl ict<br />
can be solved applying energy effi cient hardware accelerators<br />
for cryptographic means.<br />
In order to ensure secure communication, public as<br />
well as secret key cryptography has to be applied. Secret<br />
key mechanisms are used for bulk data transfer,<br />
whereas public key approaches are used for mutual<br />
authentication, digital signatures as well as for secret<br />
key exchange. We use AES (Advanced Encryption<br />
Standard) as a secret key mechanism. Up to now there<br />
has been no known successful attack on AES, so it<br />
can be used for a reasonable period of time. Our main<br />
goal was to develop an area-efficient AES implementation<br />
in order to guarantee low manufacturing costs.<br />
Table 1 illustrates the characteristics of the AES hardware<br />
accelerator.<br />
As a public key mechanism we selected Elliptic Curve<br />
Cryptography (ECC). The computational burden that<br />
is inhibited by ECC is less than that of RSA, the most<br />
commonly used encryption and authentication algorithm.<br />
ECC provides the same level of security as RSA<br />
but with a significantly shorter key length, so ECC is<br />
well suited for application in mobile communication.<br />
The main operation in ECC is the ‘kP’ multiplication.<br />
The complexity of this multiplication can be reduced<br />
29
Ausgewählte Projekte<br />
Drahtloses Internet<br />
von RSA, dem verbreitetsten Verfahren für Verschlüsselung<br />
und Authentisierung. Außerdem bietet ECC<br />
die gleiche Sicherheit wie RSA bei deutlich kürzerer<br />
Schlüssellänge, d.h. ECC ist für den Einsatz im Mobilbereich<br />
besonders geeignet. Die wichtigste Basis-Operation<br />
ist die ‚kP’-Multiplikation. Die Komplexität dieser<br />
Operation kann mit Hilfe der Karatsuba-Methode, die<br />
i.d.R. rekursiv angewendet wird, reduziert werden. Im<br />
Rahmen des Projektes Mobile Business Engine wurde<br />
eine iterative Anwendung der Karatsuba-Methode entwickelt,<br />
die die Realisierung von Hardware-Beschleunigern<br />
mit geringem Flächenbedarf erlaubt. Das gleiche<br />
Vorgehen wurde auch für andere rekursive Verfahren,<br />
die auf dem Karatsuba-Verfahren beruhen, untersucht.<br />
Die iterativen Varianten haben einen bis zu 60 Prozent<br />
geringeren Flächenbedarf als die rekursiven Versionen.<br />
Der Energiebedarf für die Multiplikationen ist bei einigen<br />
Varianten ebenfalls um 30 Prozent geringer als bei<br />
der günstigsten rekursiven Variante. Tabelle 1 zeigt<br />
die Parameter der tatsächlich gefertigten Variante.<br />
Sowohl der AES- als auch der ECC-Hardwarebeschleuniger<br />
sind bereits am <strong>IHP</strong> gefertigt worden. Beide wurden<br />
in einen gemeinsamen Chip integriert, der darüber<br />
hinaus über eine PCMCIA- und eine CardBus-Schnittstelle<br />
zur Einbindung in mobile Endgeräte verfügt.<br />
Abb. 1 zeigt das Chipfoto. Die Parameter der beiden<br />
Hardwarebeschleuniger belegen eindeutig, dass weder<br />
die Herstellungskosten noch der Energieverbrauch<br />
einem Einsatz der Hardwarebeschleuniger in mobilen<br />
Endgeräten entgegen stehen.<br />
Abb. 1: Chipfoto des Dual Krypto Chips.<br />
Fig. 1: Chip photo of the dual crypto chip.<br />
30<br />
Selected Projects<br />
Wireless Internet<br />
AES (128bit) ECC (233bit)<br />
Throughput @ 33 MHz 42 Mbps 0.85 Mbps<br />
Power consumption @ 33 MHz 9.59 mW 56.85 mW<br />
Complexity 14.44 Kgates 27.26 Kgates<br />
Rate 100 clock cycles 9000 clock cycles<br />
Size (@ 0.25 µm technology) 1.01 mm2 2.11 mm2 Tabelle 1: Eckdaten der beiden Hardwarebeschleuniger.<br />
Table 1: Characteristics of both hardware accelerators.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
by applying the Karatsuba method. Normally the Karatsuba<br />
approach is applied recursively. In the Mobile<br />
Business Engine project we developed an iterative implementation<br />
of the Karatsuba method, which allows<br />
area efficient hardware accelerators for the ‘kP’ multiplication<br />
to be realized. We also investigated our idea<br />
for other recursive approaches which are based on the<br />
Karatsuba method. The hardware accelerators which<br />
are realized when adopting an iterative approach take<br />
up to 60 per cent less area and some versions use<br />
about 30 per cent less energy per multiplication than<br />
the recursive variants. The parameters of the manufactured<br />
version are shown in table 1.<br />
Both hardware accelerators have already been integrated<br />
into one chip, which also provides a PCMCIA<br />
and a CardBus interface for integration of the chip into<br />
mobile devices. Fig. 1 shows a photo of this chip. The<br />
characteristics of both hardware accelerators clearly<br />
indicate that neither the cost nor the energy consumption<br />
prohibits the use of hardware accelerators<br />
in mobile devices.
TCP/IP-Kommunikations-Chip<br />
Ziel des Projektes ist es, das TCP/IP-Protokoll mittels<br />
einer Hardwarelösung bei hohen Datenraten und reduziertem<br />
Stromverbrauch zu unterstützen.<br />
TCP/IP ist das zentrale Protokoll im Internet. Im Zuge<br />
der Entwicklung werden zunehmend kleinere und unterschiedlichere<br />
Geräte an das Internet angeschlossen,<br />
welche nur über geringe Energiequellen verfügen. So<br />
stellt z.B. für PDAs und Laptopcomputer das TCP/IP-<br />
Protokoll eine erhebliche Belastung der Systemressourcen<br />
dar. Mittels speziell entwickelter Hardware<br />
wird diese Last reduziert und effizienter Datentransfer<br />
bei hohen Datenraten ermöglicht. Außerdem kann<br />
man auf diese Art „dumme“ Geräte ohne eigene CPU<br />
an das Internet anschließen.<br />
Das Projekt hat hierzu einen Chip mit einer Systemarchitektur<br />
wie in Abb. 2 dargestellt entwickelt. Der Chip<br />
benötigt Schnittstellen sowohl nach oben als auch<br />
nach unten, da die mittleren Protokollschichten hier<br />
implementiert werden. Nach oben zu einer Applikation<br />
wird ein Rechner mittels CardBus angeschlossen.<br />
Nach unten, zu einem Bluetooth-Radiomodul mit MAC/<br />
PHY-Implementation wird zur Zeit eine serielle UART-<br />
Schnittstelle verwendet. Später wird diese durch einen<br />
Anschluss mit 54 Mbps an den <strong>IHP</strong>-eigenen IEEE<br />
802.11a-Chipset ersetzt werden.<br />
ISPRAM<br />
(32 kB)<br />
Abb. 2: Die Systemarchitektur des TCP/IP-Chips.<br />
Fig. 2: The system architecture of the TCP/IP chip.<br />
Ausgewählte Projekte<br />
Drahtloses Internet<br />
TCP/IP Communication Chip<br />
Selected Projects<br />
Wireless Internet<br />
The goal is to enable TCP/IP with dedicated hardware,<br />
by means of a communication chip which can support<br />
high data rates at minimal power consumption.<br />
TCP/IP is the central protocol used on the Internet.<br />
The trend is to connect smaller and more diverse devices<br />
with limited processing power and battery supplies.<br />
TCP/IP processing is a substantial load on the<br />
system resources, especially for mobile devices such<br />
as PDAs or laptops. A hardware TCP/IP processor reduces<br />
the burden while supporting data transfer at<br />
high throughput. In addition, such a hardware solution<br />
can enable a more primitive device to be developed<br />
with none or only a small CPU with Internet access in<br />
the sense of “ubiquitous computing”.<br />
For this purpose, the project developed a special chip.<br />
The system architecture is shown in Fig. 2. Since the<br />
middle layers of the protocol stack are implemented<br />
here, both an upper interface (to an application) and a<br />
lower interface (to a radio modem with the MAC/PHY<br />
layers) are needed. A CardBus interface connects a<br />
host computer to the chip. For the lower interface, a<br />
serial (UART) connection to an external Bluetooth module<br />
is currently being used. Later, a high-speed connection<br />
to the <strong>IHP</strong>-developed IEEE 802.11a chipset will<br />
allow data rates of up to 54 Mbps.<br />
EJTAG<br />
MIPS<br />
Processor<br />
Core<br />
EC<br />
A<strong>MB</strong>A-AHB APB<br />
GPIO<br />
DSPRAM<br />
(8 kB )<br />
SI Bus<br />
Bridge<br />
(Master)<br />
UART 0<br />
(Master)<br />
CardBus<br />
(Master)<br />
CardBus (Linux Host)<br />
Registers<br />
&<br />
Control<br />
Bridge<br />
Memory Controller<br />
(AHB Slave) )<br />
SRAM (32 kB)<br />
UART 1+2<br />
Check<br />
Sum1<br />
Check<br />
Sum2<br />
Serial 0 (Bluetooth RF Module)<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 31<br />
GPIO<br />
AES<br />
Serial 1+2<br />
External<br />
Memory<br />
Flash<br />
SRAM
Ausgewählte Projekte<br />
Drahtloses Internet<br />
Connector<br />
JTAG UART JPIO<br />
Diagnostic LEDs<br />
Abb. 3: Der TCP/IP-Chip als Teil eines PC-Cardsystems.<br />
Fig. 3: The TCP/IP chip as part of a PC-Card system.<br />
Der Chip basiert auf einem integrierten MIPS-Prozessor<br />
und einem A<strong>MB</strong>A-Systembus. Zwei besondere Maßnahmen<br />
reduzieren die Last auf den Prozessor und<br />
sparen somit Energie. Erstens wird die TCP-Prüfsumme<br />
in Hardware ausgeführt, wobei der Einsatz von<br />
zwei identischen Einheiten die parallele Verarbeitung<br />
von Daten über beide Schnittstellen erlaubt. Zweitens<br />
kopieren beide Schnittstellen ihre Daten zu oder von<br />
dem internen Speicher, ohne dass der Prozessor daran<br />
beteiligt ist. Damit werden alle Operationen, die die<br />
Daten direkt anfassen, in Hardware behandelt. Dem<br />
Prozessor bleiben vergleichsweise komplizierte aber<br />
weniger rechenintensive Aufgaben wie die Behandlung<br />
der TCP/IP-Header und der Verbindungsauf- und abbau.<br />
Untersuchungen an unserer TCP/IP-Implementierung<br />
haben gezeigt, dass 80% bis 90% der Energie bei<br />
diesen Schritten verbraucht wird.<br />
Der Chip wurde auch dazu entworfen, andere Entwicklungen<br />
im <strong>IHP</strong> aufzunehmen oder zu unterstützen. Ein<br />
AES-Modul aus dem Projekt Mobile Business Engine<br />
erlaubt die Verschlüsselung der übertragenen Daten.<br />
Zusätzliche periphere Schnittstellen (GPIO, UART) erlauben<br />
es, den Chip zur Entwicklung von Sensorchips<br />
einzusetzen. Zur Zeit wird der Chip als PC-Card getestet<br />
(Abb. 3).<br />
32<br />
Diagnostic<br />
Select<br />
Bluetooth<br />
Module<br />
Selected Projects<br />
Wireless Internet<br />
TCP1 – Chip<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
CardBus<br />
connector<br />
The chip is based on a MIPS processor core and an<br />
A<strong>MB</strong>A bus. To reduce the load on the processor and<br />
to save power, two features were implemented. Firstly,<br />
the TCP checksum is done using special hardware<br />
blocks. Two such blocks were implemented to allow<br />
parallel processing of data over both interfaces. Secondly,<br />
data can be copied to and from the internal<br />
SRAM directly from the upper and lower interfaces.<br />
This way, all operations which run directly over the<br />
payload of the TCP packets are handled by hardware.<br />
The processor is left with comparatively complicated<br />
but low-effort tasks, such as construction or evaluation<br />
of the TCP/IP headers, the algorithms for TCP<br />
congestion control, and connection buildup and teardown.<br />
Profiling of our own TCP/IP program has shown<br />
that 80% to 90% of the power is consumed here.<br />
The chip was also designed to support other applications<br />
within the <strong>IHP</strong>. An AES encryption module from<br />
the Mobile Business Engine project was included to allow<br />
on-the-fly encryption of data payloads. Additional<br />
external interfaces (GPIO, UART) make it possible to<br />
test sensor network applications. The chip is currently<br />
being evaluated on a PC-Card test board (Fig. 3).
Link-Emulator für das<br />
IEEE 802.11a MAC Protokoll<br />
Der Link-Emulator implementiert das Medium-Access-<br />
Control (MAC)-Protokoll des Standards IEEE 802.11a<br />
für ein drahtloses LAN auf einer PC-Steckkarte. Mehrere<br />
MAC-Module können mittels eines programmierbaren<br />
Logik-Bausteins zu einem 802.11-Netzwerk verknüpft<br />
werden. Der Logik-Baustein emuliert die physikalische<br />
Übertragungsschicht und erlaubt eine gezielte Steuerung<br />
ihres Übertragungsverhaltens. Ein solches System<br />
kann zur Entwicklung spezieller Erweiterungen<br />
des IEEE 802.11-MAC- oder PHY-Protokolls benutzt<br />
werden.<br />
Der Link-Emulator des <strong>IHP</strong> dient als Zwischenstufe bei<br />
der Entwicklung eines IEEE 802.11a-Modems im Rahmen<br />
des von der Europäischen Union geförderten Projektes<br />
WINDECT (http://www.windect.ethz.ch). Dessen<br />
Ziel ist es, Möglichkeiten für Telefonie über ein drahtloses<br />
LAN zu untersuchen und zu demonstrieren. Im<br />
Unterschied zu Voice-over-IP (VoIP) wird in WINDECT<br />
eine priorisierte HCCA-Verbindung des IEEE 802.11-<br />
Protokolls für den Telefonkanal benutzt. Dies garantiert<br />
die erforderliche Qualität des Dienstes (QoS), wobei<br />
soviel Übertragungskapazität wie möglich für den<br />
niedrig priorisierten Datentransfer des LAN verbleibt.<br />
CardBus<br />
connector<br />
<strong>IHP</strong>’s MAC-<br />
Chip<br />
1 Mbyte<br />
RAM<br />
Abb. 4: Foto des MAC-Moduls eines Link-Emulators für IEEE 802.11a.<br />
Fig. 4: Photo of the MAC module of the IEEE 802.11a link emulator.<br />
Ausgewählte Projekte<br />
Drahtloses Internet<br />
Link Emulator for the<br />
IEEE 802.11a MAC Protocol<br />
Selected Projects<br />
Wireless Internet<br />
The link emulator implements the Medium Access Control<br />
(MAC) protocol of the IEEE 802.11a wireless LAN<br />
standard on a plug-in PC card. Several MAC modules<br />
can be connected by a programmable logic device<br />
emulating the physical layer to form an 802.11 network.<br />
The PHY emulator allows for control of many<br />
PHY layer and channel properties. Such a system may<br />
be used as a development tool for special extensions<br />
of the IEEE 802.11a MAC or physical layers.<br />
<strong>IHP</strong>’s link emulator serves as an intermediate step in<br />
the development of an enhanced IEEE 802.11a modem<br />
for the WINDECT project, funded by the European Commission<br />
(http://www.windect.ethz.ch). The goal of this<br />
project is to investigate and demonstrate high-quality<br />
telephony over a wireless LAN, i.e. to unify wireless<br />
voice and data networks using only one infrastructure.<br />
In contrast to voice-over-IP (VoIP), WINDECT implements<br />
the voice stream as a prioritized HCCA connection<br />
in an IEEE 802.11a system. This guarantees the<br />
required quality of service (QoS) in bandwidth and latency<br />
for the telephony channel, leaving as much bandwidth<br />
as possible for unprioritized LAN data transfer.<br />
8 Mbyte<br />
fl ash<br />
EJTAG + UART<br />
prog. interfaces<br />
EPP connector to<br />
PHY emulator<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 33
Ausgewählte Projekte<br />
Drahtloses Internet<br />
CardBus<br />
connector <strong>IHP</strong>’s MAC-Chip RAM + Flash<br />
34<br />
Selected Projects<br />
Wireless Internet<br />
Das MAC-Protokoll ist als Hardware-Software Co-<br />
Design auf der Basis eines MIPS-4kEp-Prozessors mit<br />
integiertem Hardware-Accelerator für zeitkritische Funktionen<br />
realisiert. Der Emulator für die physikalische<br />
Übertragungsschicht wird über eine Parallel-Schnittstelle<br />
(EPP) angeschlossen. Als Schnittstelle zu den<br />
höheren Protokollschichten stehen CardBus oder PCM-<br />
CIA zur Verfügung. Der MAC-Prozessor-Chip wurde in<br />
der 0,25-µm-CMOS-Technologie des <strong>IHP</strong> hergestellt.<br />
Ein komplettes MAC-Modul, d.h. Prozessor, Speicher<br />
und Peripherie, passt auf eine Standard PC-Karte und<br />
kann in Notebook, PC oder PDA verwendet werden<br />
(Abb. 4). Ein Link-Emulator-System wurde mit grossem<br />
Erfolg bei der Entwicklung des Kommunikationssystems<br />
für das Projekt WINDECT verwendet.<br />
Abb. 5 zeigt die nächste Entwicklungsstufe der Arbeiten<br />
für das WINDECT Projekt: das Test Board für ein<br />
komplettes, IEEE 802.11a kompatibles, 5-GHz-WLAN-<br />
Modem. Es besteht aus dem MAC-Prozessor, der auch<br />
im Link-Emulator benutzt wird, jedoch erweitert um einen<br />
PHY Layer mit digitalem Basisband-Prozessor und<br />
5-GHz-Analog-Front-End.<br />
Abb. 5: Foto des Test Boards für ein IEEE 802.11a-WLAN-Modem.<br />
Fig. 5: Photo of the IEEE 802.11a WLAN Modem Test Board.<br />
<strong>IHP</strong>´s Digital<br />
Baseband Chip<br />
Baseband<br />
FPGA<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
The MAC protocol is implemented as a hardware-software<br />
co-design on the basis of a MIPS 4kEp processor<br />
with attached hardware accelerator for time-critical<br />
protocol functions. The PHY layer emulator is connected<br />
via an enhanced parallel port (EPP). Either Card-<br />
Bus or PCMCIA may be used as an interface to higher<br />
layers. A MAC chip consisting of the MIPS core with<br />
integrated hardware accelerator and interfaces was fabricated<br />
using <strong>IHP</strong>’s 0.25 µm CMOS technology. A complete<br />
MAC unit, i.e. processor, external RAM, flash and<br />
peripherals fits on a standard PC card, which can be<br />
plugged into a notebook or PDA computer (Fig. 4).<br />
The link emulator system was successfully employed<br />
during the development of the WINDECT communication<br />
system.<br />
Fig. 5 presents the next development stage within<br />
the WINDECT project – a test board for a complete<br />
5 GHz WLAN Modem complying with the IEEE 802.11a<br />
standard. It consists of the same MAC processor as<br />
used with the Link Emulator, but extended with a real<br />
PHY layer having the main components Digital Baseband<br />
Processor and 5 GHz Analog Front End.<br />
<strong>IHP</strong>´s Analog<br />
Front End Chip<br />
Antenna<br />
Connector
Infrastruktur für Funktionaltest/Functional Test Infrastructure:<br />
Agilent SOC93000 Testsystem (links/left)<br />
Accretech UF200 Wafer Prober (rechts/right)<br />
Ausgewählte Projekte<br />
Drahtloses Internet<br />
Selected Projects<br />
Wireless Internet<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 35
Ausgewählte Projekte<br />
Drahtloses Internet<br />
Integrierte Schaltkreise für<br />
60-GHz-Anwendungen<br />
36<br />
Selected Projects<br />
Wireless Internet<br />
Es werden integrierte Schaltkreise für die drahtlose<br />
Kommunikation bei 60 GHz entwickelt.<br />
Das unlizensierte 60-GHz-Band von 57 bis 64 GHz ermöglicht<br />
Kommunikation mit hohen Datenraten. Angestrebte<br />
Anwendungen sind drahtlose Netzwerke sowie<br />
Punkt-zu-Punkt Kommunikation.<br />
Silizium-Germanium-Technologie mit Transitfrequenzen<br />
über 200 GHz ist perfekt geeignet, um Technologien<br />
basierend auf Verbindungshalbleitern auf dem Gebiet<br />
der Millimeterwellenkommunikation zu ersetzen. Diese<br />
Technologie bietet eine hohe Integrationsdichte bei niedrigen<br />
Kosten. Eine vielversprechende Anwendung stellt<br />
die drahtlose Kommunikation in dem 60-GHz-ISM-Band<br />
dar. Der vorhandene IEEE 802.11a-WLAN-Standard gestattet<br />
drahtlose Kommunikation in dem 5-GHz-Band<br />
basierend auf OFDM bei moderaten Datenraten unter<br />
schwierigen Kanalbedingungen. Die Kombination eines<br />
60-GHz-OFDM-Systems für hohe Datenraten mit 802.11a<br />
würde eine perfekte Lösung für eine Vielfalt von Anwendungsszenarien<br />
darstellen. Kompatibilität eines 60-GHz-<br />
OFDM-Systems mit 802.11a ist deshalb zwingend erforderlich.<br />
Dies gestattet ferner die Wiederverwendung der<br />
Schaltkreise, welche für 5 GHz entwickelt wurden.<br />
S - Parameters (dB)<br />
20<br />
10<br />
0<br />
-10<br />
-20<br />
-30<br />
Noise Figure simulated<br />
Noise Figure minimum<br />
S11 simulated<br />
S11 measured<br />
S22 simulated<br />
S22 measured<br />
Abb. 6: Gemessene Verstärkung und Refl exion eines 60-GHz-LNA.<br />
Fig. 6: Measured gain and refl ection of 60 GHz LNA.<br />
Integrated Circuits for<br />
60 GHz-Applications<br />
30 40 50 60 70 80 90<br />
Frequency (GHz)<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Integrated circuits for wireless communications at<br />
60 GHz are developed.<br />
The unlicensed 60 GHz band from 57 to 64 GHz enables<br />
high-data-rate communications. Target applications<br />
are wireless networks and point-to-point communication.<br />
Silicon-Germanium BiCMOS technology with transit frequencies<br />
above 200 GHz is perfectly suited to replace<br />
compound semiconductor technologies in the field of<br />
millimeter-wave communication systems. This technology<br />
offers high integration at low cost. Wireless communication<br />
in the 60 GHz industrial, scientific, medical<br />
(ISM) band represents a promising application.<br />
The existing IEEE 802.11a standard for WLAN allows<br />
wireless communication in the 5 GHz band based on<br />
OFDM with moderate data rates under difficult channel<br />
conditions. The combination of a 60 GHz high data<br />
rate OFDM-system and 802.11a would represent a perfect<br />
solution for a wide range of application scenarios.<br />
Compatibility of a 60 GHz-system with 802.11a<br />
is, therefore, mandatory. It also allows the circuitry<br />
developed for 5 GHz to be re-used.<br />
S21 simulated<br />
S21 measuread
Es wurde ein Frequenzplan erdacht, der es gestattet,<br />
das Frequenzband von 60 GHz bis 61 GHz auf eine<br />
Frequenz von etwa 5 GHz herunterzumischen, um ein<br />
OFDM-System kompatibel zum IEEE Standard 802.11a<br />
zu ermöglichen. Dies erfordert einen rauscharmen Verstärker<br />
(LNA) für 60 GHz, einen Mischer und einen<br />
spannungsgesteuerten Oszillator (VCO) eingebettet<br />
in eine Phase-locked Loop (PLL), um eine stabile Frequenz<br />
von 56 GHz zu generieren. Abb. 6 zeigt die Verstärkung<br />
und die Rückwärtsisolation eines integrierten<br />
LNA in SiGe:C-BiCMOS-Technologie. Abb. 7 zeigt ein<br />
Chipfoto einer vollintegrierten PLL mit einem gemessenen<br />
Durchstimmbereich von 3,3 GHz. Das Ausgangsspektrum<br />
dieser PLL ist in Abb. 8 dargestellt.<br />
Abb. 7: Chip-Foto einer vollintegrierten 56-GHz-PLL.<br />
Fig. 7: Chip photo of fully integrated 56 GHz PLL.<br />
Ausgewählte Projekte<br />
Drahtloses Internet<br />
-10<br />
-15<br />
-20<br />
-25<br />
-30<br />
-35<br />
-40<br />
-45<br />
-50<br />
-55<br />
-60<br />
Ref Lv 1<br />
-10 dBm<br />
Delta 2 [T1]<br />
-12.98 dB<br />
200.000 000 00 KHz<br />
Selected Projects<br />
Wireless Internet<br />
A frequency plan was conceived, which allows to convert<br />
the frequency band from 60 GHz to 61 GHz to<br />
a frequency around 5 GHz to enable an OFDM system<br />
compatible to the IEEE 802.11a standard. This requires<br />
a low-noise amplifier (LNA) for 60 GHz, a downconversion<br />
mixer and a voltage-controlled oscillator<br />
(VCO) embedded in a phase-locked loop (PLL) to generate<br />
a stable frequency of 56 GHz. Fig. 6 shows the<br />
gain and the reverse isolation of an integrated LNA in<br />
SiGe:C BiCMOS technology. Fig. 7 shows a chip photo<br />
of a fully integrated PLL with a measured tuning<br />
range of 3.3 GHz. The output spectrum of this PLL is<br />
shown in Fig. 8.<br />
1 AVG<br />
RBW 30 KHz #6<br />
VBW 30 KHz<br />
SWT 5 ms Unit dBm<br />
[T1] -22.96 dBm<br />
57.34400892 GHz<br />
[T1] -12.98 dB<br />
200.00000000 KHz<br />
[T1] -12.44 dB<br />
-200.00000000 KHz<br />
Center 57.34403892 GHz<br />
150 KHz Span 1.5 MHz<br />
Date: 01.Nov.<strong>2004</strong> 11:17:54<br />
Abb. 8: Hochaufgelöstes Ausgangsspektrum einer 56-GHz-PLL.<br />
Fig. 8: High-resolution output spectrum of 56 GHz PLL.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 37<br />
1<br />
1<br />
1<br />
1<br />
2<br />
2<br />
A<br />
SGL<br />
1 SA<br />
MIX
Ausgewählte Projekte<br />
Technologieplattform<br />
Technologieplattform/<br />
Technology Platform<br />
Hochgeschwindigkeits-Bipolartransistoren<br />
Ziel des Projektes ist die Verbesserung der maximalen<br />
Leistungsfähigkeit von Hochgeschwindigkeits-npn-<br />
bzw. pnp-SiGe:C-HBTs.<br />
Auch im höchsten Leistungsniveau wird für SiGe:C-<br />
HBTs ein selektiv implantierter Kollektor verwendet,<br />
um eine lokal verstärkte Kollektordotierung zu formen,<br />
die sowohl die Basis-Kollektor-Laufzeit als auch<br />
die externe Basis-Kollektor-Kapazität reduziert. Trotz<br />
dieser Maßnahme verbrauchen konventionelle Kollektor-Anordnungen<br />
mehr Si-Fläche als nötig ist, um einen<br />
widerstandsarmen Strompfad vom aktiven Transistor<br />
zum externen Kollektorgebiet zu bilden.<br />
Wir entwickelten ein neues Kollektormodul, das die parasitäre<br />
Basis-Kollektor-Kapazität substanziell reduziert.<br />
Dies wurde durch Aushöhlen des Kollektorgebietes erreicht.<br />
Abb. 9 zeigt die neue Kollektorstruktur in einem<br />
TEM-Querschnittsbild im Vergleich mit einer schematischen<br />
Darstellung.<br />
38<br />
Base Poly<br />
STI<br />
Emitter<br />
Collector<br />
Pedestal<br />
Selected Projects<br />
Technology Platform<br />
SiGe Base<br />
Abb. 9: Querschnitt der fertigen HBT-Struktur in schematischer<br />
Darstellung (links) und als TEM-Bild (rechts).<br />
Fig. 9: Cross-sections of the fi nal HBT structure as a schematic<br />
drawing (left) and a TEM image (right).<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
High-Speed Bipolar Transistors<br />
Target of this project is to improve the maximum performance<br />
of high speed npn and pnp SiGe:C HBTs, respectively.<br />
Including the highest performance level, a selectivelyimplanted<br />
collector is used for SiGe:C HBTs to provide<br />
a locally enhanced collector doping, reducing both<br />
the base-collector transit time and the external basecollector<br />
capacitance. However, conventional collector<br />
designs consume more Si area than it is needed<br />
to form a low resistance current path from the active<br />
transistor to the external collector region.<br />
We developed a new collector module, that substantially<br />
reduces parasitic base-collector capacitances.<br />
This was achieved by an undercut of the collector region.<br />
Fig. 9 shows the novel collector structure as<br />
TEM cross-section in comparison with a schematic<br />
drawing.<br />
Emitter Base Poly<br />
SiGe Base
Im Gegensatz zu konventionellen Konstruktionen besitzt<br />
die externe, dielektrisch isolierte Basisschicht<br />
einen einkristallinen Abschnitt auf dem Isolationsgebiet.<br />
Dadurch wird es möglich, durch die Variation der<br />
Kollektorfensterweite bezüglich des Emitterfensters<br />
die HF-Leistungsfähigkeit zu optimieren, wobei man<br />
weitgehend befreit ist von der Sorge um erhöhte Leckströme<br />
an einer Facette oder einen vergrößerten Basiswiderstand.<br />
Durch Invertierung der Dotierungstypen sind auf verschiedenen<br />
Scheiben npn- und pnp-HBTs mit dem gleichen<br />
Prozessablauf hergestellt worden. Sowohl für<br />
npn- als auch für pnp-SiGe:C-HBTs konnten wir f T -Werte<br />
und CML-Gatterverzögerungszeiten (Abb. 10) demonstrieren,<br />
die die bis dahin veröffentlichten Bestwerte<br />
ihrer Klasse übertrafen.<br />
� (ps)<br />
10<br />
5<br />
pnp �V=300mV<br />
5.9 ps<br />
A E =0.175 x 0.42 µm 2<br />
A E =0.175 x 0.84 µm 2<br />
1<br />
Current per Gate (mA)<br />
<strong>IHP</strong> 2003<br />
npn<br />
3.2 ps<br />
Abb. 10: CML-Ringoszillator-Gatter-Verzögerungszeit � über Strom<br />
pro Gate für Oszillatoren bestehend aus 53 Stufen mit<br />
npn- bzw. pnp-SiGe:C-HBTs. T=300 K, |VEE|=2,5 V, differentieller<br />
Spannungshub 300 mV.<br />
Fig. 10: CML ring oscillator gate delay � vs. current per gate for<br />
oscillators consisting of 53 stages with npn and pnp<br />
SiGe:C HBTs, respectively. T=300 K, |VEE|=2.5 V, differential<br />
voltage swing 300 mV.<br />
10<br />
Ausgewählte Projekte<br />
Technologieplattform<br />
Selected Projects<br />
Technology Platform<br />
In contrast to conventional constructions, the external,<br />
dielectrically-isolated base layer has a single crystaline<br />
part on the isolation region. This allows us to<br />
optimize the RF performance by varying the collector<br />
window enclosure of the emitter window largely relieved<br />
of concerns arising from facet leakage or increasing<br />
base resistance.<br />
On different wafers, npn and pnp transistors were produced<br />
in the same flow by inverting the doping types.<br />
For both npn and pnp SiGe:C HBTs, we demonstrated<br />
peak f T values and CML gate delays (Fig. 10) that surpassed<br />
the best in class data had been reported till<br />
then.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 39
Ausgewählte Projekte<br />
Technologieplattform<br />
Integration von Hochgeschwindigkeits-SiGe:C-HBTs<br />
mit Dünnfi lm-<br />
SOI-CMOS<br />
Das Ziel des Projektes war die Entwicklung eines Verfahrens<br />
zur Integration schneller SiGe:C-Heterobipolartransistoren<br />
(HBTs) mit modernen CMOS-Technologien<br />
auf SOI-Substraten (Silicon on Insulator).<br />
Die Integration von SiGe:C-HBTs für Hochfrequenzanwendungen<br />
mit SOI-CMOS-Technologien ist ein vielversprechender<br />
Ansatz zur Realisierung von Systemlösungen<br />
für die Telekommunikation auf einem Siliziumchip<br />
(System-on-Chip). Das SOI-Substrat kann zur Verbesserung<br />
der Eigenschaften der CMOS-Feldeffekttransistoren<br />
und der passiven Schaltungskomponenten sowie<br />
zur verbesserten Isolation genutzt werden. Skalierte<br />
SOI-CMOS-Technologien erlauben die Realisierung einer<br />
steigenden Anzahl von Schaltungsfunktionen im<br />
Radiofrequenzbereich.<br />
Für viele Anwendungen im mm-Wellenbereich und für<br />
Kommunikationssysteme mit großer Bandbreite bleiben<br />
jedoch Hochgeschwindigkeits-HBTs wegen ihrer<br />
größeren Spannungsfestigkeit, ihres großen Ausgangswiderstandes,<br />
ihres geringen 1/f-Rauschens und<br />
der großen Zahl erprobter Schaltungskonzepte unverzichtbar.<br />
40<br />
Selected Projects<br />
Technology Platform<br />
Abb. 11: REM-Querschnitt eines HBTs auf SOI-Substrat. Die hochleitende<br />
Kollektor-Wanne wird im Silizium-Substrat<br />
unterhalb der vergrabenen Oxidschicht gebildet.<br />
Fig. 11: SEM cross section of an HBT on SOI substrate. The highly<br />
conductive collector well is formed in the Si substrate<br />
below the buried oxide.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Integration of High-Speed SiGe:C<br />
HBTs with Thin-Film SOI CMOS<br />
The goal of the project was to demonstrate a way<br />
to integrate high-speed SiGe:C heterojunction bipolar<br />
transistors (HBTs) with a complementary metal-oxidesemiconductor<br />
(CMOS) technology on thin-film siliconon-insulator<br />
(SOI) wafers.<br />
The integration of high-speed SiGe:C HBTs with stateof-the-art<br />
SOI CMOS technologies is a promising route<br />
to system-on-chip (SoC) applications for telecommunications.<br />
The SOI substrate can be used to enhance<br />
the performance of MOS transistors and on-chip passive<br />
circuit components, and to minimize isolation problems.<br />
Scaled SOI CMOS technologies can facilitate<br />
the implementation of an increasing number of radiofrequency<br />
(RF) functions.<br />
However, high-speed HBTs remain indispensable for<br />
many mm-wave applications and high-bandwidth communication<br />
systems due to their high voltage capability,<br />
high output resistance, low 1/f noise, and the large<br />
number of proven RF circuit concepts.<br />
f T , f max (GHz)<br />
250<br />
200<br />
150<br />
100<br />
V CE =1.5 V<br />
f max<br />
A =2x (0.21 x 0.84)µm E<br />
Collector Current (A)<br />
2<br />
50<br />
0<br />
10-5 10-4 10-3 10-2 Abb. 12: Transitfrequenz f T und maximale Oszillationsfrequenz<br />
f max in Abhängigkeit vom Kollektorstrom.<br />
Fig. 12: Transit frequency f T and maximum oscillation frequency<br />
f max vs. collector current.<br />
f T
Es wurde ein neues Integrationsverfahren für Hochgeschwindigkeits-SiGe:C-HBTs<br />
auf SOI-Substraten entwickelt.<br />
Im Gegensatz zu allen bisherigen Ansätzen<br />
ist die Leistungsfähigkeit der SiGe:C-HBTs nicht durch<br />
die geringe Silizium-Schichtdicke der CMOS-kompatiblen<br />
SOI-Substrate begrenzt. Die entscheidende Neuerung<br />
des entwickelten Verfahrens besteht in der Realisierung<br />
eines Kollektors mit geringem Widerstand in<br />
dem Si-Substrat unterhalb der Oxidschicht. Die HBTs<br />
werden in Fenstern in der Oxidschicht gefertigt, die<br />
durch selektive Siliziumepitaxie gefüllt sind (Abb. 11<br />
und 12).<br />
SiGe:C-HBTs mit Grenzfrequenzen f T = 220 GHz und<br />
f max = 230 GHz wurden realisiert (Abb. 13). Das sind<br />
die schnellsten bisher gezeigten HBTs auf CMOS-kompatiblen<br />
SOI-Substraten. Die HBTs wurden mit vollständig<br />
verarmten SOI-CMOS-Transistoren mit 90 nm Gatelänge<br />
und 25 nm Silizium-Schichtdicke integriert.<br />
HBT<br />
Collector<br />
Si substrate<br />
Abb. 13: Schematischer Querschnitt eines auf einem SOI-Wafer<br />
integrierten HBT und MOSFET.<br />
Ausgewählte Projekte<br />
Technologieplattform<br />
Selected Projects<br />
Technology Platform<br />
A new integration scheme for high-speed SiGe:C HBTs<br />
on SOI substrates was developed. In contrast to all<br />
previous approaches, the HBT performance is not<br />
limited by the small silicon thickness of the CMOScompatible<br />
SOI substrates. The key new process feature<br />
is the formation of low-resistive collectors in the<br />
silicon substrate below the buried oxide of the SOI<br />
wafer. The HBTs are fabricated in windows of the buried<br />
oxide which are filled by selective silicon epitaxy<br />
(Figs. 11 and 12).<br />
SiGe:C HBTs with f T /f max values of 220 GHz/230 GHz<br />
were achieved (Fig. 13). These are the fastest reported<br />
HBTs on CMOS-compatible SOI substrates. The<br />
HBTs were integrated with fully-depleted CMOS transistors<br />
with 90 nm gate length and 25 nm silicon thickness.<br />
MOSFET<br />
B E C S D<br />
SiGe:C base<br />
Buried Oxide<br />
Fig. 13: Schematic cross section of an HBT and a MOSFET integrated<br />
on a silicon-on-insulator wafer.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 41
Ausgewählte Projekte<br />
Technologieplattform<br />
Kostengünstiger, modularer<br />
BiCMOS-Prozess für HF-SoC<br />
Ziel dieses Projektes ist die Entwicklung und Qualifizierung<br />
eines kostengünstigen, modularen 0,25-µm-<br />
SiGe:C-BiCMOS-Prozesses, der die Herstellung von<br />
Ein-Chip-Systemen mit digitaler, analoger, gemischter<br />
und HF-Signalverarbeitung (HF-SoC) erlaubt.<br />
SiGe:C-BiCMOS wird gegenwärtig als eine der Technologien<br />
angesehen, die sich zur Herstellung von HF-SoC<br />
am besten eignen. Sie erlaubt es, modernste CMOS-<br />
Schaltungen mit bester (bipolarer) HF-Performance auf<br />
einem Chip zu kombinieren. Außerdem kann die dringende<br />
Forderung des Schaltungs- und Systementwurfs<br />
nach Verfügbarkeit weiterer Funktionen, wie Hochvolt<br />
(LDMOS) oder nichtflüchtiger Speicherung (NVM),<br />
ohne ernsthafte Integrationsprobleme erfüllt werden.<br />
Die größte Herausforderung bei der Entwicklung solcher<br />
SoC-Plattformen ist aber die Findung eines vernünftigen<br />
Kompromisses zwischen Kosten und offeriertem<br />
Bauelemente-Spektrum sowie -Parametern.<br />
Im <strong>IHP</strong> wurde der Prozeß SGB25VD entwickelt, eine kostengünstige<br />
BiCMOS-Plattform für HF-SoC-Anwendungen.<br />
Der Prozess kombiniert ein 0,25-µm-HF-CMOS-Gerüst<br />
mit einem 1-Masken SiGe:C-HBT-Modul und einem komplementären,<br />
2-Masken LDMOS-Modul. Abb. 14 zeigt ein<br />
Schema des Prozessablaufs und Tabelle 2 die wichtigsten<br />
aktiven und passiven Bauelemente, deren Fabrikation<br />
insgesamt nur 21 Maskenschritte erfordert.<br />
Die in den Abb. 15 bzw. 16 gezeigten Ausbeutedaten<br />
belegen die CMOS-VLSI- und Bipolar-MSI-Tauglichkeit<br />
42<br />
RF-CMOS Flow<br />
Shallow Trench Isolation<br />
Well Implants<br />
Gate Oxidation<br />
Gate Poly Deposition<br />
Gate Structuring<br />
Gate Spacer Formation<br />
Salicide Blocker<br />
Contact Module<br />
BEOL including:<br />
4 Al Layers (2 µm thick upper layer)<br />
MIM Module<br />
Abb. 14: SGB25VD-Prozessablauf.<br />
Fig. 14: SGB25VD process fl ow.<br />
Selected Projects<br />
Technology Platform<br />
VD Modules<br />
HBT - Module<br />
Complementary<br />
LDMOS Module<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Low-cost, Modular BiCMOS Process<br />
for RF-SoCs<br />
The aim of this project is the development and qualifi<br />
cation of a cost-optimized, modular 0.25 µm SiGe:C<br />
BiCMOS platform suitable for the fabrication of systems<br />
on-a chip with digital, analog, mixed-signal and<br />
RF functionality (RF-SoCs).<br />
SiGe:C BiCMOS is currently considered to be one of<br />
the technologies of choice for the fabrication of RF-<br />
SoCs because it allows the combination of state-ofthe-art<br />
CMOS circuitry with best (bipolar) RF performance<br />
on a single chip. Moreover, the urgent demand<br />
from circuit and system design for the modular integration<br />
of further functions, such as high-voltage<br />
(LDMOS) or non-volatile memory (NVM), can be fulfi lled<br />
without serious integration issues. However, the biggest<br />
challenge for the development of SoC platforms is to<br />
compromise device performance and functionality on the<br />
one hand, with cost, given by features such as the number<br />
of mask and process steps, yield etc., on the other.<br />
<strong>IHP</strong> has developed the process SGB25VD, a low-cost<br />
modular SiGe:C BiCMOS platform for RF-SoC applications.<br />
It combines a 0.25 µm RF-CMOS backbone with<br />
a one-mask SiGe:C HBT module and a two-mask complementary<br />
LDMOS module. Fig. 14 shows a SGB25VD<br />
process flow schematic, while table 2 summarizes the<br />
essential active and passive devices fabricated by the<br />
process using only 21 mask steps in total.<br />
Module Mask no. Devices<br />
RF-CMOS<br />
(qualified)<br />
HBT<br />
(qualified)<br />
LDMOS<br />
(under<br />
qualification)<br />
18<br />
Tabelle 2: Wesentliche SGB25VD-Bauelemente.<br />
Table 2: SGB25VD device summary.<br />
1<br />
2<br />
nMOS transistors<br />
pMOS transistors<br />
Isol. nMOS transistors<br />
MOS varactor<br />
(3.2:1 tuning range)<br />
Junction varactor<br />
Several poly resistors<br />
(6 �, 210 �, 310 �, 2 k�)<br />
MIM cap (1fF/µm2 )<br />
Predefined inductors<br />
80 GHz f / 2.4 V BV T CEO<br />
50 GHz f / 3.8 V BV T CEO<br />
30 GHz f / 7 V BV T CEO<br />
nLDMOS<br />
pLDMOS<br />
Isolated nLDMOS
1M-SRAM Wafer Yield (%)<br />
100<br />
80<br />
60<br />
40<br />
20<br />
Bit Error Count = 0 (@ 1.2-3.2V)<br />
B D<br />
A C E F<br />
G<br />
H<br />
I<br />
J<br />
K<br />
L M<br />
CMOS<br />
BiCMOS lots<br />
Lot ID (A-M)<br />
Abb. 15: Ausbeute-Trend für einen 1-Mbit-SRAM.<br />
Fig. 15: Yield trend chart for a 1 Mbit SRAM.<br />
des Prozesses als wesentliche Voraussetzungen für<br />
eine kostengünstige Herstellung von HF-SoC. Einige<br />
Ergebnisse der SGB25VD-Prozeßqualifikation sind in<br />
Abb. 17 (zur intrinsischen HBT-Zuverlässikeit) und Tabelle<br />
3 (CMOS Stress-Tests) wiedergegeben. Die Qualifizierung<br />
wesentlicher SGB25VD-Module wurde mittlerweile<br />
erfolgreich abgeschlossen. Das erlaubte es<br />
uns, den Prozess auch für externe Kunden, in direkter<br />
Kooperation oder über Europractice, freizugeben.<br />
Weitere Module, wie ein NVM mit niedrigem Energieverbrauch<br />
(siehe dazu den Flash-Beitrag in diesem<br />
Heft), ein MIM-Kondensator mit höherer Kapazitätsdichte<br />
und ein HBT mit verbesserten HF-Parametern<br />
sind in Entwicklung (Tabelle 4). Der aufgeführte HBT<br />
mit 130 GHz f T bei 2,1 V BV CEO kann dabei zusätzlich<br />
zum Standard-HBT-Portfolio produziert werden.<br />
Devices from 3 lots<br />
Pass criteria: continuity test (open, shorts)<br />
stand-by current of all blocks<br />
functionality at 4 different voltages, ...<br />
• HTOL (2.75 V, 125°C, 1 MHz, 1000 hours, 336DUTs)<br />
Test passed with 2/336 fails in different lots<br />
• Static Bake (150°C, 1000 hours, 120 DUTs)<br />
Test passed with 0/120<br />
• AATC (-65°C to 150°C, 1000 cycles, 90 DUTs)<br />
Test passed with 0/90<br />
• Pressure Cooker (121°C, 100% RH, 2 bar, 168 hours, 90 DUTs)<br />
Test passed with 0/90<br />
• EFRS (2.5 V, 125°C, 1 MHz, 48 hours, 1278 DUTs)<br />
0.4% fail (5/1278)<br />
Tabelle 3: Ergebnisse der 1-Mbit-SRAM-Stress-Tests.<br />
Table 3: 1 Mbit SRAM stress test summary.<br />
Module Mask no. Devices<br />
NVM (Flash)<br />
(1M feasibility)<br />
4 Low-power, floating<br />
gate cell memory<br />
MIM capacitor<br />
(feasibility) 0 > 1.5 fF/µm2 cap density<br />
High-f HBT T<br />
(feasibility) 1 130 GHz f / 2.1 V BV T CEO<br />
Ausgewählte Projekte<br />
Technologieplattform<br />
Yield of HBT-Arrays (%)<br />
100<br />
80<br />
60<br />
40<br />
20<br />
0<br />
50 GHz HBT<br />
vs. 80 GHz HBT<br />
vs. 30 GHz HBT<br />
Selected Projects<br />
Technology Platform<br />
only<br />
50 GHz HBT<br />
measured<br />
1 2 3 4 5 6 7 8 9 10<br />
Lot ID (1-10)<br />
Abb. 16: Ausbeute-Trend für 4-k-HBT-Arrays.<br />
Fig. 16: Yield trend chart for 4 k HBT arrays.<br />
The CMOS and bipolar yield data shown in the Figs. 15<br />
and 16 respectively demonstrate the CMOS VLSI and<br />
bipolar MSI ability of the process as essential conditions<br />
for a cost-effective fabrication of RF-SoCs. Some<br />
results of the SGB25VD process qualifi cation are given<br />
in Fig. 17 (concerning bipolar intrinsic reliability) and<br />
table 3 (CMOS stress tests). Meanwhile, the qualification<br />
of the key SGB25VD process modules was successfully<br />
completed. It allowed us to release the process<br />
not only for <strong>IHP</strong> designers but also for external<br />
customers, via direct cooperation or Europractice<br />
service. Further modules, such as a low-power NVM<br />
(for more details, see the Flash contribution of this issue),<br />
a MIM capacitor with higher cap density, or an<br />
HBT with improved RF parameters are under development<br />
(table 4). Note that the feasible, 130 GHz f T , 2.1 V<br />
BV CEO HBT can be fabricated in addition to the standard<br />
SGB25VD HBT portfolio.<br />
Lifetime (hours)<br />
10 8<br />
10 7<br />
10 6<br />
10 5<br />
10 4<br />
10 3<br />
10 2<br />
10 1<br />
1 10 100<br />
Stress Current I E (mA)<br />
Abb. 17: Stromabhängigkeit der Lebensdauer (für 10% ß-Degradation<br />
@ V BE = 0,7 V) für ein Array mit vier parallelgeschalteten<br />
80-GHz-Transistoren.<br />
Fig. 17: Current dependence of lifetime (for 10% ß-degradation<br />
@ V BE = 0.7 V) for an array of four parallel 80 GHz HBTs.<br />
Tabelle 4: In Entwicklung befi ndliche Module.<br />
Table 4: Modules under development.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 43<br />
I E @f T,max<br />
T=150°C<br />
V CB =1V<br />
11 years<br />
T=100°C
Ausgewählte Projekte<br />
Technologieplattform<br />
Integration von Flash-Speicher<br />
Das Ziel dieses Projektes ist die Demonstration einer<br />
kostengünstigen, auf einem Tunnelstrom-Schreibkonzept<br />
basierenden Prozesstechnologie zur Integration<br />
eines „embedded-Flash“-Halbleiterspeichers in<br />
einen leistungsfähigen 0,25-µm-SiGe:C-HF-BiCMOS-<br />
Prozess.<br />
Eine modulare Technologie für nichtfl üchtige Speicher,<br />
eingebettet in einen SiGe:C-HF-BiCMOS-Prozess, bietet<br />
herausragende Möglichkeiten für eine Reihe wichtiger<br />
Anwendungen auf System-Ebene. Die meisten Si-<br />
Foundries bieten „embedded Flash“-Optionen für ihre<br />
CMOS- und RF-CMOS-Prozesse an. Für SiGe:C-BiCMOS<br />
stellt es somit eine konsequente Weiterentwicklung<br />
dar, die aber noch nicht etabliert ist. Hauptanforderungen<br />
sind geringe Kosten und Leistungsverbrauch,<br />
insbesondere zur Verwendung in tragbaren Systemen.<br />
Es werden Speicher kleiner bis mittlerer Dichte benötigt<br />
(von einigen Byte, z.B. für nichtflüchtige Register,<br />
bis zu einigen Mbit, z.B. zur Speicherung von Betriebssystemen).<br />
Die Zellengröße und Zellenleistungsfähigkeit<br />
muss für solche Speicher ausreichen.<br />
Insgesamt liegen die Vorteile eines solchen Speichers<br />
in der zusätzlichen Systemfunktionalität und reduzierten<br />
Systemkosten.<br />
Es ist eine Prozesstechnologie zur Integration eines<br />
„embedded-Flash“-Speichers in die 0,25-µm-SiGe:C-HF-<br />
SoC-Technologieplattform des <strong>IHP</strong> entwickelt worden.<br />
Aufgrund der CMOS-Kompatibilität ist ein Standard-„Floating-gate“<br />
Ansatz gewählt worden. Als Mechanismus<br />
zur Programmierung der Zelle wurde leistungsarmes<br />
Fowler-Nordheim-Tunneln gewählt. Eine Konsequenz<br />
daraus ist die Anforderung, hohe Spannungen zu handhaben<br />
(+/- 6 V), was zusätzliche Hochvoltbauelemente<br />
(HV-MOS) erfordert. Die Herausforderung ist, Flash-<br />
Zellen zusammen mit HV-MOS-Bauelementen kostengünstig<br />
zu integrieren, d.h. mit wenigen zusätzlichen<br />
Maskenebenen und Prozessschritten.<br />
Der prinzipielle Prozessablauf ist in Abb. 18 zu sehen.<br />
Es werden 4 zusätzliche Masken benötigt. Einzelne Prozessschritte<br />
werden sowohl für Flash-Zellen als auch für<br />
HV-MOS- und CMOS-Bauelemente verwendet. Abb. 19<br />
zeigt eine REM-Querschnittsaufnahme einer Speicherzelle.<br />
Einzelzellen zeigen Schreibzeiten bis zu 1 µs bei<br />
Programmierung mit V prg = 16 V (+/- 8 V an Gate bzw.<br />
Well) und einem V T -Fenster von 4 V zwischen program-<br />
44<br />
Selected Projects<br />
Technology Platform<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Flash Memory Integration<br />
The goal of this project is the demonstration of a costeffective<br />
process technology for integrating an embedded<br />
flash memory based on a low power tunnel writing<br />
concept into a 0.25 µm, high-performance SiGe:C<br />
RF-BiCMOS process.<br />
A modular non-volatile-memory technology embedded<br />
into a SiGe:C RF-BiCMOS process has significant potential<br />
for a range of important system-level applications.<br />
Most Si-foundries offer optional embedded flash<br />
modules in their CMOS or RF-CMOS processes. For<br />
SiGe:C BiCMOS this is a consistent development which<br />
has not yet been established. Main requirements are<br />
cost-effectiveness and low power consumption, particularly<br />
for use in portable systems. Memories are needed<br />
ranging from small to medium density (from a few<br />
bytes, e.g. for non-volatile registers, up to a few Mbit,<br />
e.g. for operation system storage). Cell size and performance<br />
must be sufficient for these memory sizes.<br />
The overall advantages of such embedded memory<br />
integration are the added system functionality and reduced<br />
total system costs.<br />
A process technology was developed to integrate an<br />
embedded Flash memory into <strong>IHP</strong>’s 0.25 µm SiGe:C<br />
RF-SoC technology platform. For CMOS compatibility<br />
a standard floating-gate approach was chosen. Fowler-<br />
Nordheim tunneling was chosen as a cell-programming<br />
mechanism due to its intrinsic low power consumption.<br />
One consequence is the need to handle the high<br />
voltages (+/- 6 V) used for this technique, which in turn<br />
requires high-voltage (HV) devices. One challenge is to<br />
integrate the flash cells together with HV-MOS transistors<br />
at low additional cost in terms of mask count and<br />
process steps.<br />
The principle process fl ow is shown in Fig. 18. The<br />
developed fl ow requires 4 additional mask steps on<br />
top of the baseline BiCMOS fl ow while sharing process<br />
steps for fl ash-cells, HV-MOS and CMOS devices.<br />
Fig. 19 shows an SEM cross section view of one memory<br />
cell. The single cells show a writing time of as<br />
low as 1µs for programming with V prg = 16 V (+/-8 V at<br />
gate and well) and a 4 V V T -window between the written<br />
and erased state (see Fig. 20). An endurance of<br />
10 5 write and erase cycles has been demonstrated.<br />
The HV-MOS transistors show a breakdown voltage of<br />
>10 V, which is sufficient for this application.
Shallow Trench Isolation<br />
High energy P-implant<br />
nMOS, pMOS wells<br />
5nm CMOS Gate-oxide<br />
Gate poly deposition<br />
1-Mask HBT- Module<br />
Gate structuring<br />
S/D implants<br />
Backend processing<br />
Abb. 18: Prinzipieller Prozessablauf.<br />
Fig. 18: Principle process fl ow.<br />
Dual-gate-oxide wet etch<br />
(Mask 1)<br />
Floating-gate and<br />
Flash-PWELL implant<br />
(Mask 2)<br />
Floating-gate etching<br />
and HV-NWELL implant<br />
(Mask 3)<br />
Control-gate etching<br />
and HV n-LDD implant<br />
(Mask 4)<br />
miertem und gelöschtem Zustand (Abb. 20). Eine Datenwechselstabilität<br />
von 10 5 Schreib- und Löschzyklen<br />
ist gezeigt worden. Die HV-MOS Transistoren erreichen<br />
>10 V Durchbruchspannung.<br />
In Kooperation mit der Technischen Universität Kiev<br />
ist ein 1-Mbit-Demonstrator entwickelt worden, dessen<br />
prinzipielle Funktion nachgewiesen werden konnte.<br />
Die Anwendbarkeit der entwickelten Technologie für<br />
solche Speicherdichten ist somit gezeigt worden. Ein<br />
Chipfoto des Speichers ist in Abb. 21 zu sehen.<br />
Abb. 21: Chipfoto des 1-Mbit-Demonstrators, zusammen mit<br />
einer REM-Draufsicht auf das Speicherarray vor der<br />
Aufbringung der Metallebenen.<br />
Fig. 21: Micrograph of the 1 Mbit demonstrator circuit together<br />
with a top view on the memory-array before formation<br />
of the metal interconnect.<br />
Ausgewählte Projekte<br />
Technologieplattform<br />
Abb. 19: REM-Querschnittsaufnahme einer Speicherzelle.<br />
Fig. 19: SEM cross-section of a memory cell.<br />
In cooperation with the Technical University of Kiev a<br />
1 Mbit memory was designed as a demonstrator. The<br />
first devices were fabricated and the principle functionality<br />
demonstrated, thus showing the feasibility of<br />
the process for memories of this density. A micrograph<br />
of the memory is shown in Fig. 21.<br />
V t (V)<br />
3<br />
2<br />
1<br />
0<br />
-1<br />
-2<br />
-3<br />
10 -8 10 -7 10 -6 10 -5 10 -4 10 -2<br />
10 -3 10 -1<br />
Pulse Width (s)<br />
Abb. 20: Transientes Verhalten der Flash-Zelle für verschiedene<br />
Programmierspannungen.<br />
Fig. 20: Transient characteristic of a memory cell for different<br />
programming voltages.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 45<br />
+16V<br />
+14V<br />
-16V<br />
Selected Projects<br />
Technology Platform<br />
+12V<br />
-14V<br />
-12V
Ausgewählte Projekte<br />
Technologieplattform<br />
Modellierung passiver Bauelemente<br />
mit ADS Momentum<br />
Hauptziel ist die Unterstützung zukünftiger Aktivitäten<br />
der Abteilung Circuit Design im Bereich 77 GHz und später<br />
im Bereich 120 GHz. ADS Momentum ist eine 2,5-dimensionale<br />
elektromagnetische Simulationsumgebung,<br />
die in der Lage ist, das Verhalten von Metallisierungsschichten<br />
bei hohen Frequenzen zu berechnen.<br />
In HF-Schaltkreisen wirken die Metallisierungsschichten<br />
nicht nur als leitende Verbindungen, sondern bilden<br />
auch Induktivitäten, Transformatoren, Kapazitäten<br />
und Übertragungsleitungen. Diese passiven Strukturen<br />
müssen sorgfältig entworfen werden, um eine korrekte<br />
Funktion der Schaltkreise zu sichern. Mit einem festen<br />
Satz an Komponenten ist der Designer auf bestimmte<br />
Kombinationen begrenzt. Es ist wünschenswert, parametrisierte<br />
Elemente zu haben, die an die aktuellen<br />
Bedürfnisse angepasst werden können. Die Designer<br />
werden damit bei der Entwicklung von Schaltkreisen<br />
wesentlich flexibler. Abb. 22 zeigt einige Teststrukturen,<br />
die zur Bewertung der Performance von ADS Momentum<br />
genutzt werden. Ein Vergleich zwischen Messung<br />
und Simulation ist in Abb. 23 dargestellt.<br />
Für die Übertragungsleitung wird bis 60 GHz eine gute<br />
Übereinstimmung von Messungen und Simulation erreicht.<br />
Alle Induktivitäten werden bis zu ihrer Eigenresonanzfrequenz<br />
gut simuliert. Abhängig vom Design<br />
der Induktivität wurde eine gute Übereinstimmung<br />
auch darüber hinaus bis zu 30 GHz erreicht.<br />
Eine Verbesserung der Simulationsergebnisse bei Frequenzen<br />
von 77 GHz und darüber wird durch Anpas-<br />
46<br />
Selected Projects<br />
Technology Platform<br />
a) b) c)<br />
Abb. 22: Beispiele für Layouts passiver Teststrukturen: a) und b)<br />
Induktivitäten; c) mäanderförmige Leitbahn.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Passive Modeling with ADS Momentum<br />
The main goal is to support the upcoming activities of<br />
the circuit design department in the 77 GHz range and<br />
the 120 GHz range at a later stage. ADS Momentum is<br />
a 2.5D electromagnetic simulation environment that is<br />
able to predict the behavior of the metallization layers<br />
at high frequencies.<br />
In the RF circuits the metallization layers not only<br />
act as conducting connections but also form inductors,<br />
transformers, capacitors and transmission lines.<br />
These passive structures have to be designed carefully<br />
to ensure proper functioning of the circuitries. With<br />
a set of fixed components the designer is limited to<br />
certain combinations. It is desirable to have parameterized<br />
elements that can be adapted to meet current requirements,<br />
thus enabling designers to become much<br />
more flexible in circuit development. Fig. 22 shows<br />
some test structures that are used to evaluate the performance<br />
of ADS Momentum. A comparison between<br />
measurement and simulation is shown in Fig. 23.<br />
Fig. 22: Example layouts of passive test structures: a) and b)<br />
inductors; c) meandered transmission line.<br />
Good conformity of measurement and simulation is<br />
achieved for the transmission line up to 60 GHz. All inductors<br />
are well simulated up to their self-resonance<br />
frequency. Good conformity was achieved up to a maximum<br />
of 30 GHz, depending on the inductor design.<br />
An improvement of the simulation results at frequencies<br />
of 77 GHz and above is expected by trimming the<br />
substrate description file. It specifies the sequence of
sung der Modellierung der Substrateigenschaften erwartet.<br />
Sie spezifiziert die Abfolge von Isolatoren und<br />
Metallen, deren Dicke und die physikalischen Eigenschaften<br />
jeder dieser Schichten.<br />
Der Schichtstapel wird mit Hilfe der Modellierungssoftware<br />
IC-CAP optimiert. Die relative Dielektrizitätskonstante<br />
� r der Oxidschichten und des Siliziums werden<br />
angepasst, um die beste Übereinstimmung zwischen<br />
Messungen und Simulation zu erhalten. Die Leitfähigkeit<br />
der Siliziumsubstrate wird ebenfalls angepasst. Es<br />
müssen Teststrukturen entwickelt werden, die besonders<br />
empfindlich auf die angepassten Parameter, aber<br />
weniger empfindlich auf Messprobleme reagieren. Da<br />
Frequenzen sehr gut gemessen werden können, sind<br />
resonante Strukturen dafür mögliche Lösungen.<br />
PH(S21) (deg)<br />
0<br />
-30<br />
-60<br />
-90<br />
-120<br />
-150<br />
-180<br />
Measurement<br />
Simulation<br />
0 20 40 60 80 100 120<br />
Frequency (GHz)<br />
Abb. 23: Messung und Simulation einer mäanderförmigen Leitbahn.<br />
Fig. 23: Measurement and simulation of a meandered transmission<br />
line.<br />
Ausgewählte Projekte<br />
Technologieplattform<br />
Selected Projects<br />
Technology Platform<br />
insulators and metals, their thicknesses and the physical<br />
properties of each of these layers.<br />
The modeling software IC-CAP optimizes the layer<br />
stack. The relative permittivity � r of the oxide layers<br />
and silicon are tuned to get the best fit between<br />
measurement and simulation. The conductivity of the<br />
silicon substrate is also tuned. Test structures have<br />
to be developed that are particularly sensitive to the<br />
tuned parameters but less sensitive to measurement<br />
issues. Possible solutions are resonant structures,<br />
since frequencies can be measured very well.<br />
MAG(S21) (dB)<br />
1<br />
0<br />
-1<br />
-2<br />
-3<br />
-4<br />
-5<br />
Measurement<br />
Simulation<br />
0 20 40 60 80 100 120<br />
Frequency (GHz)<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 47
Ausgewählte Projekte<br />
Technologieplattform<br />
48<br />
Pilotlinie<br />
Selected Projects<br />
Technology Platform<br />
Das <strong>IHP</strong> betreibt eine Pilotlinie, die sowohl technologische<br />
Entwicklungen als auch den Zugriff auf sehr<br />
leistungsfähige und stabile Technologien für interne<br />
und externe Designer ermöglicht.<br />
Innovationen bei Technologien und Schaltkreisen erfordern<br />
eine hohe Stabilität der Prozesslinie sowie kurze<br />
Präparationszeiten bei hoher Qualität und Ausbeute.<br />
Gegenwärtig sind mehrere 0,25-µm-SiGe:C-BiCMOS-<br />
Technologien verfügbar. Sie enthalten integrierte Hetero-<br />
Bipolartransistoren mit Grenzfrequenzen bis 220 GHz<br />
und HF-LDMOS-Bauelemente mit Durchbruchspannungen<br />
bis zu 26 V, einschließlich komplementärer Bauelemente.<br />
Die Technologien sind im Kapitel „Angebote<br />
und Leistungen“ dieses Berichtes genauer beschrieben.<br />
Eine 0,13-µm-BiCMOS-Technologie wird derzeit<br />
entwickelt.<br />
Neben der Nutzung für Schaltkreis- und Systementwicklungen<br />
am <strong>IHP</strong> werden die Technologien als MPW<br />
und Prototyping Service auch externen Partnern und<br />
Kunden angeboten.<br />
Die Steuerung in der Pilot Linie basiert auf einem vollständig<br />
automatisierten System. Alle wesentlichen<br />
Prozessdaten werden in einer Datenbank bereitge-<br />
Pilotline<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
<strong>IHP</strong> is running a pilot line, enabling technological developments<br />
as well as access to very powerful and<br />
stable technologies for internal and external designers.<br />
Innovations in technologies and circuits need high pilot<br />
line stability as well as short preparation times of<br />
high quality and yield.<br />
There are currently several 0.25 µm SiGe:C BiCMOS<br />
technologies available. They offer integrated HBTs with<br />
cut-off frequencies of up to 220 GHz and RF LDMOS<br />
devices with breakdown voltages up to 26 V, including<br />
complementary devices. The technologies are described<br />
in more detail in the chapter "Deliverables and Services"<br />
of this report. A 0.13 µm BiCMOS-technology is<br />
currently under development.<br />
In addition to the use for the development of circuits<br />
and systems at the <strong>IHP</strong>, the technologies are offered<br />
as MPW and Prototyping service to external partners<br />
and customers.<br />
The workflow in the pilot line is managed by a fully automated<br />
Manufacturing Execution System. All required<br />
data from WIP (work in process) are stored in a database<br />
(Fig. 24). These data are available for management<br />
and customers.<br />
The pilot line guarantees a stable yield, typically about<br />
70% for 1 Mbit-SRAMs.<br />
For expedited lots, cycle times can be improved to a<br />
flow factor of 1.4. The flow factor is defined as the actual<br />
processing time divided by the minimum possible<br />
processing time for full BiCMOS flows.<br />
The high quality of the pilot line is documented by<br />
the annual reservice of the ISO9001:2000 certification<br />
of all technology departments without deviations<br />
(Fig. 25).<br />
Please come and visit our cleanroom.<br />
Abb. 24: Schema des Systems zur Prozess-Steuerung.<br />
Fig. 24: Schematic of the Manufacturing Execution System.
stellt, auf die sowohl das Management als auch die<br />
Nutzer Zugriff haben (Abb. 24).<br />
Die Pilotlinie garantiert eine stabile Ausbeute, z.B. ca.<br />
70% für einen 1-Mbit-SRAM.<br />
Für priorisierte Lose wird eine Durchlaufzeit erreicht,<br />
die sich lediglich um den Faktor 1,4 von der physikalischen<br />
Prozesszeit unterscheidet.<br />
Die hohe Qualität der Pilotlinie wird durch die jährliche<br />
erfolgreiche ISO-Zertifizierung 9001:2000 dokumentiert<br />
(Abb. 25).<br />
Gern laden wir Sie zu einer Besichtigung unseres Reinraumes<br />
ein.<br />
Abb. 25: DIN EN ISO9001:2000-Zertifi kat der DQS GmbH.<br />
Fig. 25: DIN EN ISO9001:2000 certificate from the German DQS<br />
society.<br />
Ausgewählte Projekte<br />
Technologieplattform<br />
Selected Projects<br />
Technology Platform<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 49
Ausgewählte Projekte<br />
Materialien<br />
Praseodymsilikat als Zwischenschicht<br />
und Gate-Dielektrikum<br />
Das <strong>IHP</strong> konzentriert sich bei der Suche nach neuen<br />
Isolatoren hoher Dielektrizitätskonstante für mikroelektronische<br />
Anwendungen auf praseodym-basierte<br />
Materialien. Dieser Artikel befasst sich mit durch<br />
Festphasenreaktion hergestelltem Praseodymsilikat<br />
als Zwischenschicht und Gate-Dielektrikum.<br />
Die untersuchten Schichtstapel wurden durch Verdampfen<br />
von metallischem Pr auf einer 1,8 nm dicken<br />
SiO 2 -Schicht hergestellt. Anschließend erfolgte eine<br />
Luftoxydation und eine Temperung in N 2 -Atmosphäre<br />
(Abb. 26). Die chemische Zusammensetzung und die<br />
Mikrostruktur wurden analysiert und durch Ab-initio-<br />
Berechnungen simuliert. Die Ergebnisse zeigen, dass<br />
die Pr-Abscheidung bei Raumtemperatur (RT) zu einer<br />
Bildung von Pr-Silizid und Pr-Oxiden führt. Die Oxidation<br />
der Struktur mit nachfolgender Temperung führt<br />
zu einem Stapel aus einem SiO 2 -basierten Puffer mit<br />
erhöhter Dielektrizitätskonstante und einer Pr-Silikatschicht<br />
mit hohem k-Wert.<br />
Die Leckstromdichte des Stapels beträgt 10 -4 A/cm 2<br />
bei einer äquivalenten Oxidschichtdicke (EOT) von<br />
1,5 nm. Die Kapazitäts-Spannungskurven zeigen eine<br />
große Verschiebung der Flachbandspannung (V FB ).<br />
Diese Verschiebung deutet auf die Anwesenheit von<br />
positiven Ladungsträgern im Stapel hin. Durch den<br />
Austausch von Aluminium durch Gold als Elektrodenmaterial<br />
wird V FB signifi kant um den Betrag von 1,3 V<br />
verkleinert. Das ist viel mehr, als man von der Differenz<br />
der Austrittsarbeiten von Al und Au (~0.9 V) erwarten<br />
würde. V FB ist somit stark von der Gate-Grenzschicht<br />
beeinflusst.<br />
Um die elektrischen Eigenschaften des Pr-Silikat/<br />
Si(001)-Systems zu optimieren, wurde eine Technik<br />
zur Verbesserung der Grenzschicht entwickelt. 1 nm Ti<br />
50<br />
Selected Projects<br />
Materials<br />
Materialien für die Mikroelektronik/<br />
Materials for <strong>Microelectronics</strong><br />
Pr<br />
SiO 2 / Si-O-N<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Praseodymium Silicate as Interface<br />
Layer and Gate Dielectric<br />
In the search for new high-k isolators for microelectronic<br />
applications <strong>IHP</strong> concentrates on praseodymiumbased<br />
materials. In this article praseodymium silicate,<br />
produced by solid-state reaction, is investigated.<br />
The stacks under investigation were prepared by evaporating<br />
metallic Pr onto 1.8 nm SiO 2 fi lm. This was<br />
followed by oxidation in air ambient and annealing in<br />
N 2 atmosphere (Fig. 26). The chemical composition<br />
and microstructure was analysed and simulated by ab<br />
initio simulations. The results indicate that Pr deposition<br />
at room temperature (RT) leads to the formation<br />
of a Pr silicide and a Pr oxide. The oxidation of the reacted<br />
structures, followed by annealing, results in a stacked<br />
dielectric composed of a SiO 2 -based buffer with<br />
an enhanced permittivity and a Pr silicate fi lm with a<br />
high dielectric constant. The leakage current density of<br />
10 -4 A/cm 2 was measured for the stacks with an equivalent<br />
oxide thickness (EOT) of 1.5 nm. The capacitance<br />
voltage traces exhibit a large fl atband voltage<br />
(Pr 2 O 3 )(SiO) x (SiO 2 ) y /PrSiON<br />
Si (001) Si (001)<br />
Abb. 26: Schematische Darstellung der Festphasenreaktion zwischen<br />
SiO 2 /Si-O-N und metallischem Pr.<br />
Fig. 26: Schematic representation of the solid-state reaction between<br />
SiO 2 /Si-O-N and metallic Pr.<br />
(V FB ) shift, indicating the presence of a positive charge<br />
in the stack. Switching away from Al contacts to Au<br />
gate electrodes introduces a signifi cant reduction of<br />
V FB by 1.3 V, which is much more than the change expected<br />
from the work function difference between Al<br />
and Au (~ 0.9 V). This is strongly affected by the gate<br />
interface.<br />
To optimize the electrical properties of the Pr silicate/<br />
Si(001) system, we have adopted an interface-engineering<br />
approach. 1 nm Ti was deposited at RT in an ultrahigh<br />
vacuum (UHV) through electron beam evapora-
wurde bei RT unter Ultra-Hochvakuum durch Elektronenstrahlverdampfen<br />
auf 2,5 nm dicke Pr-Silikat-Schichten<br />
abgeschieden. Die Filme wurden in situ für 5 Minuten<br />
im Temperaturbereich von 70 bis 880°C getempert.<br />
Der Effekt der Ti-Zugabe wurde mittels Synchrotronstrahlungs-Photoelektronenspektroskopie<br />
untersucht.<br />
Durch die Variation der Photonenanregungsenergie<br />
konnte das Tiefenprofil zerstörungsfrei untersucht<br />
werden. Diese Untersuchungen zeigen, dass durch<br />
die Temperung eine Diffusion des Ti in das Pr-Silikat<br />
aktiviert werden konnte. Es bildete sich eine homogene<br />
Schicht Pr:Ti-Silikat mit qualitativ hochwertigen<br />
elektrischen Eigenschaften, wie in Abb. 27 durch die<br />
Leckstromdichte Jg in Abhängigkeit von der äquivalenten<br />
Oxidschichtdicke (EOT) gezeigt wird. Basierend<br />
auf den Ab-initio-Berechnungen wurde ein Verfahren<br />
vorgeschlagen, wie Ti-Atome die elektrischen Eigenschaften<br />
der Grenzschicht verbessern können. Wie in<br />
Abb. 28 dargestellt, werden durch die Oxydation von<br />
Ti-Einschlüssen stress-getrappte Defekte eliminiert. Die<br />
Pr:Ti-Silikat-Schicht weist größere k-Werte als Pr-Silikat-<br />
Schichten auf, besitzt ein EOT von 1,2 nm und keine<br />
Grenzschicht-Defektzustände.<br />
Abb. 28: Durch Oxidation der Ti-Einschlüsse werden die durch Stress<br />
erzeugten Trap-Defekte verdrängt:<br />
- O wird von der defekten Grenzschicht in die Ti-Einschlüsse<br />
gezogen,<br />
- Si wird durch Ti aus dem Silikat verdrängt,<br />
- Si wächst wieder an der Grenzfl äche.<br />
(große Kugeln: Silizium, kleine Kugeln: Sauerstoff)<br />
Ausgewählte Projekte<br />
Materialien<br />
Jg (A/cm 2 )<br />
10 4<br />
10 2<br />
10 0<br />
10 -2<br />
10 -4<br />
10 -6<br />
10 -8<br />
Selected Projects<br />
Materials<br />
La silicate (Watanabe, Appl. Phys. Lett. 83, 3546(2003))<br />
Hf silicate (Watanabe, Appl. Phys. Lett. 85, 449(<strong>2004</strong>))<br />
Pr:Ti silicate (our work)<br />
Hf silicate (Punchaipetch, J. Vac. Sci. Technol. A 22, 395 (<strong>2004</strong>)<br />
Pr silicate (our work)<br />
HfSiON<br />
1.0 1.5 2.0 2.5 3.0<br />
EOT (nm)<br />
Abb. 27: Leckstromdichte Jg von Pr-Silikaten und Pr:Ti-Silikaten<br />
als Funktion der äquivalenten Oxidschichtdicke (EOT) im<br />
Vergleich zu anderen veröffentlichten Werten von Hochk-Materialien.<br />
Fig. 27: Leakage current density Jg as a function of equivalent<br />
oxide thickness (EOT) for Pr silicate and Pr:Ti silicate in<br />
comparison to values of other high-k materials published<br />
in the literature.<br />
tion on 2.5 nm thick Pr silicate layers. The fi lms were<br />
annealed in situ for 5 minutes at temperatures ranging<br />
from 70 to 880 °C. Synchrotron radiation excited photoelectron<br />
spectroscopy was applied to study the effect<br />
of Ti additives. Non-destructive depth profi ling by<br />
varying the photon excitation energy shows that annealing<br />
activates the diffusion of deposited Ti into the<br />
Pr silicate. A homogeneous Pr:Ti silicate layer is formed<br />
showing high quality electrical properties in leakage<br />
current density Jg versus equivalent oxide thickness<br />
(EOT) (Fig. 27). On the basis of ab initio calculations,<br />
a mechanism has been proposed whereby Ti atoms<br />
could improve the electrical interface properties. As<br />
shown in Fig. 28, through the oxidation of Ti inclusions,<br />
stress-trapped defects burn away. The Pr:Ti silicate layer<br />
shows higher k values in comparison to Pr silicate,<br />
no interface defect states, and an EOT of 1.2 nm.<br />
Fig. 28: Through the oxidation of Ti inclusions, stress-trapped<br />
defects burn away:<br />
- O is drawn into Ti inclusions from defected interface,<br />
- Si is expelled from silicate by Ti ejected from inclusions,<br />
- Si is re-grown at the interface.<br />
(large bullets: silicon, small bullets: oxygen)<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 51<br />
SiO 2
Ausgewählte Projekte<br />
Materialien<br />
MIM Kondensatoren mit verbesserten<br />
elektrischen Parametern<br />
Metall-Isolator-Metall (MIM)-Kondensatoren finden großes<br />
Interesse als passive Bauelemente in siliziumbasierten<br />
Schaltkreisen für Hochfrequenz- und Mischsignalanwendungen.<br />
Der Ersatz von konventionellem SiO 2<br />
und Si 3 N 4 durch Materialien hoher Dielektrizitätskonstante<br />
ist substantiell für die Reduzierung der Kondensatorfläche.<br />
Unterschiedliche Hoch-k-Materialien wie<br />
Al 2 O 3 , AlTiO x , AlTaO x , (HfO 2 ) 1-x (Al 2 O 3 ) x , HfO 2 , ZrO 2 , Y 2 O 3 ,<br />
Ta 2 O 5 und Pr 2 O 3 wurden als Kandidaten für MIM-Kondensatoren<br />
untersucht.<br />
Abb. 29: Kapazitätsdichte als Funktion der physikalischen Schichtdicke<br />
für verschiedene Hoch-k-Materialien, eingeschlossen<br />
Pr 2 O 3 und PrTi x O y . Das Ziel der ITRS ist hier und in den<br />
folgenden beiden Abbildungen ebenfalls eingezeichnet.<br />
Fig. 29: Capacitance density as a function of physical thickness<br />
for different high-k dielectrics including Pr 2 O 3 and PrTiO 3 .<br />
The goal of the ITRS is also marked here and in the<br />
following two fi gures.<br />
Wir berichten erstmalig über die Realisierung von auf<br />
einer TiN x -Metallelektrode abgeschiedenen Kondensatoren<br />
mit amorphem dielektrischem PrTi x O y und einer<br />
Al-Top-Elektrode. Die PrTi x O y -Kondensatoren wurden<br />
im thermischen Budget der Back-End-Prozesse gefertigt.<br />
Die hygroskopische Natur der Lanthanid-Oxide<br />
wie Pr 2 O 3 ist ein bekanntes Phänomen. Durch Wasserabsorbtion<br />
in Pr 2 O 3 bilden sich negative Festladungen.<br />
Die Beimengung von TiO 2 zu Pr 2 O 3 kann die Wasseraufnahme<br />
aus der Luft unterdrücken.<br />
52<br />
Capacitance Density (fF/µm 2 )<br />
20<br />
18<br />
16<br />
14<br />
12<br />
10<br />
8<br />
6<br />
4<br />
2<br />
k = 15<br />
Physical Thickness (nm)<br />
Selected Projects<br />
Materials<br />
PrTiO 3<br />
Pr 2 O 3<br />
Ta 2 O 5<br />
HfO 2<br />
ITRS <strong>2004</strong><br />
0<br />
0 10 20 30 40 50 60 70<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
MIM Capacitors with Improved Electrical<br />
Parameters<br />
Metal-insulator-metal (MIM) capacitors as passive devices<br />
in silicon radio-frequency and mixed-signal integrated<br />
circuit applications attract considerable attention.<br />
The replacement of conventional SiO 2 and Si 3 N 4<br />
by high-k dielectric materials is substantial to reduce<br />
the capacitor’s area. Recently, several high-k materials<br />
such as Al 2 O 3 , AlTiO x , AlTaO x , (HfO 2 ) 1-x (Al 2 O 3 ) x , HfO 2 ,<br />
ZrO 2 , Y 2 O 3 , Ta 2 O 5 and Pr 2 O 3 have been investigated as<br />
candidates for MIM capacitors.<br />
Leakage parameter (fA/pF*V)<br />
1000<br />
100<br />
10<br />
1<br />
0.1<br />
PrTiO PrTiO<br />
3<br />
3<br />
Pr O 2 3<br />
Pr O 2 3<br />
5 fF/µm 2<br />
Film Thickness (nm)<br />
k = 15<br />
Φ B = 0.9 eV<br />
k = 15<br />
Φ = 1.0 eV<br />
B<br />
0 10 20 30 40 50 60<br />
Abb. 30: Leckstromparameter in Abhängigkeit von der Schichtdicke.<br />
Fig. 30: Leakage parameter as a function of fi lm thickness.<br />
We are reporting for the fi rst time on the capacitor performance<br />
of amorphous PrTi x O y dielectric fi lms which<br />
were deposited on TiN x metal electrodes to form MIM<br />
structures with Al top electrodes. The PrTi x O y capacitors<br />
were fabricated within the temperature budget of<br />
the back end of line process. The hygroscopic nature<br />
is a well-known characteristic of lanthanide oxides as<br />
Pr 2 O 3 . Negative fi xed charges can be formed by water<br />
absorption of Pr 2 O 3 layers. The addition of TiO 2 into<br />
the Pr 2 O 3 matrix can suppress the water absorption<br />
from air.<br />
B<br />
ITRS <strong>2004</strong>
Die Kapazitätsdichten bei 100 kHz für verschiedene<br />
PrTi x O y -Schichtdicken sind in Abb. 29 dargestellt. Zum<br />
Vergleich sind Messpunkte anderer Hoch-k-Materialien<br />
beigefügt. Zur Bestimmung der dielektrischen<br />
Konstante wurde ein Einschicht-Kondensator-Modell,<br />
repräsentiert durch die schwarze Kurve, an die Messpunkte<br />
angepasst. Der erhaltene k-Wert für amorphe<br />
PrTi x O y -Schichten beträgt 15. Der bei 1 V bestimmte<br />
Strom-Parameter in Abhängigkeit von der Schichtdicke<br />
des PrTi x O y und Pr 2 O 3 ist in Abb. 30 dargestellt.<br />
Abb. 31 zeigt den quadratischen Kapazitäts-Spannungskoeffizienten<br />
(VCC) der PrTi x O y -MIM-Kondensatoren<br />
als Funktion der Kapazitätsdichte. Zudem sind<br />
Quadratic VCC (ppm/V 2 )<br />
10000<br />
1000<br />
100<br />
10<br />
1<br />
Voltage Linearity at 10 kHz<br />
PrTiO3 HfO2 Ta O 2 5<br />
HfO + SiO 2 2<br />
ITRS <strong>2004</strong><br />
Capacitance Density (fF/µm2 0 5 10 15<br />
)<br />
Abb. 31: Quadratischer Spannungskoeffi zient der Kapazität (VCC)<br />
als Funktion der Kapazitätsdichte für verschiedene Hochk-Materialien<br />
einschließlich PrTiO 3 .<br />
Fig. 31: Quadratic voltage coeffi cients of capacitance (VCC) as<br />
a function of capacitance density for different high-k<br />
dielectrics including PrTiO 3 .<br />
Messungen anderer Kandidaten dargestellt. Aufgrund<br />
von dielektrischen Traps nahe der Dielektrikum/Metall-<br />
Grenzschicht sind die VCCs stark frequenzabhängig.<br />
Der MIM-Kondensator mit einer PrTi x O y -Schichtdicke<br />
von 20 nm zeigt eine Kapazitätsdichte von 5 fF/µm 2<br />
und einen quadratischen Spannungskoeffizienten von<br />
1000 ppm/V 2 und kann somit Anforderungen der ITRS<br />
(International Technology Roadmap for Semiconductors)<br />
<strong>2004</strong> erfüllen.<br />
Ausgewählte Projekte<br />
Materialien<br />
Selected Projects<br />
Materials<br />
The capacitance densities at 100 kHz for various PrTi x O y<br />
layer thickness are shown in Fig. 29. Measurement<br />
points of other high-k materials are also depicted for<br />
the sake of comparison. A single layer capacitor model<br />
represented by the solid line was used to determine<br />
the dielectric constant. The received k value of<br />
amorphous PrTi x O y films is about 15. The leakage parameter<br />
determined at 1 V versus both PrTi x O y and Pr 2 O 3<br />
layer thickness are shown in Fig. 30.<br />
Fig. 31 illustrates the quadratic voltage coefficients of<br />
the capacitance (VCC) of PrTi x O y MIM capacitors as a<br />
function of the capacitance density. Moreover, results<br />
of other material candidates are presented. The VCCs,<br />
caused by bulk-dielectric traps near the dielectric/metal<br />
interface, are strongly dependent on frequency.<br />
The MIM capacitor with a PrTi x O y layer thickness of<br />
20 nm shows a capacitance density of 5 fF/µm 2 and a<br />
quadratic voltage coefficient of 1000 ppm/V 2 , which<br />
means that it can meet the requirements of the ITRS<br />
(International Technology Roadmap for Semiconductors)<br />
<strong>2004</strong>.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 53
Ausgewählte Projekte<br />
Materialien<br />
Heteroepitaktische Si/Pr 2 O 3 /Si-<br />
Strukturen<br />
Bei der rasanten Skalierung in der Mikroelektronik<br />
sind heteroepitaktische Materialsysteme von besonders<br />
großem Interesse, da gitterangepasste Systeme<br />
Funktionalität mit hoher struktureller Stabilität kombinieren.<br />
Heteroepitaktische Si/Pr 2 O 3 /Si-Strukturen<br />
sind vielversprechende Halbleiter-Isolator-Halbleiter<br />
(SIS) Stapel für zukünftige Anwendungen als Siliconon-Insulator<br />
(SOI)-Wafer oder für innovative Transistordesigns<br />
wie Multiple-Gate-Transistoren.<br />
Hier wird das Wachstum solcher Strukturen auf Si(111)<br />
mittels Molekularstrahlepitaxie (<strong>MB</strong>E) beschrieben.<br />
Das Wachstumsverhalten von Pr 2 O 3 -Schichten auf<br />
Si(111) wurde mittels Reflektion hochenergetischer<br />
Elektronen (RHEED) untersucht. Mittels Raster-Tunnel-<br />
Mikroskopie (STM) wurde die Bildung einer geschlossenen<br />
Oxidschicht visualisiert. Analysen durch Syn-<br />
chrotron Radiation-Grazing-Incidence X-ray Diffraction<br />
(SR-GIXRD) zeigen den Übergang von pseudomorphem<br />
zu volumenartigem Verhalten im ultradünnen Schichtdickenbereich<br />
< 10 nm. Dickere Oxidschichten (bis zu<br />
50 nm) wurden mittels XRD und Röntgenrefl ektometrie<br />
(XRR) untersucht, um die kristalline Qualität und die<br />
Oberflächenrauhigkeit zu bestimmen. Es wurde festgestellt,<br />
dass Pr 2 O 3 -Schichten in der hexagonal orientierten<br />
(0001)-Phase auf Si(111) wachsen. Durch eine<br />
Temperung kann aber das Oxid in die kubische Pha-<br />
54<br />
Selected Projects<br />
Materials<br />
Abb. 32: TEM-Untersuchung des heteroepitaktischen Si/Pr 2 O 3 /<br />
Si(001)-Systems: (a) Übersichtsaufnahme des Querschnittes,<br />
(b) und (c) sind hochaufgelöste TEM-Abbildungen<br />
entlang der Si-Bulk [2 ]-Richtung der Grenzfl ächen<br />
Si(111)/Pr 2 O 3 und Pr 2 O 3 /Si(111) Epischicht.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Heteroepitaxial Si/Pr 2 O 3 /Si<br />
Structures<br />
In the course of aggressive scaling in microelectronics,<br />
heteroepitaxial materials systems are of special<br />
interest because lattice matched systems combine<br />
functionality with high structural stability. Heteroepitaxial<br />
Si/Pr 2 O 3 /Si structures are promising semiconductor-insulator-semiconductor<br />
(SIS) stacks for future<br />
applications as engineered wafer materials such as<br />
silicon-on-insulator (SOI) or for innovative transistor<br />
designs, e.g. multiple gate transistors.<br />
Here, we are reporting on the molecular beam epitaxy<br />
(<strong>MB</strong>E) growth of such structures on Si(111) wafers.<br />
The growth behaviour of Pr 2 O 3 films on Si(111)<br />
was studied by reflection high energy electron diffraction<br />
(RHEED) to determine the growth mode. Scanning<br />
tunnelling microscopy (STM) was applied to visualize<br />
the formation of a closed oxide overlayer. Synchro-<br />
Fig. 32: TEM study of the heteroepitaxial Si/Pr 2 O 3 /Si(001)<br />
system: (a) Overview cross section image, (b) and (c)<br />
show highly resolved cross section TEM images along<br />
the Si bulk [2 ] direction of the Si(111) substrate/<br />
Pr 2 O 3 and Pr 2 O 3 /Si(111) epilayer interface.<br />
tron radiation-grazing incidence X-ray diffraction (SR-<br />
GIXRD) studies monitored the transition from pseudomorphism<br />
to bulk behaviour in the ultra-thin thickness<br />
regime < 10 nm. Thicker oxide layers (up to 50 nm)<br />
were studied by XRD and X-ray reflectivity (XRR) to monitor<br />
the crystalline quality and surface roughness. It<br />
was discovered that the Pr 2 O 3 film grows in the (0001)<br />
oriented hexagonal phase on Si(111) but an annealing<br />
procedure can transform the oxide in its cubic phase<br />
with (111) orientation. The Si overgrowth was carried
se mit (111)-Orientierung umgewandelt werden. Das<br />
Überwachsen mit Si wurde sowohl auf hexagonalen als<br />
auch auf kubischen Oxidfilmen durchgeführt, um den<br />
Grad der Verspannung der Si-Epischicht anzupassen.<br />
Zur Bestätigung der durch Röntgen-Diffraktrometrie<br />
erhaltenen Ergebnisse wurden TEM-Aufnahmen gemacht.<br />
Die Ergebnisse sind in Abb. 32 zusammengefasst.<br />
Abb. 32(a) zeigt eine Querrschnittsaufnahme<br />
der Si/Pr 2 O 3 /Si(111)-Heterostruktur. Die aus XRR-Messungen<br />
erhaltenen Schichtdicken zeigen eine Struktur,<br />
die aus einer 52 nm dicken Pr 2 O 3 -Schicht und einer<br />
17 nm dicken Si-Schutzschicht besteht. Man kann deutlich<br />
erkennen, dass die Pr 2 O 3 /Si(111) -Substrat-Grenzschicht<br />
sehr glatt, die Grenze zwischen der Pr 2 O 3 -<br />
Schicht und der Si-Epischicht jedoch viel rauher ist.<br />
Abb. 32(b) und 32(c) sind hochaufgelöste Gitterabbildungen<br />
der Pr 2 O 3 /Si(111)- und der Si-Epischicht/Pr 2 O 3 -<br />
Grenzschichten. Die Blickrichtung ist entlang der Si(111) in-plane Richtung, was man aus der Tatsache<br />
schließen kann, dass die Si(111)-Gitterebenen vertikal<br />
geschichtet sind. Die angrenzenden hexagonalen<br />
(0001) Pr 2 O 3 -Ebenen besitzen ebenfalls eine On-top-<br />
Stapelung in dieser Blickrichtung. Neben den bereits<br />
diskutierten Unterschieden der Grenzschicht-Rauhigkeiten<br />
zeigt sich, dass die beiden Pr 2 O 3 /Si-Grenzschichten<br />
typischerweise keine Grenzschicht-Reaktionen<br />
aufweisen.<br />
Ausgewählte Projekte<br />
Materialien<br />
Selected Projects<br />
Materials<br />
out on hexagonal as well as cubic oxide layers to tailor<br />
the degree of strain in the Si epilayer.<br />
TEM measurements were performed to corroborate the<br />
results of the X-ray diffraction studies and are summarized<br />
in Fig. 32. Fig. 32(a) shows a cross section overview<br />
image of the Si/Pr 2 O 3 /Si(111) heterostructure.<br />
Film thickness values derived from XRR fits suggested<br />
a structure composed of a 52 nm thick Pr 2 O 3 film<br />
and a 17 nm thick Si capping layer. One can clearly<br />
see that the Pr 2 O 3 /Si(111) substrate interface is very<br />
smooth and the boundary between the Pr 2 O 3 film and<br />
the Si epilayer is much rougher. Figs. 32(b) and 32(c)<br />
are highly resolved direct lattice images of the Pr 2 O 3 /<br />
Si(111) substrate and the Si epilayer/Pr 2 O 3 interfaces.<br />
The view direction is along a Si(111) in-plane direction,<br />
as can be inferred from the fact that the Si(111)<br />
lattice planes appear vertically stacked. It is noted that<br />
adjacent (0001) hex-Pr 2 O 3 planes also exhibit such ontop<br />
stacking from this line of vision. Besides the differences<br />
of the interface roughnesses already discussed,<br />
a common feature of the two Pr 2 O 3 /Si interfaces<br />
is that no sign of an interfacial reaction can be observed.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 55
Ausgewählte Projekte<br />
Materialien<br />
56<br />
Si-basierte Lichtemitter<br />
Dieser Beitrag befasst sich mit den Grundlagen für<br />
CMOS-kompatible Lichtemitter. Ziel ist die Optimierung<br />
eines Emitters, der bei � ~ 1,5 µm arbeitet und<br />
für 300 K eine Quanten-Effizienz von einigen Prozent<br />
aufweist.<br />
Die Motivation für diese Arbeiten ergibt sich aus<br />
den Grenzen des Metall-Leitbahnsystems hinsichtlich<br />
Geschwindigkeit, Verlustwärme, Signal-Übersprechen<br />
usw., weshalb bereits in einigen Jahren eine zusätzliche<br />
optische Signal-Übertragung auf dem Chip zwingend<br />
notwendig sein wird.<br />
Zur „Bandkanten-Lumineszenz bei 1,1 µm an implantierten<br />
Strukturen“ haben wir, neben der bereits in der<br />
Literatur beschriebenen B-Implantation in n-Si, auch<br />
Internal Efficiency (%)<br />
0.8<br />
0.7<br />
0.6<br />
0.5<br />
0.4<br />
0.3<br />
0.2<br />
D4<br />
BB<br />
80K<br />
300K<br />
0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25<br />
Selected Projects<br />
Materials<br />
0.1<br />
Phosphorous implant<br />
0.0<br />
50 100 150 200 250 300<br />
Temperature (K)<br />
Abb. 33: Anomalie im Temperaturverhalten der Elektrolumineszenz<br />
in einer in Durchlassrichtung gepolten LED, hergestellt<br />
durch Phosphor-Implantation in p-Silizium. Der Einsatz<br />
im Bild zeigt das Lumineszenzspektrum: Bei 300 K<br />
dominiert die Bandkantenlumineszenz (BB).<br />
Fig. 33: Anomalous T-behaviour of electroluminescence in a<br />
forward biased LED made by P-implant in p-type Si. The<br />
inset shows the luminescence spectrum: at 300 K the<br />
band-edge luminescence (BB) dominates.<br />
die P-Implantation in p-Si untersucht. Abb. 33 zeigt<br />
dafür die anormale Zunahme der Intensität der Elektro-Lumineszenz<br />
mit der Temperatur. Bisher haben wir<br />
für P-Implant eine interne Effizienz von 2% bei 300 K<br />
nachgewiesen. Unser Modell, das die eigenen Messdaten<br />
sowie Daten aus der Literatur beschreiben kann,<br />
lässt eine Verbesserung der Effizienz auf mindestens<br />
5% erwarten. Es führt die effiziente Lichtemission auf<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Si-based Light Emitters<br />
This contribution addresses the basis of CMOS compatible<br />
light-emitting devices. The goal is to optimize<br />
an emitter for � ~ 1.5 µm, which has a quantum efficiency<br />
of a few percent at 300 K.<br />
This work has been motivated by the limitations of the<br />
metal interconnect system in terms of speed, heat penalty,<br />
cross talk etc. According to these limitations,<br />
on-chip optical interconnects will become necessary<br />
within a few years.<br />
With respect to “Band-edge luminescence at 1.1 µm<br />
from implanted Si devices”, we analyzed, in addition to<br />
the B implantation in n-type Si already described in the<br />
literature, P implantation in p-type Si. Fig. 33 shows<br />
the anomalous temperature behaviour of the electroluminescence.<br />
The best value for the internal quantum<br />
efficiency at 300 K we have been able to reach so far<br />
is 2% for P implantation. We developed a model that<br />
allows us to describe the data measured on our own<br />
samples and experimental data given in the literature.<br />
As it stands, we can see the potential for increasing<br />
the efficiency to at least 5%. According to this model,<br />
the efficient light emission is a consequence of the<br />
perfection of the Si material in the vicinity of the implanted<br />
region rather than the reduction of non-radiative<br />
channels due to the strain fields of implantationinduced<br />
dislocation loops, as suggested in the literature.<br />
Furthermore, our model explains the anomalous<br />
temperature behaviour of the luminescence.<br />
An alternative for Si-based light emission is the application<br />
of “D1-band dislocation luminescence at 1.5 µm”.<br />
As shown in Fig. 34, we found that the D1 emission<br />
dominates in structures consisting of a regular dislocation<br />
network (formed by wafer bonding at MPI Halle),<br />
exhibiting an intensity which is at least 10 times<br />
higher than the intensity of the band-edge line. Accordingly,<br />
we expect that the quantum efficiency of LED<br />
structures, which have been optimized with respect<br />
to the D1 emission, might considerably exceed that of<br />
implanted structures.
PL Intensity (a.u.)<br />
15000<br />
10000<br />
5000<br />
0<br />
D1<br />
80 K<br />
140 K<br />
290 K<br />
0.8 1.0<br />
Photon Energy (eV)<br />
eine hohe Perfektion des Si in der Nachbarschaft des<br />
implantierten Gebietes zurück und nicht, wie in der<br />
Literatur angegeben, auf eine Reduzierung von nichtstrahlenden<br />
Rekombinations-Pfaden durch das Verzerrungsfeld<br />
an den implantationsinduzierten Versetzungsschleifen.<br />
Weiterhin kann es auch das anormale<br />
Temperaturverhalten erklären.<br />
Eine andere Möglichkeit für die Si-basierte Lichtemission<br />
besteht in der Nutzung der „D1-Band Versetzungs-<br />
Lumineszenz bei 1,5 µm“. Wie Abb. 34 demonstriert,<br />
konnten wir nachweisen, dass in Strukturen mit einem<br />
regulären Versetzungsnetzwerk (erzeugt durch Waferbonden<br />
am MPI Halle) die D1-Emission dominiert und<br />
mehr als zehnmal intensiver ist als die Bandkantenlinie.<br />
Dies lässt erwarten, dass die Quanten-Effizienz in LED-<br />
Strukturen, die auf D1-Emission optimiert sind, die von<br />
implantierten Strukturen deutlich übersteigen sollte.<br />
Intensity (a.u.)<br />
60<br />
50<br />
40<br />
30<br />
20<br />
10<br />
0<br />
80k<br />
Ausgewählte Projekte<br />
Materialien<br />
D1<br />
D2<br />
D3 D4<br />
0.7 0.8 0.9<br />
Energy (eV)<br />
1.0 1.1 1.2<br />
BB<br />
(BB)<br />
Selected Projects<br />
Materials<br />
Abb. 34: Photolumineszenz-Spektrum einer Si-Struktur mit einem<br />
durch Waferbonden hergestellten Versetzungsnetzwerk<br />
200 nm parallel zur Oberfl äche. Die D1-Emission dominiert<br />
im analysierten Bereich von 80-290 K. Im kleinen<br />
Bild ist zum Vergleich ein typisches Spektrum von<br />
Silizium mit Versetzungen.<br />
Fig. 34: Photoluminescence spectrum of a Si structure with a dislocation<br />
network 200 nm parallel to the surface, formed<br />
by wafer bonding. The D1 emission dominates in the<br />
analyzed range of 80-290 K. See the inset showing a<br />
typical spectrum of dislocated Si for comparison.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 57
Gemeinsames Labor <strong>IHP</strong>/BTU<br />
<strong>IHP</strong>/BTU Joint Lab
Das Gemeinsame Labor <strong>IHP</strong>/BTU auf dem Campus der<br />
Brandenburgischen Technischen Universität in Cottbus<br />
wurde im Jahre 2000 mit dem Hauptziel gegründet, die<br />
Forschungspotentiale beider Partner zu bündeln und<br />
leistungsfähige überkritische Potentiale für anspruchsvolle<br />
interdisziplinäre Forschungen zu schaffen.<br />
An den Arbeiten, die auf moderne Halbleitermaterialien,<br />
Halbleitertechnologien und den Schaltungs- und<br />
Systementwurf ausgerichtet sind, beteiligen sich seitens<br />
der BTU vor allem die Lehrstühle<br />
- Experimentalphysik/Materialwissenschaften<br />
- Theoretische Physik<br />
- Physikalische Chemie<br />
- Systeme<br />
- Mikroelektronik<br />
Bund und Land Brandenburg fördern im Rahmen des<br />
Hochschul- und Wissenschaftsprogramms im Gemeinsamen<br />
Labor den Aufbau eines Kompetenzzentrums<br />
für Halbleitermaterialien und -technologien.<br />
Ausgehend von einer Analyse der künftigen Entwicklung<br />
der Halbleiterelektronik und der Ausrichtung des <strong>IHP</strong><br />
wurden in <strong>2004</strong> folgende Arbeitsrichtungen als langfristige<br />
Forschungsschwerpunkte herausgearbeitet:<br />
- Advanced Silicon (Silicium für zukünftige Halbleitertechnologien<br />
und -schaltungen)<br />
- Hoch-k-Materialien (neue Dielektrika für die Nanoelektronik)<br />
- Kopplung Halbleiteroberfl äche – biologische Medien<br />
- Optische Datenübertragung auf dem Chip<br />
- Quantenbauelemente<br />
- Diagnostik für Material- und Technologieentwicklung<br />
des <strong>IHP</strong>.<br />
Die Forschungsarbeiten sind überwiegend grundlagenorientiert<br />
und haben ausgeprägten Vorlaufcharakter.<br />
Durch die enge Kopplung mit dem <strong>IHP</strong> besteht dabei<br />
die einzigartige Chance, neue Erkenntnisse bis zu anwendungsreifen<br />
Lösungen zu führen. Als aussichtsreich<br />
sind besonders die Arbeiten zu Si-basierten Lichtemittern<br />
und Quantenbauelementen hervorzuheben.<br />
Gemeinsames Labor<br />
<strong>IHP</strong>/BTU<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
The <strong>IHP</strong>/BTU Joint Lab, located on the campus of the<br />
Technical University of Brandenburg Cottbus, was<br />
founded in 2000. The main objective was to bundle<br />
the research resources of both partners and to establish<br />
capable supercritical potentials for ambitious interdisciplinary<br />
research.<br />
The research work ranges from modern semiconductor<br />
materials and technologies to the design of circuits<br />
and systems. The following chairs of the BTU Cottbus<br />
are involved:<br />
- Experimental Physics/Materials Science<br />
- Theoretical Physics<br />
- Physical Chemistry<br />
- Systems<br />
- <strong>Microelectronics</strong><br />
<strong>IHP</strong>/BTU Joint Lab<br />
The federal government and the State of Brandenburg<br />
support the development of a center of competency<br />
for semiconductor materials and technologies at the<br />
Joint Lab within the framework of their University and<br />
Science Program.<br />
Based on an analysis of future trends in the development<br />
of semiconductor electronics and <strong>IHP</strong>’s research<br />
focus, the following topics were identified in <strong>2004</strong> as<br />
prospective long-term research directions:<br />
- Advanced Silicon (silicon for future technologies<br />
and circuits)<br />
- High-k materials (new dielectrics for nanoelectronics)<br />
- Linkage between semiconductor surface and biomedia<br />
- On-chip optical data transmission<br />
- Quantum devices<br />
- Diagnostics support for <strong>IHP</strong> materials and technologies.<br />
The research conducted is predominantly fundamental<br />
and has a distinct search character. The close link<br />
to <strong>IHP</strong>’s capabilities provides a unique opportunity to<br />
generate implementable solutions from new scientific<br />
insights. Si-based light emitters and quantum devices<br />
are among promising research topics.<br />
59
Gemeinsames Labor<br />
<strong>IHP</strong>/BTU<br />
Allein zu Halbleitermaterialien und -technologien sind<br />
im laufenden Jahr 16 Publikationen entstanden, 33 Vorträge<br />
– darunter 9 eingeladene – gehalten und 2 Patente<br />
angemeldet worden.<br />
Für die laufenden Forschungsprojekte wurden in <strong>2004</strong><br />
insgesamt über 500 000 Euro Drittmittel eingeworben.<br />
Eine wichtige Aufgabe stellt der Ausbau der internationalen<br />
Vernetzung und die Gewinnung ausländischer<br />
Experten für die Mitarbeit dar. Ausdruck des<br />
erfolgreichen Wirkens des Gemeinsamen Labors auf<br />
diesem Gebiet sind seine internationale Zusammensetzung,<br />
die Beteiligung an einem japanischem Standardisierungsprojekt<br />
für Si-Wafer (siehe N. Inoue et<br />
al., Proc. of JSPS, <strong>2004</strong>, pp. 123-128), und die langjährige<br />
aktive Mitwirkung in internationalen Konferenzkomitees<br />
(z.B. Conference und Program Co-Chair bei<br />
11. Internationaler GADEST-Konferenz 2005).<br />
Das Gemeinsame Labor unterstützt und erweitert das<br />
Lehrangebot der BTU in den Studiengängen Physik,<br />
Physik der Halbleitertechnologie, Informatik und Elektrotechnik<br />
mit Vorlesungen, Übungen und Praktika. In<br />
<strong>2004</strong> wurden 3 Doktoranden und 5 Diplomanden betreut.<br />
Weiterführende Informationen über das Gemeinsame<br />
Labor sind unter www.tu-cottbus.de/jointlab abrufbar.<br />
60<br />
<strong>IHP</strong>/BTU Joint Lab<br />
Neues Elektronensondensystem mit Kathodolumineszenzausrüstung<br />
erweitert diagnostisches Potential.<br />
New electron probe system with cathodoluminescence attachments<br />
enhances diagnostic capabilities.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Research carried out this year on semiconductor materials<br />
and technology alone has resulted in 16 publications,<br />
33 presentations – 9 invited –, and 2 filed<br />
patents.<br />
A total third party funding of more than Euro 500,000<br />
was raised for the running projects.<br />
Prof. Dr. Eicke R. Weber, University of California, Berkeley (zweiter<br />
von links) beim Besuch des Gemeinsamen Labors im November <strong>2004</strong>.<br />
Prof. Eicke R. Weber, University of California, Berkeley (second from<br />
left) visiting the Joint Lab in November <strong>2004</strong>.<br />
The extension of the international integration and recruitment<br />
of foreign experts for collaboration is an<br />
important task for the capabilities of the Joint Lab.<br />
The international composition of the Joint Lab staff,<br />
the participation in a Japanese standardization project<br />
for silicon wafers (see N. Inoue et al., Proc. of JSPS,<br />
<strong>2004</strong>, pp. 123-128) and longtime active involvement in<br />
international conference committees (e.g. Conference<br />
and Program Co-Chair of 11 th GADEST Conference in<br />
2005) emphasize the successful work of the Joint Lab<br />
in this area.<br />
The Joint Lab supports and broadens the educational<br />
offers of the BTU with courses in Physics, Physics<br />
of Semiconductor Technology, Computer Science and<br />
Electrical Engineering through lectures, tutorials and<br />
lab practicals. In <strong>2004</strong> 5 graduates and 3 PhD students<br />
were supervised by Joint Lab staff.<br />
For more information about the Joint Lab please visit<br />
the website www.tu-cottbus.de/jointlab.
Gemeinsames Labor<br />
<strong>IHP</strong>/BTU<br />
<strong>IHP</strong>/BTU Joint Lab<br />
Die Mitarbeiter des Gemeinsamen Labors mit dem Präsidenten der BTU Cottbus, Prof. Dr. Ernst Sigmund (links außen) und dem Direktor des<br />
Gemeinsamen Labors, Prof. Dr. Hans Richter (zweiter von rechts).<br />
The employees of the Joint Lab with the President of BTU Cottbus, Prof. Ernst Sigmund (far left) and the Director of Joint Lab, Prof. Hans<br />
Richter (second from right).<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 61
Konferenzen und Workshops<br />
Conferences and Workshops
Das <strong>IHP</strong> beteiligte sich aktiv an der Organisation internationaler<br />
Konferenzen und Tagungen. Die Themen der<br />
Veranstaltungen reichten von Materialien bis zur Systementwicklung<br />
und spiegelten so die Forschungsgebiete<br />
des <strong>IHP</strong> wider.<br />
Im Folgenden ist eine Auswahl der <strong>2004</strong> mit aktiver<br />
Beteiligung des <strong>IHP</strong> organisierten Konferenzen und Tagungen<br />
beschrieben.<br />
2. Internationale Konferenz für Wired/Wireless<br />
Internet Communications WWIC <strong>2004</strong>, 04.-06.<br />
Februar <strong>2004</strong>, Frankfurt (Oder).<br />
Der Fokus der WWIC sind heterogene Netzwerkarchitekturen.<br />
Die Integration mobiler Endgeräte ins<br />
Internet führt zu einer Reihe neuer Herausforderungen,<br />
wie Design und Evaluierung von Protokollen, dynamische<br />
Integration, Performanz-Betrachtungen sowie<br />
neue Performanz-Metriken und Schichten übergreifende<br />
Interaktionen. Die Anzahl sowie die Qualität der Einreichungen<br />
zeigt, dass die WWIC auf einem guten Weg<br />
ist sich als eine der bedeutenden Konferenzen in diesem<br />
Gebiet zu etablieren.<br />
Der Tagungsband wurde in der angesehenen Reihe<br />
„Lecture Nodes in Computer Science“ des Springer<br />
Verlages veröffentlicht. Die Konferenz wurde vom <strong>IHP</strong><br />
organisiert und im Institut durchgeführt.<br />
Peter Langendörfer (<strong>IHP</strong>) war einer der Vorsitzenden<br />
des Programmkomitees. Daniel Dietterle, Jan Schäffner<br />
und Heike Wasgien (alle <strong>IHP</strong>) arbeiteten im Organisationskomitee.<br />
2. Internationales SiGe Technology and Device<br />
Meeting ISTDM <strong>2004</strong>, 16.-19. Mai <strong>2004</strong>, Frankfurt<br />
(Oder).<br />
116 Experten diskutierten aktuelle Ergebnisse der<br />
SiGe-Forschung auf den Gebieten Materialwissenschaften,<br />
Prozesstechnologie, Bauelementeentwicklung und<br />
Schaltkreisdesign. Die Kombination aus Grundlagen-<br />
und angewandter Forschung wird deutlich in der Zusammensetzung<br />
der Teilnehmer (44% von Universitäten,<br />
34% von Forschungsinstituten und 22% aus der<br />
Industrie). Die Kongressteilnehmer kamen aus 14 europäischen<br />
und asiatischen Ländern sowie den USA.<br />
Der Tagungsband wurde im Februar 2005 in „Materials<br />
Science in Semiconductor Processing” (Elsevier)<br />
veröffentlicht.<br />
Konferenzen<br />
und Workshops<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Conferences<br />
and Workshops<br />
The <strong>IHP</strong> was active in organizing international conferences<br />
and workshops. The topics spanned from system<br />
design to materials, reflecting the research areas<br />
of the <strong>IHP</strong>.<br />
A selection of the international conferences and workshops,<br />
organized in <strong>2004</strong> with active contributions of<br />
the <strong>IHP</strong>, are described below.<br />
2 nd International Conference on Wired/Wireless<br />
Internet Communications WWIC <strong>2004</strong>, February<br />
04-06, Frankfurt (Oder).<br />
WWIC is dedicated to bridging the gap between wired<br />
and wireless Internet. The issue of integrating mobile<br />
devices in the Internet poses many challenges such as<br />
the design and evaluation of protocols, the dynamics<br />
of the integration, the performance tradeoffs, the need<br />
for new performance metrics, and the cross-layer interactions.<br />
The number and the quality of submissions<br />
indicates that WWIC is well on the way to establishing<br />
itself as one of the major events in this field.<br />
The proceedings have been published in the prestigious<br />
"Lecture Nodes in Computer Science" Series of<br />
Springer. The conference was organized by <strong>IHP</strong> staff<br />
and held at the institute.<br />
Peter Langendörfer (<strong>IHP</strong>) was one of the Technical Program<br />
Chairs, and Daniel Dietterle, Jan Schäffner and<br />
Heike Wasgien (all <strong>IHP</strong>) were part of the organizing<br />
committee.<br />
2 nd International SiGe Technology and Device<br />
Meeting, May 16-19, <strong>2004</strong>, Frankfurt (Oder).<br />
Altogether 116 experts met to discuss the current status<br />
of SiGe materials science, process technology, devices,<br />
and circuit design. This combination of basic<br />
and applied research was reflected in the composition<br />
of the participants (44% from universities, 34% from<br />
state-run research institutes, and 22% from industry).<br />
The participants came from 14 European and Asian<br />
countries and from the USA.<br />
The proceedings of the conference are published as<br />
the February 2005 issue of “Materials Science in Semiconductor<br />
Processing” (Elsevier).<br />
63
Konferenzen<br />
und Workshops<br />
64<br />
Conferences<br />
and Workshops<br />
Die ISTDM wurde vom <strong>IHP</strong> organisiert und im Kongresscentrum<br />
„Kleist Forum“ in Frankfurt (Oder) durchgeführt.<br />
Bernd Tillack (<strong>IHP</strong>) führte den Vorsitz des Programmkomitees.<br />
Gerhard Fischer, Monika Schultze und Yuji<br />
Yamamoto (alle <strong>IHP</strong>) waren Mitglieder des Organisationskomitees.<br />
Symposium C des Frühjahrstreffens der E-MRS:<br />
Neue Materialien in der zukünftigen Siliziumtechnologie,<br />
24.-28. Mai <strong>2004</strong>, Strassburg (Frankreich).<br />
Das Symposium konzentrierte sich auf zukünftige Herausforderungen<br />
für die Materialforschung durch die<br />
weitere Strukturverkleinerung silizium-basierter Bauelemente,<br />
die in den nächsten Jahren die physikalischen<br />
Grenzen erreichen werden. Die Veranstaltung<br />
war insbesondere der Charakterisierung und der Auswahl<br />
neuer Materialien für die Integration in CMOS-<br />
Technologien gewidmet, bestimmt von den praktischen<br />
Anforderungen der Industrie.<br />
Hans-Joachim Müssig und Jarek Dabrowski (<strong>IHP</strong>) waren<br />
Mitglieder des Organisationskomitees.<br />
8. B<strong>MB</strong>F Statusseminar Mobile Kommunikation,<br />
(Bundesministerium für Bildung und Forschung),<br />
13.-15. Juli <strong>2004</strong>, <strong>IHP</strong> Frankfurt (Oder).<br />
Im Rahmen des 8. Statusseminars des B<strong>MB</strong>F Förderbereichs<br />
Mobile Kommunikation stellten über 100 eingeladene<br />
Wissenschaftler aus Industrie und Forschung<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
The conference was organized by the <strong>IHP</strong> and held at<br />
the Congresscenter "Kleist Forum" in Frankfurt (Oder).<br />
Bernd Tillack (<strong>IHP</strong>) was Chairman of the Program Committee.<br />
Gerhard Fischer, Monika Schultze, and Yuji Yamamoto<br />
(all <strong>IHP</strong>) were members of the organizing committee.<br />
Das Organisationskomitee der ISTDM <strong>2004</strong>./Organization Committee of the ISTDM <strong>2004</strong>.<br />
Prof. Junichi Murota (Tohoku University Sendai), Dr. Bernd Tillack (<strong>IHP</strong>) und Prof. Erich Kasper (University of Stuttgart) [von links nach<br />
rechts/from left to right].<br />
Symposium C of the E-MRS <strong>2004</strong> Spring Meeting:<br />
New Materials in Future Silicon Technology, May<br />
24-28, <strong>2004</strong>, Strasbourg (France).<br />
The symposium focused on the future challenges in<br />
material science to the continued scaling of siliconbased<br />
devices reaching the physical limits of miniaturization<br />
within the next few years. It was devoted to<br />
the characterization and selection of new materials for<br />
the integration into CMOS technology in response to<br />
practical demands ensuing from the industry.<br />
Hans-Joachim Müssig and Jarek Dabrowski (<strong>IHP</strong>) were<br />
members of the symposium organizers.<br />
8 th B<strong>MB</strong>F Status Seminar Mobile Communications<br />
(Federal Ministry for Education and Research),<br />
July 13-15, <strong>2004</strong>, <strong>IHP</strong> Frankfurt (Oder).<br />
More than one hundred scientists from industries and<br />
academia presented their latest findings during the<br />
8 th B<strong>MB</strong>F Status Seminar in Frankfurt (Oder). Besides
ihre jüngsten Forschungsergebnisse in Fachvorträgen<br />
am <strong>IHP</strong> in Frankfurt (Oder) vor. Darüber hinaus wurden<br />
zahlreiche Poster und funktionsfähige Demonstratoren<br />
vorgestellt.<br />
Das Statusseminar wurde so zu einem Forum des regen<br />
Meinungsaustausches führender Wissenschaftler<br />
auf dem Gebiet der mobilen Kommunikation. Als Gastgeber<br />
hat das <strong>IHP</strong> diese Gelegenheit genutzt, die eigenen<br />
Forschungsvorhaben einem breiten und sachkundigen<br />
Publikum vorzustellen.<br />
Der lokale Organisator des Seminars war Rolf Kraemer<br />
(<strong>IHP</strong>).<br />
9. Augustusburg Conference of Advanced Science:<br />
Das Silizium-Zeitalter, 23.-25. September <strong>2004</strong>,<br />
Augustusburg.<br />
Diese Veranstaltung war vorgesehen als Forum für die<br />
Bewertung und Diskussion verschiedener Aspekte des<br />
Siliziumszeitalters. Vortragende aus Hochschulen und<br />
der Industrie präsentierten ihren Blick auf die Anwendung<br />
des Siliziums in der Mikroelektronik, Photovoltaik<br />
und Photonik.<br />
Martin Kittler (<strong>IHP</strong>) war der Vorsitzende dieser Konferenz<br />
und Hans Richter (<strong>IHP</strong>) Mitglied im Organisationskomitee.<br />
<strong>IHP</strong> Workshop High-Performance SiGe:C BiCMOS for<br />
Wireless and Broadband Communication, 30. September<br />
<strong>2004</strong>, Frankfurt (Oder).<br />
Vertreter von 27 Firmen und wissenschaftlichen Einrichtungen<br />
aus acht Ländern nutzten das Treffen, um<br />
sowohl bereits verfügbare Technologien als auch neueste<br />
Forschungsarbeiten des <strong>IHP</strong> kennen zu lernen.<br />
Neben aktiven Nutzern der <strong>IHP</strong>-Technologien trafen<br />
sich auf dem Workshop auch zahlreiche neue Interessenten<br />
für eine Kooperation mit dem Institut. Die Veranstaltung<br />
bot nicht nur neueste Informationen aus<br />
erster Hand, sondern auch Gelegenheit für zahlreiche<br />
persönliche Gespräche und neue Kontakte.<br />
Der Workshop wurde durch Wolfgang Kissinger (<strong>IHP</strong>)<br />
organisiert.<br />
Konferenzen<br />
und Workshops<br />
Conferences<br />
and Workshops<br />
technical presentations, a poster presentation and an<br />
exhibition of working demonstrators were organized.<br />
Thus the Status Seminar became a forum for intense<br />
discussions between experts in the field of mobile<br />
communications. As the host of this event, the<br />
<strong>IHP</strong> used this opportunity to present its own research<br />
projects and findings to a broad and competent community.<br />
The local organizer of this event was Rolf Kraemer<br />
(<strong>IHP</strong>).<br />
9 th Augustusburg Conference of Advanced Science:<br />
The Silicon Age, September 23-25, <strong>2004</strong>, Augustusburg.<br />
This event provided a forum for reviewing and discussing<br />
different aspects of the silicon age.Speakers<br />
from academia and industry represented their views<br />
on silicon used for microelectronics, photovoltaics<br />
and photonics.<br />
Martin Kittler (<strong>IHP</strong>) was the Chairman of this conference<br />
and Hans Richter (<strong>IHP</strong>) was member of the organizing<br />
committee.<br />
<strong>IHP</strong> Workshop High-Performance SiGe:C BiCMOS<br />
for Wireless and Broadband Communication, September<br />
30, <strong>2004</strong>, Frankfurt (Oder).<br />
Participants from 27 companies and research institutions<br />
from eight countries used the meeting to learn<br />
about the available technologies as well as the latest<br />
research at the <strong>IHP</strong>.<br />
In addition to active users of <strong>IHP</strong>’s technologies, numerous<br />
potential collaborators with the <strong>IHP</strong> also met<br />
at this workshop. The event offered not only the latest<br />
first-hand information, but also the opportunity to engage<br />
in many personal discussions and to forge new<br />
contacts.<br />
The workshop was organized by Wolfgang Kissinger<br />
(<strong>IHP</strong>).<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 65
Zusammenarbeit und Partner<br />
Collaborators and Partners
Industrie/Industry<br />
A*Star, Singapore<br />
ABS GmbH, Germany<br />
ACCESS e.V., Germany<br />
Acquiris, Switzerland<br />
AdMOS GmbH, Germany<br />
advICo microelectronics GmbH, Germany<br />
Agilent Technologies GmbH, Germany<br />
AIXTRON AG, Germany<br />
Alcatel SEL AG, Germany<br />
alpha microelectronics GmbH, Germany<br />
AMD Inc., Germany<br />
ARMINES, France<br />
Ascom Systec AG, Switzerland<br />
ASM Inc., USA<br />
Atmel Germany GmbH, Germany<br />
Centellax Inc., Santa Rosa, USA<br />
centrotherm GmbH & Co. KG, Germany<br />
CML Microsystems Plc, UK<br />
CNR IMM, Catania, Italy<br />
CoreOptics GmbH, Germany<br />
CSEM SA, Switzerland<br />
DaimlerChrysler Research Centre, Germany<br />
Deutsche Solar AG, Germany<br />
EADS Radio Communication Systems GmbH und<br />
Co. KG, Germany<br />
Enpirion Inc., USA<br />
Freescale Semiconductor, Germany<br />
Fundacion Robtiker-Tenalia Technology Corp., Spain<br />
IMST GmbH, Germany<br />
Infineon Technologies AG, Germany<br />
InnoSenT GmbH, Germany<br />
Institute for Solar Energy Research GmbH, Germany<br />
Pulse Technologies, Russia<br />
KMSD Ltd. Kaunas Mixed Signal Design, Lithuania<br />
KOTURA Inc., USA<br />
lesswire AG, Germany<br />
MEDAV GmbH, Germany<br />
Melexis GmbH, Germany<br />
Merge Optics GmbH, Germany<br />
Zusammenarbeit<br />
und Partner<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Collaborators<br />
and Partners<br />
Micronas GmbH, Germany<br />
Mitsubishi Electric Information Technology Centre<br />
Europe B.V., France<br />
Motorola S.A.S., France<br />
Nokia GmbH, Germany<br />
Nokia Research Centre, Germany<br />
Philips CFT, Eindhoven, The Netherlands<br />
Philips Electronics Netherland B.V., The Netherlands<br />
Philips Electronics Ltd., UK<br />
Philips Research Laboratories Aachen, Germany<br />
Philips Semiconductor GmbH, Germany<br />
PropheSi Technologies, USA<br />
Robert Bosch GmbH, Germany<br />
RWE Schott Solar GmbH, Germany<br />
Samsung Electronics Co. Ltd., Republic of Korea<br />
Sennheiser electronic GmbH & Co. KG, Germany<br />
Siemens AG, Germany<br />
Siemens Austria AG, Austria<br />
SiGe Semiconductor Inc., Canada<br />
Signalion GmbH, Germany<br />
Siltronic AG, Germany<br />
ST<strong>Microelectronics</strong> N.V., Switzerland<br />
StrataLight Communications, USA<br />
SUSS MicroTec Test Systems GmbH, Deutschland<br />
Synergy Microwave Corporation, USA<br />
Synergy Microwave Research GmbH, Teltow<br />
Tanner Research Inc., USA<br />
Telefonica Investigacion y Desarrollo S.A.<br />
Unipersonal, Spain<br />
Texas Instruments GmbH, Germany<br />
Thales Communication S.A., Switzerland<br />
Thales Electronic Engineering GmbH, Germany<br />
T-Systems Nova GmbH, Germany<br />
VTT Electronics, Finland<br />
Winfinity GmbH, Germany<br />
Wisair Ltd., Israel<br />
XFAB Semiconductor Foundries AG, Germany<br />
ZMD AG, Germany<br />
67
Zusammenarbeit<br />
und Partner<br />
68<br />
Collaborators<br />
and Partners<br />
Forschungsinstitute und Universitäten/Research Institutes and Universities<br />
Australia Telescope National Faciity (CSIRO), Australia<br />
CEA/LETI, France<br />
Delft University of Technology, The Netherlands<br />
Denmark Technical University, Denmark<br />
European University Viadrina of Frankfurt (Oder),<br />
Germany<br />
Fraunhofer IIS, Germany<br />
Fraunhofer ISE, Germany<br />
Freie Universität Berlin, Germany<br />
Friedrich-Alexander University Erlangen-Nuremberg,<br />
Germany<br />
Georg-August University of Göttingen, Germany<br />
Georgia Institute of Technology Atlanta, USA<br />
Hahn-Meitner-Institute, Germany<br />
Hangzhou Dianzi University, China<br />
Humboldt Universität zu Berlin, Germany<br />
IMEC, Belgium<br />
Indian Institute of Technology, Kharagpur, India<br />
Institute for Infocomm Research, Singapore<br />
Institute for Physical High Technology (IPHT), Jena,<br />
Germany<br />
Institute of Computer Science, ICS-FORTH, Greece<br />
Institute of <strong>Microelectronics</strong>, Singapore<br />
Institute of Semiconductor Physics, Kiev, Ukraina<br />
Josef Stefan Institute, Slovenia<br />
K. U. Leuven, Belgium<br />
KTH Stockholm, Sweden<br />
Las Palmas de Gran Canaria University, Spain<br />
London South Bank University, UK<br />
Ludwig-Maximilians-University of Munich, Germany<br />
Max Planck Institute of Microstructure Physics,<br />
Germany<br />
National Electronics and Computer Technology<br />
Centre, Thailand<br />
National Technical University of Athens, Greece<br />
Politecnico di Torino, Italy<br />
Progress <strong>Microelectronics</strong> Research Institute,<br />
Moscow, Russia<br />
RadioLabs, Italy<br />
RWTH Aachen, Germany<br />
Saint-Petersburg State University, Russia<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Sino German Science Centre, Peking, China<br />
Swiss Federal Institute of Technologies (ETH),<br />
Switzerland<br />
Technical University Bergakademie Freiberg, Germany<br />
Technical University of Berlin, Germany<br />
Technical University of Brandenburg, Cottbus,<br />
Germany<br />
Technical University of Catalonia, Spain<br />
Technical University of Darmstadt, Germany<br />
Technical University of Dresden, Germany<br />
Technical University of Ilmenau, Germany<br />
Technion-Israel Institute of Technology, Israel<br />
Tel-Aviv University, Tel-Aviv, Israel<br />
TIMA Laboratory, France<br />
Tohoku University, Sendai, Japan<br />
University of Applied Sciences Wildau, Germany<br />
University of Bristol, UK<br />
University of Cambridge, UK<br />
University of Firenzi, Italy<br />
University of Florence, Italy<br />
University of Glasgow, UK<br />
University of Hamburg-Harburg, Germany<br />
University of Karlsruhe (TH), Germany<br />
University of Kassel, Germany<br />
University of Konstanz, Germany<br />
University of Limerick, Ireland<br />
University of London, UK<br />
University of Manchester, UK<br />
University of Newcastle upon Tyne, UK<br />
University of Nottingham, UK<br />
University of Oulu, Finland<br />
University of Paderborn, Germany<br />
University of Potsdam, Germany<br />
University of Rom, Italy<br />
University of Stuttgart, Germany<br />
University of Toronto, Canada<br />
University of Ulm, Germany<br />
University of Zielona Gora, Poland<br />
Victoria University, UK<br />
Zhejiang University, Zhedalu, China
Zusammenarbeit<br />
und Partner<br />
Collaborators<br />
and Partners<br />
Brandenburgs Ministerin für Wissenschaft, Forschung und Kultur, Prof. Dr. Johanna Wanka, im Gespräch mit Schülern anlässlich der Übergabe<br />
des Forschungspreises des Fördervereins „Freunde des <strong>IHP</strong> e.V.“ am 4. September <strong>2004</strong>.<br />
Brandenburg’s Minister for Science, Research and Culture, Prof. Johanna Wanka, conversing with pupils at the award-giving ceremony for<br />
the research prize of the organization “Freunde des <strong>IHP</strong> e.V.” on September 4, <strong>2004</strong>.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 69
Gastwissenschaftler und Seminare<br />
Guest Scientists and Seminars
Gastwissenschaftler<br />
und Seminare<br />
Gastwissenschaftler/ Institution/Institution Forschungsgebiet/<br />
Guest Scientist Research Area<br />
1. Dr. K. Washio Hitachi Ltd., Central Research Process Technology<br />
Laboratory, Tokyo, Japan<br />
2. Prof. O. Vyvenko Saint-Petersburg State Material and Diagnostics<br />
University, Russia<br />
3. Mr. V. Passi University of Darmstadt, Process Technology<br />
Germany<br />
4. Mr. B. Mongellaz University of Bordeaux, France Process Technology<br />
5. Dr. A. U. Mane Humboldt Research Fellowship Material and Diagnostics<br />
6. Mr. A. Hudyryev Institute for Semiconductor Process Technology<br />
Physics, Kiev, Ukraina<br />
7. Mr. O. Gromovyy Institute for Semiconductor Process Technology<br />
Physics, Kiev, Ukraina<br />
8. Mr. A. Chakravorty Indian Institute of Technology, Process Technology<br />
Kharagpur, India<br />
9. Prof. S. Bannerje Indian Institute of Technology, Systems<br />
Kharagpur, India<br />
10. Dr. V. Bukalo Institute for Semiconductor Material and Diagnostics<br />
Physics, Kiev, Ukraina<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Guest Scientists<br />
and Seminars<br />
71
Gastwissenschaftler<br />
und Seminare<br />
72<br />
Guest Scientists<br />
and Seminars<br />
Vortragender/Presenter Institution/Institution Topic/Thema<br />
1. Dr. U. Wulf Technical University of Brandenburg, ‘‘Other Projects about Quantum<br />
Cottbus, Germany Transport at the Chair of Theoretical<br />
Physics of the BTU Cottbus”<br />
2. Dr.-Ing. A. Willig Hasso Plattner Institute for Software “The Intermediate Checksum<br />
Systems Engineering, Germany Scheme”<br />
3. Dr. K. Washio Hitachi Ltd., Central Research “Overview of Hitachi‘s SiGe<br />
Laboratory, Tokyo, Japan HBT/BiCMOS Technologies and Their<br />
Applications”<br />
4. Prof. P. Seegebrecht University of Kiel, Germany “MOS Tunnel Structures With the<br />
Focus on Optical Properties”<br />
5. Dr. P. N. Racec <strong>IHP</strong>/BTU Joint Lab, Cottbus, Germany “Transport Modelling in MIS-type<br />
Nanostructures”<br />
6. Mr. W. Hoenlein Infi neon Technologies Dresden, Germany “Carbon Nanotubes – a Successor to<br />
Silicon Technology?”<br />
7. Mr. C. Hoene Technical University of Berlin, Germany “IP Telephony over Wireless LAN”<br />
8. Mr. E. Hijzen Philips Research Leuven, Belgium “RF Device Research at Philips<br />
Research Leuven”<br />
9. Dr.-Ing. A. Festag European Network Centre (NEC) “Mobile Internet”<br />
Heidelberg, Germany<br />
10. Prof. C. Enz CSEM SA, Neuchatel, Switzerland “The EKV MOS Transistor Model for<br />
Low-Voltage and Low-Power Circuit<br />
Design”<br />
11. Ms. D. Drachenberg Technical University of Brandenburg, “Examination of Antirefl ective<br />
Cottbus, Germany Coatings for 130 nm Technology”<br />
12. Prof. A. Devi Ruhr University of Bochum, Germany “Precursor Engineering for Chemical<br />
Vapor Deposition and Atomic<br />
Layer Deposition of Advanced<br />
Functional Materials”<br />
13. Mrs. S. H. Christiansen Max-Planck-Institute for Micro- “Future Silicon: Strained,<br />
structure Physics, Halle, Germany Flexible, Nano-structured”<br />
14. Prof. A. Bestavros University of Boston, Computer “Exploiting the Transients of<br />
Science Department, USA Adaptation for RoQ Attacks on<br />
Internet Resources”<br />
15. Dr. med. G. Becher FILT GmbH, Berlin-Buch, Germany “<strong>Microelectronics</strong> and Semiconductor<br />
Technology for Medical Applications<br />
– Do Our Expectations Conform<br />
With the Possibilities and Do<br />
We Even Know What To Expect ?“<br />
16. Prof. S. Banerjee Indian Institute of Technology “VLSI for Biomedical<br />
Kharagpur, India Instrumentation”<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT
Gastwissenschaftler<br />
und Seminare<br />
Guest Scientists<br />
and Seminars<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 73
Publikationen<br />
Publications
A 16-BIT CORDIC ROTATOR FOR HIGH-SPEED WIRELESS LAN<br />
Koushik Maharatna 1 , Alfonso Troya 2 , Swapna Banerjee 3 , Eckhard Grass 2 , Miloš Krsti� 2<br />
1 Dept. of EE, University of Bristol, UK, Koushik.Maharatna@bristol.ac.uk<br />
2 <strong>IHP</strong>, Frankfurt (Oder), Germany, {troya, grass, krstic}@ihp-microelectronics.com<br />
3 Dept. of E & ECE, IIT Kharagpur, India, swapna@ece.iitkgp.ernet.in<br />
Abstract – In this paper we propose a novel 16-bit low<br />
power CORDIC rotator that is used for high-speed wireless<br />
LAN. The algorithm converges to the final target angle by<br />
adaptively selecting appropriate iteration steps while<br />
keeping the scale factor virtually constant. The VLSI<br />
architecture of the proposed design eliminates the entire<br />
arithmetic hardware in the angle approximation datapath and<br />
reduces the number of iterations by 50% on an average. The<br />
cell area of the processor is 0.7 mm 2 and it dissipates 7 mW<br />
power at 20 MHz frequency.<br />
Keywords – CORDIC, NCO, Synchronization, low power,<br />
WLAN.<br />
I. INTRODUCTION<br />
OFDM-based high-speed Wireless LAN (WLAN) systems<br />
are currently in the focus of research and development.<br />
However, the hardware cost of such systems is quite high<br />
and innovative techniques have to be used to design the<br />
critical functional blocks in order to satisfy the timing and<br />
power constraints as well as to minimize the overall circuit<br />
complexity and cost. One such critical functional block is<br />
the CoOrdinate Rotation DIgital Computer (CORDIC) that<br />
can be used for the frequency offset correction of the input<br />
data during synchronization at the receiver. In this case, the<br />
forward rotation mode of the CORDIC is utilized which<br />
essentially works as a Numerically Controlled Oscillator<br />
(NCO). Though it offers an elegant solution, the classical<br />
CORDIC algorithm has several shortcomings which<br />
inspired many researchers to look into the development of<br />
high-performance CORDIC algorithm and its efficient<br />
implementation [1 – 6]. However, the algorithmic level<br />
speed limit of CORDIC as well as the required scale factor<br />
compensation are problems which restrict the application<br />
range of this circuit.<br />
In this paper we describe a novel CORDIC rotator that is<br />
used for the synchronizer unit in a project that aims at the<br />
implementation of single-chip modem for IEEE 802.11a<br />
standard [7]. Though according to the specification of the<br />
project we design a 16-bit CORDIC processor that can<br />
operate in the forward operation mode only, the method can<br />
be generalized for any arbitrary wordlength. In essence, the<br />
current work is based on a scaling free CORDIC algorithm<br />
proposed earlier by the authors [8, 9]. The CORDIC rotator<br />
proposed here is virtually scaling free (needs a scaling by<br />
Nachdrucke<br />
ausgewählter Publikationen<br />
1/√2 or 1) and has the convergence range over the entire<br />
coordinate space. It converges to the target angle by<br />
adaptively choosing the actually needed iteration steps only,<br />
while skipping the other not actually needed iteration steps.<br />
This adaptive selection does not have any impact on the<br />
final scale factor. Based on this algorithm, we propose a<br />
design of a low power 16-bit pipelined CORDIC rotator that<br />
eliminates the entire arithmetic processing and subsequent<br />
circuitry along the angle approximation (or z) datapath and<br />
on an average saves 50% iterations without compromising<br />
the accuracy. The rest of the paper is structured as follows:<br />
Section II describes the theoretical formulation of the<br />
algorithm while the VLSI implementation is described in<br />
Section III. The performance evaluation is done in Section<br />
IV and the conclusions are drawn in Section V.<br />
II. THEORETICAL GROUNDWORK<br />
In essence, this work is based on a scaling free CORDIC<br />
algorithm proposed by the authors that eliminates the<br />
problem of scale factor compensation [8, 9]. In this<br />
algorithm the vector is rotated only in one direction in steps<br />
of very small angles i so that the magnitude of the vector<br />
remains preserved at each step of elementary rotation. The<br />
angles i are expressed as,<br />
(1)<br />
With this consideration, the working equation of the scaling<br />
free CORDIC at the i th iteration becomes,<br />
sin( i) i = 2 −i<br />
�x<br />
� � − ( 2i<br />
+ 1)<br />
��<br />
�<br />
�<br />
−<br />
− i x<br />
�<br />
i + 1 1 2<br />
2<br />
� =<br />
��<br />
i<br />
(2a)<br />
�<br />
�y<br />
� � − − i + �<br />
� + �<br />
�y<br />
i<br />
�<br />
�<br />
�−<br />
i ( 2 1)<br />
1 2 1−<br />
2 � i �<br />
z<br />
i+<br />
1<br />
= z − 2<br />
i<br />
−i<br />
Reprints of<br />
Selected Publications<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 75<br />
(2b)<br />
Because of the 1 st order approximation used in equation (1),<br />
the allowed values of elementary rotational index (iteration<br />
index) i are,<br />
�(b − 2.585) / 3� = p ≤ i ≤ b−1 (3)<br />
where b is the wordlength. Though this approach eliminates<br />
the scale factor compensation problem, its convergence<br />
range is very small. In this work we extend its convergence<br />
over the entire coordinate space by employing a technique<br />
called domain folding.
Nachdrucke<br />
ausgewählter Publikationen<br />
76<br />
We first divide the first quadrant into four domains namely<br />
A∈[0, π/8), B∈[π/8, π/4), C∈[π/4, 3π/8) and D∈[3π/8, π/2].<br />
In each of these domains the target angle θ can be redefined<br />
in terms of another angle φ bounded in the interval [0, π/8]<br />
by the following equations,<br />
θ = φ , in domain A (4)<br />
θ = π/4 − φ , in domain B (5)<br />
θ = π/4 + φ , in domain C (6)<br />
θ = π/2 − φ , in domain D (7)<br />
Thus, the CORDIC rotator operation on an input vector<br />
[x y] T in different domains can be expressed in terms of φ as<br />
follows (considering clockwise rotation),<br />
�x<br />
�<br />
��<br />
y<br />
�x<br />
�<br />
��<br />
y<br />
�x<br />
�<br />
��<br />
y<br />
�x<br />
�<br />
��<br />
y<br />
fA<br />
fA<br />
fB<br />
fB<br />
fC<br />
fC<br />
fD<br />
fD<br />
� �cos<br />
φ sin φ ��x<br />
�<br />
=<br />
(8)<br />
� �<br />
��<br />
�<br />
��<br />
�−<br />
sin φ cosφ<br />
��<br />
y�<br />
� 1 �(cosφ<br />
+ sin φ)<br />
( cosφ<br />
− sin φ)<br />
��x<br />
�<br />
� =<br />
(9)<br />
�<br />
��<br />
�<br />
��<br />
2 �−<br />
(cosφ<br />
− sin φ)<br />
( cosφ<br />
+ sin φ)<br />
��<br />
y�<br />
� 1 �(cosφ<br />
− sinφ<br />
) ( cosφ<br />
+ sinφ<br />
) ��x<br />
�<br />
� =<br />
(10)<br />
�<br />
��<br />
�<br />
��<br />
2 �−<br />
(cosφ<br />
+ sinφ<br />
) ( cosφ<br />
− sinφ<br />
) ��<br />
y�<br />
� �sin<br />
φ cosφ<br />
��x<br />
�<br />
=<br />
(11)<br />
� �<br />
��<br />
�<br />
��<br />
�−<br />
cosφ<br />
sinφ<br />
��<br />
y�<br />
where xf* denotes the final vector resulting from a CORDIC<br />
rotator operation with target angles lying in a certain domain<br />
indicated by ‘*’.<br />
Now denoting [x1+ y1+] T and [x1− y1−] T as the result of<br />
CORDIC rotation for angles φ and −φ respectively,<br />
equations (8) to (11) can be written as,<br />
x fA = x1−<br />
= y1−<br />
x fB<br />
x fC<br />
1<br />
= [ x1+<br />
+ y1+<br />
]<br />
2<br />
1<br />
[ 1−<br />
1−<br />
]<br />
2<br />
+ = y x<br />
y fA (12)<br />
y fB<br />
y fC<br />
1<br />
= [ −x1<br />
+ + y1+<br />
]<br />
2<br />
x fD = y1+<br />
= −x1<br />
+<br />
1<br />
[ 1−<br />
1−<br />
]<br />
2<br />
+ − = y x<br />
Reprints of<br />
Selected Publications<br />
(13)<br />
(14)<br />
y fD (15)<br />
Hence, using the above equations, the CORDIC rotator<br />
operation with target angles lying in any domain in the first<br />
quadrant can be computed from the results of the CORDIC<br />
rotation with the modified target angle φ (bounded in the<br />
interval [0, π/8]). By exploiting the symmetry of the coordinate<br />
axes, this technique can be extended to carry out<br />
CORDIC rotator operations with target angles lying in other<br />
quadrants as well with minimal extra hardware overhead. As<br />
a result, a CORDIC having a convergence range of [0, π/8]<br />
is sufficient to cover the entire coordinate space. It is to be<br />
noted that for target angles lying in domains B or C, we<br />
require a fixed scale factor of 1/ 2 that is absolutely<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
independent of the number of iterations executed. On the<br />
other hand, for the angles lying in domains A or D, no<br />
scaling is required. We call this technique domain folding<br />
since in this formulation all the domains are effectively<br />
folded back to domain A.<br />
To enhance the convergence range of the scaling free<br />
CORDIC to π/8, we propose the greedy algorithm shown in<br />
Figure 1 which essentially selects only the absolutely<br />
needed elementary rotational steps in an adaptive manner.<br />
Rref in Figure 1 denotes a user-defined accuracy.<br />
III. VLSI IMPLEMENTATION AND RESULTS<br />
In principle, our design consists of three basic sections, viz.,<br />
the sign/domain detection circuitry, the basic CORDIC<br />
rotator having a convergence range [0, π/8], and the output<br />
circuitry. The design specification for our system needs a<br />
16-bit CORDIC rotator. In our formulation the maximum<br />
target angle φ to be computed is π/8, which can be<br />
expressed as 0001100100100010 with an error of O(2 −16 ),<br />
where we consider the definition of decimal 1 to be<br />
0100000000000000. Thus, for representing the absolute<br />
value of any angle lying in our modified convergence range<br />
one can omit the 3 MSB and use the 13 LSBs. We use this<br />
fact to reduce the arithmetic computation in the z datapath.<br />
Fig. 1. The proposed greedy algorithm.<br />
A. Sign / Domain detection circuitry<br />
We assume that the largest angle that can be assigned to the<br />
primary input angle (z0) is within the range [0, 2π] and thus,<br />
requires 18-bit representation. Any negative angle will also<br />
fall in this range. Accordingly, the sign/domain detection<br />
circuit has two 16-bit data input for x and y datapath and an<br />
18-bit input for the z datapath. This circuit first detects the<br />
sign (quadrant) and the domain in which the target angle lies<br />
and applies the domain folding technique to derive a 13-bit<br />
unsigned representation of the modified target angle φ. It<br />
also generates two 2-bit signals called quad and domain that
characterize quadrant and domain of the original target<br />
angle.<br />
B. Basic pipelined CORDIC rotator<br />
The elementary rotational section used here is shown in<br />
Figure 2 [8], which is essentially derived from equation (2a).<br />
For a pipeline implementation, each of these sections<br />
requires two adders more compared to that of the<br />
conventional CORDIC. However, for the elementary<br />
rotational sections corresponding to i ≥ 7, a right shift by<br />
(2i+1)-bit essentially results in a machine zero or retention<br />
of the sign bit only and thus, the extra adders can be omitted<br />
for those stages. The allowed values of iteration in the<br />
present case are {4, 5, …, 15} (p = 4 from equation (3)).<br />
However, a right shift by 15-bit once again results in the<br />
retention of the sign bit only and thus for practical purpose<br />
the i = 15 stage can be omitted. We will show later that this<br />
does not significantly affect the accuracy.<br />
In our implementation, we have used the i = 4 elementary<br />
rotational stage six times whereas, the stages corresponding<br />
to i = 5…14 are used once each. With this arrangement the<br />
maximum angle that can be computed is 25°, therefore<br />
covering our convergence range. To make the pipeline<br />
completely balanced in terms of operation speed, we<br />
concatenate the elementary rotational sections<br />
corresponding to i = (7, 8), (9, 10), (11, 12) and (13, 14),<br />
where the sections within the parenthesis form a single<br />
pipeline stage. Thus, the basic CORDIC pipeline becomes<br />
12 stages long, with the hardware complexity of each of<br />
them being equivalent to four 16-bit adders. The signals<br />
quad and domain are transferred synchronously between<br />
two successive stages of the pipeline in a local register<br />
transfer manner. These signals act as a token attributed to<br />
the data in different sections of the pipeline carrying the<br />
information about the initial quadrant and domain of that<br />
particular data.<br />
As it has been mentioned earlier, in this algorithm we<br />
approach the target angle by rotating the vector in one<br />
direction only. Thus, in essence, we are approximating the<br />
final target angle as a pure summation of 2 −i . As a result, the<br />
appropriate rotational sections to be activated for a<br />
particular target angle have a one-to-one correspondence<br />
with the position of a logic ‘1’ in the 13-bit unsigned<br />
representation of φ. As an example, let us consider φ = 20°<br />
(0.349 radian). The unsigned representation of this angle is<br />
1011001010111. To achieve this target angle, the rotational<br />
sections to be activated are governed by the algorithm<br />
described in Figure 1. In the present example these are i = 4,<br />
4, 4, 4, 4, 5, 8, 10, 12, 13 and 14, whereas the deactivated<br />
elementary rotational sections are simply bypassed. The<br />
number of active i = 4 stages is obtained after decoding the<br />
first three Most Significant Bits (MSB) in φ (12 th , 11 th and<br />
10 th bits). Hence, the combinatorial logic shown in Figure 3<br />
is a simple digital decoder. In the previous example, we<br />
found the first three MSBs to be 101, which corresponds to<br />
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decimal 5. Note that the case in which all three MSBs are<br />
‘1’ will never occur.<br />
To keep the pipelined operation intact, we feed the<br />
individual bits of the 13-bit unsigned representation of φ to<br />
the appropriate elementary rotational sections as an enable<br />
signal for that particular section through an array of shift<br />
registers. The number of the shift registers is chosen in such<br />
a manner that the appropriate section gets enabled at the<br />
appropriate clock cycles. The complete architecture is<br />
shown in Figure 3 where the dotted lines indicate the<br />
concatenated elementary rotational stages. This arrangement<br />
essentially mimics the search algorithm shown in Figure 1<br />
and eliminates the comparison of zi with 2 −i and Rref and the<br />
associated computation of the new residual angle (zi+1).<br />
Thus, the attendant hardware in the angle approximation<br />
datapath can be omitted completely. It is to be noted that in<br />
the conventional CORDIC algorithm this simple<br />
arrangement for eliminating the z datapath cannot be<br />
adopted directly since the target angle is approximated by<br />
to-and-fro motion of the vector.<br />
Fig. 2. The elementary rotational section.<br />
Fig. 3. The architecture of the basic CORDIC rotator.<br />
C. The output unit<br />
The output unit consists of two fixed scaling units of 1/√2<br />
and two adder/subtractors according to (13), (14). The<br />
scaling unit is realized using a shift-and-add technique and<br />
requires five adders each, i.e. 2 –1/2 = 2 –1 + 2 –3 + 2 –4 + 2 –6 +<br />
2 -8 + 2 –14 . Thus, the overall hardware complexity of this unit<br />
is 12 16-bit adders. Depending on the quad and domain<br />
signals, this unit assigns the sign, and either scales the data<br />
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or passes it to the primary output registers. All the<br />
operations in this unit are completed in one clock cycle.<br />
The complete processor is modeled in VHDL and is<br />
synthesized using <strong>IHP</strong> 0.25 µm BiCMOS technology. The<br />
cell area of the processor core occupies 0.7 mm 2 which is<br />
equivalent to 24.7 k inverter gates in this technology. After<br />
layout, the silicon area is 0.9 mm 2 . To our knowledge, this is<br />
the smallest pipelined CORDIC rotator reported so far. The<br />
power dissipation estimated by the Synopsys Design<br />
Analyzer tool at the intended 20 MHz operation frequency is<br />
7 mW. The latency of the processor is 14 clock cycles and<br />
the throughput is 1 set of results per clock cycle. These<br />
figures show that the processor consumes little silicon area<br />
and is suitable for high-speed low power applications. The<br />
layout of the processor core is shown in Figure 4.<br />
Fig. 4. The layout of the CORDIC rotator core.<br />
IV. PERFORMANCE EVALUATION<br />
A. Area<br />
The silicon area of the proposed design compared to some<br />
existing designs is shown in Table 1 considering 16-bit<br />
implementation. To make the comparison uniform, the<br />
scaling circuitry is not considered here, since it is not<br />
reported in [4] and [5]. It can be seen clearly that the<br />
hardware requirement of the proposed one is less than the<br />
others. It is also evident that the hardware cost of the<br />
complete architecture is 22% less in terms of adders and<br />
about 53% less in terms of registers compared to that of the<br />
conventional CORDIC.<br />
Table 1<br />
A comparison of the proposed processor with some other<br />
similar processors (16-bit implementation).<br />
# full adders # registers<br />
Conventional 768 768<br />
Dawid [4] 1,280 1,984<br />
Antelo [5] 896 1,632<br />
Proposed 768 533<br />
B. Number of iterations<br />
Figure 5 shows the required number of iterations for a<br />
pseudo-random sequence of target angles in the range<br />
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[0, π/8]. On an average, the proposed processor saves 50%<br />
computations. The worst-case iteration number is 15, which<br />
occurs for the angle 21.482°.<br />
Fig. 5. Required iterations for angles in range [0, π/8].<br />
C. Accuracy<br />
The error in the x and y datapaths is plotted in Figure 6.<br />
Here, the actual VHDL model is compared with a Matlab<br />
model of an ideal CORDIC. Figure 6 shows that the worstcase<br />
error in the x and y datapaths occurs at the 11 th bit<br />
position which is similar to that of the conventional<br />
CORDIC having 16-bit wordlength.<br />
Fig. 6. Bit error position: a) x datapath; b) y datapath.<br />
D. Power<br />
The complete elimination of the z datapath in conjunction<br />
with the reduction of the total number of iterations makes<br />
the proposed scheme highly suitable for low power<br />
applications. This fact is also reflected in our synthesis<br />
results which show that the proposed processor consumes 7<br />
mW power at 20 MHz operating frequency and 2.5 V power<br />
supply.<br />
E. General discussions<br />
Though the proposed CORDIC algorithm eliminates the<br />
problem of adaptive selection of elementary rotation steps in<br />
conjunction with keeping the scale factor virtually constant,<br />
it also shows some drawbacks. Hence, the algorithm<br />
proposed here requires a variable number of iterations<br />
depending on the final target angle. Though the processor is<br />
primarily optimized for a high throughput pipeline structure,
the variable number of iterations incurs problems, when<br />
using the algorithm in the feedback mode, i.e. not pipelined.<br />
In that case, the performance is governed by the worst case<br />
delay and not by the average case delay. However, using<br />
asynchronous design or a Globally Asynchronous Locally<br />
Synchronous (GALS) methodology, one can once again get<br />
the advantage of average case performance even in the<br />
feedback mode. In the synchronous mode, though the circuit<br />
operates with the worst case delay, still power saving could<br />
be quite significant.<br />
Another problem in the proposed scheme is that the<br />
selection of the largest elementary angle depends on the<br />
wordlength (equation (3)). This angle becomes increasingly<br />
smaller as the wordlength increases. Consequently, one<br />
needs to incorporate more sections of this elementary angle<br />
in the pipeline. As a result, the conventional CORDIC is<br />
expected to outperform the proposed one in terms of<br />
hardware requirement when the wordlength reaches 20-bit.<br />
However, in that case, a hybrid scheme can be adopted to<br />
bring down the hardware cost. One may use some<br />
conventional CORDIC iteration (only unidirectional) to<br />
bring down the residual angle within the range of the scaling<br />
free CORDIC iterations and then employ the proposed<br />
algorithm. In such a case, the scale factor compensation<br />
circuitry required for those conventional CORDIC sections<br />
has to be integrated into the corresponding elementary<br />
rotational sections to avoid the generation of a final scale<br />
factor and to maintain the virtually scaling free property of<br />
the proposed algorithm. However, in general, hardware<br />
implementations with 16-bit wordlength encompass a vast<br />
application space and for that the proposed CORDIC rotator<br />
shows significantly improved performance compared to the<br />
conventional CORDIC.<br />
V. CONCLUSIONS<br />
In this article, we present a novel algorithm and architecture<br />
of a special rotational CORDIC processor that operates only<br />
in the circular coordinate space and has an unlimited angular<br />
convergence range. The algorithm adaptively selects the<br />
appropriate iteration steps and thus, converges to the target<br />
angle executing a minimum number of iterations. On an<br />
average, the number of iterations in the proposed method is<br />
about 50% less compared to that of the conventional<br />
CORDIC processor without compromising the accuracy.<br />
The novel property of the proposed algorithm is that, unlike<br />
the conventional and previously reported CORDIC, the<br />
adaptive selection of the iteration steps has no influence on<br />
the final value of the scale factor (1 or 1/√2 depending on<br />
the target angle). Thus, unlike the previously published<br />
CORDIC rotator architectures, in our scheme, it is possible<br />
to bypass the actually not needed iteration steps while<br />
keeping the scale factor virtually constant.<br />
Another novel feature of our algorithm and architecture is<br />
that in this scheme it is possible to eliminate all arithmetic<br />
computations and associated hardware in the angle<br />
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approximation datapath. This also makes the CORDIC<br />
rotator operation faster and more economic. The hardware<br />
cost of the complete architecture is 22% less in terms of<br />
adders and about 53% less in terms of registers compared to<br />
that of the conventional CORDIC. These features show the<br />
advantage of the proposed CORDIC rotator compared to the<br />
conventional CORDIC architecture. Moreover, the hardware<br />
requirement for the pre-processing unit (sign/domain<br />
detection circuitry) is very small compared to that used for<br />
the other argument reduction techniques. The reduction of<br />
area and the arithmetic computation suggests that the power<br />
efficiency of the proposed structure is better than the<br />
conventional CORDIC.<br />
Based on this algorithm, a 16-bit pipelined CORDIC<br />
processor core is designed using <strong>IHP</strong> in-house 0.25 µm<br />
BiCMOS technology. The measurement results show that<br />
the processor consumes little silicon area and is suitable for<br />
high-speed low power applications. Currently, this CORDIC<br />
processor is used as part of the Baseband Processor core in a<br />
project aiming to design a single-chip wireless modem<br />
compliant with the IEEE 802.11a standard [7].<br />
REFERENCES<br />
[1] N. Takagi, T. Asada and S. Yajima, “Redundant<br />
CORDIC methods with a constant scale factor for sine<br />
and cosine computation”, IEEE Trans. Comput., vol. 40,<br />
no. 9, pp. 989 – 995, Sept. 1991.<br />
[2] J. A. Lee and T. Lang, “Constant-factor Redundant<br />
CORDIC for Angle Calculation and Rotation”, IEEE<br />
Trans. Comput., vol. 41, no. 8, pp. 1016 – 1025, Aug.<br />
1992.<br />
[3] J. Duprat and J. M. Muller, “The CORDIC Algorithm:<br />
New Results for Fast VLSI Implementation”, IEEE<br />
Trans. Comput., vol. 42, no. 2, pp. 168 – 178, Feb. 1993.<br />
[4] H. Dawid and H. Meyr, “The differential CORDIC algorithm:<br />
Constant scale factor redundant implementation without<br />
correcting iterations”, IEEE Trans. Comput., vol. 45, no. 3, pp.<br />
307 – 318, March 1996.<br />
[5] E. Antelo, J. D. Bruguera and E. L. Zapata, “Unified mixed<br />
radix 2-4 redundant CORDIC processor”, IEEE Trans.<br />
Comput., vol. 45, no. 9, pp. 1068 – 1073, Sept. 1996.<br />
[6] A. Madisetti, A. Y. Kwentus and A. N. Willson, “A 100 MHz,<br />
16-b, direct digital frequency synthesizer with 100-dBc<br />
spurious-free dynamic range”, IEEE J. Solid-State Cir., vol. 34,<br />
no. 8, pp. 1034 – 1043, Aug. 1999.<br />
[7] M. Krstic, A. Troya, K. Maharatna and E. Grass, “Optimized<br />
Low-Power Synchronizer Design for the IEEE 802.11a<br />
Standard”, in Proceedings of the IEEE ICASSP’03, Hong<br />
Kong, P.R. of China, vol. II, pp. 321 – 324, April 2003.<br />
[8] E. Grass, B. Sarker and K. Maharatna, “A Dual Mode<br />
Synchronous/Asynchronous CORDIC Processor”, in<br />
Proceedings of the 8 th IEEE International Symposium on<br />
Asynchronous Circuits and Systems, Manchester, U. K.,<br />
pp. 76 – 83, April 2002.<br />
[9] K. Maharatna, A. S. Dhar and Swapna Banerjee, “A VLSI<br />
Array Architecture for Realization of DFT, DHT, DCT and<br />
DST”, J. Signal Processing, vol. 81, pp. 1813 – 1822, 2001.<br />
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THE SYSTEMC BEHAVIORAL MODEL OF IEEE 802.15.3<br />
MAC PROTOCOL – DESIGN AND PROFILING<br />
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Jerzy Ryman, Daniel Dietterle, Kai Dombrowski, Piotr Bubacz*<br />
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<strong>IHP</strong> Frankfurt (Oder), Germany<br />
*University of Zielona Góra, Poland<br />
[ryman | dietterle | dombro]@ihp-microelectronics.com<br />
P.Bubacz@iie.uz.zgora.pl<br />
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Abstract: This paper summarizes our work on a SystemC model of the IEEE 802.15.3<br />
medium access control (MAC) protocol. The starting point is our widely tested SDL<br />
model of this protocol. The final goal of our work is an implementation of this protocol as<br />
an embedded system. The SDL model does not provide any realistic information on<br />
performance/resource consumption, which is required for hardware/software partitioning.<br />
That leads us to SystemC as a step between the SDL behavioral model and our<br />
implementation – it provides more realistic performance information and allows modeling<br />
the hardware and software parts of the system. The complete SystemC model was<br />
profiled to make hardware/software partitioning decisions. Copyright © <strong>2004</strong> IFAC<br />
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Keywords: System design, wireless protocols, SystemC, IEEE 802.15.3, hardware/<br />
software partitioning, co-design, untimed functional modeling, SDL.<br />
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1. OVERVIEW<br />
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First, we will present the purpose of this work, then<br />
briefly describe the IEEE 802.15.3 standard and<br />
Specification and Description Language (SDL) used<br />
to design the initial model. Then we will describe the<br />
basic concepts introduced in this work. Next we will<br />
describe our experiences with profiling and finally<br />
we will conclude our paper and show possible future<br />
work.<br />
2. THE PURPOSE OF THIS WORK<br />
Our goal is to design a low-power wireless<br />
communications system for mobile battery-powered<br />
devices and sensors. It shall provide transmission of<br />
asynchronous data, as well as audio and MPEG-1<br />
encoded video streams. In other words, the<br />
communication system must provide a data<br />
throughput of 3-5 Mbps and guarantee quality of<br />
service (QoS). We found the IEEE 802.15.3 standard<br />
fulfills our requirements. After having designed a<br />
working SDL model the next step was to create<br />
something in between the solely abstract behavioral<br />
model and the target implementation. We decided to<br />
use SystemC as a promising system description<br />
language. It allows avoiding the standard waterfall<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
design scheme, using rather an almost seamless way<br />
from the behavioral model to synthesizable final<br />
code. While the Telelogic Tau SDL tool (Telelogic,<br />
2003) allows the generation of C code from the<br />
model, the result is inefficient (because of big<br />
overhead) and hardly understandable code (very long<br />
and hard to recognize names, all code in large file).<br />
Such code is hard to optimize. In contrast, the<br />
SystemC framework inherits all advantages of C++,<br />
making it a viable system description language. The<br />
code, while requiring time and effort to create, can<br />
easily be understood, debugged, profiled and<br />
optimized. There are also many ways to create the<br />
final software part of the system using an available<br />
real-time operating system. As for the hardware part,<br />
available tools for converting SystemC to<br />
synthesizable code seem to be not mature enough<br />
such that manual creation of VHDL code is<br />
unavoidable. After design, the system was tested and<br />
profiled to find the most time consuming<br />
modules/functions and consider system partitioning<br />
eventually.
3. THE IEEE 802.15.3 STANDARD<br />
3.1. General structure.<br />
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The standard (IEEE, 2003) provides a specification<br />
for the Physical (PHY) and Medium Access Control<br />
(MAC) layer for high-speed Wireless Personal Area<br />
Network (WPAN). WPANs are used to convey<br />
information over relatively short distances (up to<br />
10m) among relatively few participants. Unlike<br />
wireless local area networks (WLANs) personal<br />
networks involve little or no infrastructure. This<br />
allows small, power efficient, inexpensive solutions<br />
to be implemented for a wide range of devices. The<br />
standard differentiates 4 top-level blocks as shown<br />
below.<br />
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Fig. 1. Top-level system view.<br />
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The PHY and MAC layers have communication<br />
interfaces called Service Access Points (SAP). The<br />
interface between data and control paths is not<br />
defined and therefore left to up to the implementer.<br />
SAPs are also only a set of commands that have to be<br />
implemented leaving the details up to the designer.<br />
Power management is an important part of the<br />
standard and is based on 3 sleep modes and power<br />
level control. The standard provides also the<br />
capability for encryption (security).<br />
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3.2. The superframe.<br />
This is the base time division in the protocol. It has a<br />
length set by the PNC (0 – 65535ms) and is<br />
composed of 3 parts:<br />
- beacon – generated by the PNC,<br />
- contention access period (CAP),<br />
- channel time allocation period (CTAP).<br />
Superframe #m-1 Superframe #m Superframe #m+1<br />
Beacon<br />
#m<br />
Contention<br />
Access<br />
Period<br />
Fig. 2. Superframe.<br />
Channel Time Allocation Period<br />
MCTA MCTA<br />
1 2<br />
CTA<br />
1<br />
CTA<br />
2<br />
... CTA<br />
n<br />
Beacon is the time when the beacon frame is being<br />
broadcast by the PNC. This specific frame contains<br />
a complete set of information about the current state<br />
of the piconet, channel time allocation (CTA) and<br />
other piconet crucial data and is received by all<br />
active piconet devices. It is used also to synchronize<br />
all devices.<br />
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The CAP can be used to communicate commands<br />
and/or asynchronous data using the CSMA/CA 1<br />
contention scheme.<br />
During CTAP the TDMA 2 scheme is used (PNC<br />
makes assignments in beacon frame). There is also<br />
one specific type of CTA block: Management CTA<br />
(MCTA), which is used for communications between<br />
the DEVs and the PNC.<br />
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3.3. Network topology.<br />
The base topology is defined as a piconet –<br />
a collection of one or more logically associated<br />
devices (DEVs) that share a single identifier with a<br />
piconet coordinator (PNC) – an entity that provides<br />
time allocation, synchronization, association etc. The<br />
basic piconet containing PNC and two devices is<br />
shown below.<br />
data<br />
Fig. 3. Basic piconet.<br />
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3.4. Data flow.<br />
PNC/<br />
DEV<br />
beacon beacon<br />
DEV DEV<br />
data<br />
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data<br />
The MAC Service Access Point defines Service Data<br />
Units (SDUs) as the base unit of information. On<br />
PHY level the base data unit is a frame defined as a<br />
format of aggregated bits that are transmitted<br />
together in time. SDUs can be spread over multiple<br />
frames depending on time available for transfer, and<br />
current data rate. Standard data rates are: 11, 22<br />
(default), 33, 44, and 55 Mbps 3 . There are two base<br />
data types – asynchronous and isochronous. The<br />
latter is used for time critical, continuous applications<br />
– for example audio or video streams. There are three<br />
possible acknowledgement policies: no ack,<br />
immediate ack, and delayed ack (can be used only for<br />
streams).<br />
1 Carrier Sense Multiple Access/Collision Avoidance: each<br />
device listens to the signal level to determine when the<br />
channel is idle. Then it waits for a random amount of time<br />
before trying to send a packet. After a while, the device<br />
senses the signal level again and if the channel is free, the<br />
packet is sent. If the channel is busy, the time interval<br />
before the next attempt is increased.<br />
2 Time Division Multiple Access: devices can transmit data<br />
only in time slots assigned to them. During time slot only<br />
one device is allowed to transmit.<br />
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3 There is also an IEEE workgroup 802.15.3a that is<br />
looking into extending this standard to use with Ultra<br />
Wideband (UWB) for estimated data rates up to 1Gbps.<br />
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4. SDL LANGUAGE AND SDL MODEL<br />
4.1. SDL language<br />
SDL is an internationally standardized (ITU-T, 1999)<br />
language for specifying and describing systems. It is<br />
a formal language, which means that it is possible to<br />
analyze and interpret SDL descriptions<br />
unambiguously. It can be represented in graphical<br />
and textual descriptions. SDL has been widely used<br />
by telecommunications engineers and standards<br />
organizations for protocol specification, high-level<br />
system specification, prototyping, design, and<br />
testing.<br />
The system behavior in SDL is based on<br />
communicating extended finite state machines that<br />
are executed concurrently. State machines are<br />
represented by SDL processes. Processes<br />
communicate with each other and the system<br />
environment by exchanging asynchronous signals<br />
that may carry any number of parameters. SDL also<br />
provides timers that can be configured to generate<br />
signals at defined points in time. Each process in an<br />
SDL system contains a FIFO (First-In-First-Out)<br />
input buffer (with infinite space) into which the<br />
received signals are queued. Signal reception triggers<br />
a state transition.<br />
The important matter for us is a specific feature of<br />
SDL called save symbol (Olsen, 1994). It is used to<br />
notify the scheduler not to process the specified<br />
signal(s) immediately but to keep them for future<br />
processing.<br />
4.2. SDL model<br />
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The object-oriented SDL model (Dietterle, et al.,<br />
<strong>2004</strong>) was a base for creation of our SystemC model.<br />
It contains also a simplified PHY layer for testing<br />
purposes. While being functionally correct (that was<br />
checked in many tests), the code generated from it is<br />
inefficient (i.e. data processing algorithms are slowed<br />
down) because of the overhead (for communication<br />
and scheduling) introduced by the SDL runtime<br />
environment. It is very hard to process such code<br />
further for debugging, profiling, or any other<br />
purpose. That was the reason for creating the<br />
SystemC model.<br />
5. DESIGN PRINCIPLES<br />
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�<br />
5.1. SystemC and design concept.<br />
SystemC is a C++ class library and a methodology<br />
for designing models of software algorithms, and<br />
hardware architecture on system-level. It is offering<br />
wide abstraction level possibilities – from the pure<br />
C/C++ functional description to RTL level (Open<br />
SystemC Initiative, 2003). The optimal design flow<br />
methodology is to begin with a behavioral model<br />
based on a barebone allowing seamless (or almost<br />
seamless) flow to less abstract level. We decided to<br />
create our own platform (barebone) based on two<br />
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available elements: SystemC native elements<br />
(modules, threads and events) and the SPACE<br />
platform (Chevalier, et al., 2003). The SPACE is<br />
a system providing both untimed and timed<br />
functional (UTF/TF) simulation. The untimed<br />
functional simulation is based on a simple connection<br />
of many user modules. It does not increase the<br />
simulation time on communication between modules.<br />
That’s why we decided to use similar modularity,<br />
and a specific communication scheme. The timed<br />
functional (TF) simulation is based on an RTOS<br />
running on the instruction set simulator (ISS) so it<br />
provides real (or close to real) clock-based timing<br />
results.<br />
The reason why we decided to create our own system<br />
instead using the available one is to simplify the<br />
transition of the model from SDL to SystemC. We<br />
decided to implement only the untimed functional<br />
simulation without RTOS/ISS (but with possibility to<br />
introduce them later).<br />
The platform keeps the SystemC advantages,<br />
provides good verification environment and easy way<br />
to convert the model to use it with real time operating<br />
systems (if it contains event-driven threads).�<br />
Fig. 4. System overview<br />
�<br />
5.2. Communication concept.<br />
This is one of the main problems in modeling system<br />
containing both software and hardware parts -<br />
especially if we want to keep partitioning flexibility.<br />
While our model is much closer to the software than<br />
hardware, we wanted to have the flexibility to change<br />
part of the modules to a more hardware-like<br />
description. Therefore, we decided to create our own<br />
scheme of communication based on signals carrying<br />
data between modules. The modules communicate<br />
solely through those signals except for the few cases<br />
when direct access to memory contained in specific<br />
modules is necessary.<br />
Signals. Base signal contains target and source<br />
module identifier and command identifier. It is parent<br />
class for children that contain additionally all<br />
necessary parameters.<br />
Adapters. The signals incoming to modules ar not<br />
accepted unconditionally. Different states of the<br />
module (state machine) have different signals<br />
allowed to be consumed. In out concept this is<br />
specified by a list of accepted signals. That list is<br />
generated by a module and passed to assigned<br />
adapter. The adapter checks internal signal queue for<br />
presence of the signals from the list and if it finds it<br />
sends the signal to the module.<br />
�
The adapter also provides signal prioritization with<br />
two levels: normal and high priority. High priority is<br />
used for the reset signals. It is used to reinitialize the<br />
whole device in the same time (to avoid the<br />
hazardous situation that one device is already after<br />
reset and the other is still few signals in the queue<br />
before reset signal and have to process them).<br />
Communication manager. This is the part joining<br />
all adapters into one system and providing the signal<br />
flow between them.<br />
Module interface. In our platform, we provide the<br />
interface for the modules containing the model<br />
functionality. It is called Comm_Man_If and<br />
provides write and read methods for signals.<br />
Modules are designed to keep the SDL design – they<br />
are extended finite state machines. They contain a<br />
specific function called event_loop() that is declared<br />
as a SystemC thread. This function provides event<br />
driven sensitivity to incoming signals and/or timer<br />
events. In addition, it submits the accepted signal list<br />
to the connected adapter and reads signals from it.<br />
Based on signal contents proper function of the<br />
module is called with parameters from the current<br />
signal and the module's current state.<br />
Signals flow. The communication looks like this:<br />
- source module sends the prepared signal to<br />
its adapter using write function,<br />
- adapter sends it to the communication<br />
manager,<br />
- communication manager retrieves target<br />
identifier from signal and sends it to the<br />
correct adapter,<br />
- target module's adapter receives signal,<br />
stores it in the queue and notifies the<br />
module's event loop that it has a new signal,<br />
- target module decides when it is ready and<br />
calls read function providing the current<br />
accepted signal list to the adapter – if<br />
adapter finds signal from the list in its queue<br />
it returns the pointer to it (otherwise it<br />
returns null).<br />
6. MAC PROTOCOL DESIGN<br />
�<br />
Our model is split over multiple modules – each<br />
providing its own functionality. The modules are<br />
gathered into bigger entities called blocks. While the<br />
MAC data path is not very complex and contains<br />
only 7 modules combined into one block, in<br />
the MLME we decided to distinguish 3 sub-blocks:<br />
- Transport Engine – responsible for close<br />
cooperation with the data path (data<br />
management),<br />
- Piconet Operation – responsible for all<br />
actions connected with joining, managing,<br />
or leaving the piconet,<br />
- Request Handler – responsible for dealing<br />
with commands coming from higher layers<br />
through the MLME SAP.<br />
Also, in some cases, we decided to separate the<br />
functionality solely used by the PNC and the client<br />
device (piconet member). That gives us the<br />
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opportunity to model also simplified devices not<br />
capable of acting as PNCs (such devices are allowed<br />
by the standard). For example, the time slot<br />
allocation for the channel time allocation period<br />
(CTAP). The CTAServer is responsible for gathering<br />
time slot requests from all devices and to provide<br />
time slot assignment during the beacon generation.<br />
The CTAClient generates time slot requests that are<br />
sent do the PNC and interprets the answer.<br />
Because the system doesn’t have a shared memory<br />
block the whole used memory is declared inside the<br />
modules. TxSDUPool and RxFramePool are the two<br />
main owners of memory. In TxSDUPool we store the<br />
SDUs to transmit. RxFramePool gathers incoming<br />
frames and joins them into the complete SDU.<br />
The MAC provides CRC generation/checking, which<br />
is tested by the introduction of some random errors in<br />
our airlink model. To speed up simulation execution<br />
time we reduced the model complexity by leaving<br />
out encryption (it is optional in the standard).<br />
We can very easily test our model in different<br />
configurations with different number of stations and<br />
different parameters. The first test we made was with<br />
2 devices – one of them acting as PNC and the other<br />
as device that joins the piconet (DEV). We have<br />
tested all functionality in this configuration. Then we<br />
switched to the model containing 6 devices.<br />
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�<br />
7. PROFILING<br />
�<br />
As mentioned before in this paper, the simulation<br />
does not provide any data about time spent during the<br />
function's execution. That is the reason why we<br />
profile our system – to get the time effort spent on<br />
each module/ function. For profiling we decided to<br />
use Intel V-Tune tool. It provides timing information<br />
and dependencies between functions.<br />
The two most relevant time-consumption parameters<br />
are: self-time (the time spent in function alone) and<br />
total time (also including called sub-functions). In<br />
the profiling output we can observe what is most<br />
important to us – timing results of all interesting<br />
functions – of course those results have to be<br />
properly understood in the context. I.e. some<br />
functionality that requires response from another<br />
module is often split into two or more functions. Also<br />
some functions contain small internal state machines<br />
and are called a few times for complete execution. In<br />
the output we can see different stations separately –<br />
the problem being that it is not always clear as to<br />
which station we should assign the output result – the<br />
naming does not provide such information, so we<br />
have to analyze it to find that out.<br />
The collected data plus additional information about<br />
architectural and performance differences between<br />
system used for simulation and final<br />
processor/system can give us estimation of fulfilling<br />
time constraints based on required data rate. We can<br />
distinguish two base types of time consumption from<br />
the point of view of our modules – lets call them<br />
static and dynamic.<br />
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7.1. Static vs. dynamic time consumption.<br />
That type of time consumption is caused by initial<br />
creation and destruction of system. Also thread<br />
initialization is a constant part of the simulation.<br />
While they are slightly different for each simulation<br />
run the time differences are relatively small and we<br />
can omit them. To measure the static time<br />
consumption we run an idle testbench.<br />
The dynamic time consumption is the most<br />
interesting parameter. This type of time consumption<br />
is caused by the system functionality. To obtain this<br />
data we run a simulation testbench with the<br />
functionality we want to measure and compare the<br />
result with that from the idle testbench. Some<br />
functions have some platform-related overhead. We<br />
can remove this overhead by analyzing the functions<br />
called by them.<br />
�<br />
�<br />
7.2. Example profiling results.<br />
Here we will present example results from the<br />
testbench containing two devices, with one of them<br />
acting as a PNC, and the other one as a member of<br />
the piconet (DEV). The example testbench executes<br />
the following activities: PNC initialization, DEV<br />
association to the piconet and small (2000 bytes)<br />
isochronous stream being transmitted from the DEV<br />
to the PNC. The simulation is run for 2 seconds of<br />
simulation time (the program execution time is<br />
shorter).<br />
Table 2 TxFrame functions time results<br />
�<br />
Thread / function<br />
Main simulation:<br />
Calls Time self/total<br />
scalar del. destructor 2 2 / 78<br />
~TxFrame 2 75 / 76<br />
TxFrame 2 321 / 580<br />
PNC:<br />
event_loop 1 10916 / 18228<br />
phy_data_confirm 2055 897/897<br />
phy_tx_end_confirm 48 1/1<br />
phy_tx_start_confirm 48 19/19<br />
transmitFrame_request 48 21/21<br />
transmitFrame 1 5075 / 16694<br />
DEV:<br />
event_loop 1 10699 / 18927<br />
phy_data_confirm 2133 2112/2112<br />
phy_tx_end_confirm 14 0/0<br />
phy_tx_start_confirm 14 5/5<br />
transmitFrame_request 14 6/6<br />
transmitFrame 1 5023 / 16544<br />
�<br />
In table 2 we can observe how many times each<br />
function was called and the self-time and total time<br />
(both in µs) spent on the TxFrame functions. We can<br />
distinguish three elements – main simulation and two<br />
SystemC modules (they are seen as fibers 4 in<br />
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profiler). The main simulation thread contains<br />
construction and destruction of both station TxFrame<br />
modules. Then we have 2 stations – we can observe<br />
that most of consumed time is spent in 2 functions –<br />
event_loop and transmitFrame. That is because these<br />
functions are both defined as SystemC threads –<br />
that’s why they are called only once. The part of time<br />
spent in these functions is SystemC scheduling<br />
overhead. It is mostly the thread initialization – and<br />
that part we can see in the idle testbench. The rest is<br />
execution time. The time difference between the total<br />
and self-time has to be interpreted by looking at the<br />
called sub-functions. In the event_loop it is mostly<br />
communication effort. In the transmitFrame it is<br />
CRC calculation.<br />
The remaining functions are usual C++ functions<br />
(except of use of event notification to drive the<br />
transmitFrame thread). The phy_data_confirm is<br />
called on every incoming byte – that’s why the<br />
number of calls is much higher. The<br />
transmitFrame_request, phy_tx_start_confirm and<br />
phy_tx_end_confirm are called on only once per<br />
frame so thay are called not so often. As we can see<br />
the time spent in these functions is much smaller than<br />
the one in threads. �<br />
�<br />
�<br />
7.3. Interpretation.<br />
We can clearly see that most of the time here is spent<br />
on scheduling overhead but we can quite easily get<br />
the real functionality time consumption. For the task<br />
of finding the best hardware/software partitioning we<br />
don’t need the absolute time results – it is enough to<br />
have relative time consumption, therefore we don’t<br />
have to go into the exact time calculations. But<br />
always we have to interpret the data in the<br />
platform/module context – otherwise we can get<br />
misleading conclusions.<br />
�<br />
�<br />
8. CONCLUSION AND FUTURE WORKS<br />
�<br />
8.1. Conclusion.<br />
We can clearly see that the chosen methodology<br />
results meet our expectations. The model can be<br />
tested and profiled for very detailed output results.<br />
The design methodology (platform) can be used in<br />
the future to model other systems, or even to create<br />
some tool for automatic conversion from SDL to<br />
SystemC. The testing proved our model correctness.<br />
Profiling information provided us good base to make<br />
hardware/software partitioning decisions.<br />
4 Lightweight object that consists of a stack and a register<br />
context and can be scheduled on various threads.
8.2. Future works.<br />
For enhancing the design we plan to introduce all (3)<br />
power saving modes into our system. We are testing<br />
different real-time operating systems for integration<br />
in our final embedded system. The part of the MAC<br />
that will be ported into hardware has to be designed<br />
in VHDL language. We will test different approaches<br />
to “push” code from presented model to the final<br />
software part. That will require some modification<br />
because we want to avoid context switching between<br />
modules, as it is present in current model. So<br />
SystemC modules will in the end become just C++<br />
classes and communication will change from signals<br />
to simple function calls (except the interface to<br />
hardware).<br />
�<br />
�<br />
REFERENCES<br />
�<br />
Chevalier J., O. Benny, M. Rondonneau, G. Bois,<br />
E. M. Aboulhamid and F.-R. Boyer (1972).<br />
SPACE: A Hardware/Software SystemC<br />
Modeling Platform Including an RTOS.<br />
www.grm.polymtl.ca/circus/mwc/2003_11/<br />
Dietterle D., I. Bababanskaja, K. Dombrowski, R.<br />
Kraemer (<strong>2004</strong>). High-Level Behavioral SDL<br />
Model for the IEEE 802.15.3 MAC Protocol.<br />
In: Proc. of the 2nd International Conference on<br />
Wired/Wireless Internet Communications<br />
(WWIC).<br />
IEEE 802.15.3 Workgroup (2003). Part 15.3:<br />
Wireless Medium Access Control (MAC) and<br />
Physical Layer (PHY) Specifications for High<br />
Rate Wireless Personal Area Networks<br />
(WPANs).<br />
ITU-T (1999). ITU-T Recommendation Z.100<br />
(11/99). SDL: Specification and Description<br />
Language.<br />
Olsen A., O. Faefgemand, B. Moller-Pedersen,<br />
R. Reed, J.R.W. Smith (1991). Systems<br />
Engineering Using SDL-92, chapter 3.7.5.<br />
Elsevier Science, Netherlands<br />
Open SystemC Initiative (2003). SystemC 2.0.1<br />
Language Reference Manual.<br />
www.systemc.org<br />
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60 GHz Transceiver Circuits in SiGe:C<br />
BiCMOS Technology<br />
Wolfgang Winkler, Johannes Borngräber, Hans Gustat, Falk Korndörfer<br />
<strong>IHP</strong>, Im Technologiepark 25, D-15236 Frankfurt (Oder), Germany<br />
Phone: +49-(0)-335-5625-150 E-mail: wwinkler@ihp-microelectronics.com<br />
Abstract<br />
This paper presents the design and measurement of key<br />
circuit building blocks for a high-data-rate transceiver in<br />
the 60 GHz band. The adopted modulation scheme is<br />
ASK for simple configuration with high data rate. The<br />
circuits presented are: LNA, oscillator, mixer, modulator<br />
and demodulator. The circuits are fabricated in a<br />
0.25 �m SiGe:C BiCMOS technology.<br />
1. Introduction<br />
Traditionally, multimedia content is transferred with<br />
wired transmission systems. Because of the limited data<br />
rates, conventional WLAN systems cannot take over this<br />
task. That’s why new wireless transmission systems with<br />
data rates > 150 Mb/s are under investigation [1]. In [2] a<br />
wireless transceiver module at 60 GHz is presented<br />
showing a data-rate as high as 1.25 Gb/s. The chip set<br />
consists of different MMICs based on 0.15 �m<br />
AlGaAs/InGaAs heterojunction FET technology.<br />
For future low-cost systems it is required to realize the<br />
full transceiver in a silicon-based technology on a single<br />
chip or at least with a low chip-count. With the modern<br />
CMOS, bipolar and BiCMOS technologies developed in<br />
the last few years it seems certain to make true this goal<br />
in short term [3].<br />
This paper presents the design and measurement of key<br />
circuits for the implementation in a high data-rate<br />
60 GHz transceiver. At the present state, the circuits are<br />
completed for on-wafer measurement.<br />
2. Circuit Design<br />
Proceedings of the 30 th European Solid-State Circuits Conference<br />
September 20 - September 24, <strong>2004</strong>, Leuven, Belgium, pp. 83-86<br />
A. Transceiver Architecture<br />
Figure 1 shows the block diagram of the proposed<br />
transceiver. It is based on amplitude shift keying<br />
modulation principle (ASK). The reasons for the<br />
selection of this modulation technique are the following.<br />
- ASK is a very simple modulation scheme allowing<br />
designing and demonstrating a 60 GHz transceiver in a<br />
relatively short time-scale. It allows focusing on the<br />
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analog part of the system without having to deal with<br />
complexity, throughput and power consumption of<br />
high-data rate digital processing.<br />
- The bandwidth available in the 61 GHz ISM band is<br />
500 MHz. Thus, bandwidth efficiency is less important<br />
compared to lower frequency bands.<br />
- In a bandwidth-efficient modulation scheme like<br />
OFDM, the A/D converter (ADC) is a major problem.<br />
With the required low power consumption and<br />
throughput in mind, it is difficult to design an ADC<br />
that would suit the system needs.<br />
In summary, ASK seems well suited for a firstgeneration<br />
60 GHz transceiver, due to simplicity and<br />
power efficiency. Later implementations will certainly<br />
make use of more sophisticated modulation schemes.<br />
The transmit path of the transceiver consists of a<br />
61.25 GHz fundamental mode oscillator, a switch and a<br />
power amplifier. Between the modulator and the power<br />
amplifier a filter is inserted to reduce spurs. The receiver<br />
path consists of a low noise amplifier (LNA), a mixer, a<br />
56 GHz oscillator, a variable gain amplifier and an ASK<br />
demodulator. The circuit blocks in dashed boxes in<br />
Figure 1 are described in this paper.<br />
.<br />
Figure 1 : Transceiver block diagram
B. Low Noise Amplifier<br />
The three-stage LNA circuit is shown in Figure 2 and<br />
Figure 3. One task of the LNA design was to get<br />
unconditional stability for both on-wafer measurements<br />
and for the use of the amplifier in test board modules<br />
together with the other receiver components. Especially<br />
the use of bond wires for the connection of the ground<br />
potential (and the associated inductance) causes serious<br />
stability problems if a single-ended configuration is used.<br />
That’s why all the stages are designed in differential<br />
configuration. The input and output are trafo-coupled.<br />
The transformer coupling is useful in two ways. First, it<br />
acts as a balun for connection to a single-ended antenna.<br />
Second, the primary and secondary windings of the<br />
transformer are tuned to gat a bandpass characteristic.<br />
With this, an additional input filter in the RX path can be<br />
omitted and this function is integrated in the LNA.<br />
The circuit of one single stage of the LNA is shown in<br />
Figure 3. It is a differential stage with inductive load and<br />
with matching network at the output.<br />
Figure 2 : 60 GHz LNA.<br />
Figure 3 : Circuit of one stage of differential LNA.<br />
C. Oscillators<br />
The transceiver architecture of Figure 1 requires two<br />
oscillators working at different frequencies. One is for<br />
the transmit path at the centre of the ISM band at<br />
61.25 GHz. The other frequency in the receive path is the<br />
transmit frequency reduced by the intermediate<br />
frequency (IF). The circuit principle of both oscillators is<br />
based on a modified Colpitts principle in a symmetric<br />
configuration of negative-resistance type as shown in<br />
Figure 4 [4]. With the symmetric circuit the signal<br />
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interference via the silicon substrate is reduced in<br />
comparison to a single-ended version.<br />
The diodes and resistors in the circuit are used to define<br />
the operating point of the transistors. The tank is a<br />
symmetric circuit of the Inductors L1 and the MIM<br />
capacitor C1. The base-emitter capacitors CBE of the<br />
bipolar transistor acts in parallel to the MIM capacitors<br />
C1. For explanation, the tank can be divided into two half<br />
circuits separated by the symmetry line shown in Figure<br />
4. In operation, the oscillator-halves are working in the<br />
odd mode, such that the outputs are 180º out of phase.<br />
The nodes of the tank indicated by the symmetry line are<br />
fixed at virtual ground for the fundamental tone.<br />
The inductors L1 are designed as arms of a single loop of<br />
metal layer 4 (Aluminium with 2 µm thickness and<br />
10 µm width). The simulated inductance is 85 pH per<br />
arm. The capacitor C2 is a varicap formed by an nchannel<br />
MOS device. In order to get a wide range of<br />
capacitance variation the device is working in the whole<br />
range from depletion to accumulation. The voltage for<br />
frequency-control is applied to the n-well of the<br />
structure. With VCtrl becoming more positive, the MOS<br />
structure is driven into depletion and the capacitance will<br />
be reduced. The output of the oscillator core is connected<br />
to an amplifier in the case of the receive path. The<br />
oscillator of the transmit path is directly connected to the<br />
amplifier with switch (Figure 1).<br />
Figure 4 : Circuit of the LC oscillators used in the receive<br />
and the transmit path.<br />
D. Mixer<br />
The mixer circuit is a balanced Gilbert cell with<br />
symmetric LO and RF inputs. The differential output is<br />
connected to the VGA giving the differential signal to<br />
the demodulator.<br />
E. ASK Modulator<br />
The modulator circuit consists of bipolar transistors and<br />
a MOS transistor (Figure 5). It is a symmetric common-<br />
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base amplifier with the base connected to the drain of an<br />
n-channel MOS transistor. The gate of the MOS<br />
transistor is connected to the data input. With low<br />
voltage level at the input the MOS transistor is switched<br />
off and the common-base circuit acts as an amplifier<br />
transferring the RF to the power amplifier. With highlevel<br />
at the input the MOS transistor is switched on and<br />
the base-emitter voltage approaches zero. In this manner<br />
the amplifier is switched off and the power amplifier<br />
input is isolated from the oscillator. The advantage of the<br />
circuit is the shielding function of the bipolar base region<br />
so that a good isolation can be expected.<br />
Figure 5 : RF switch for modulation of the RF signal.<br />
F. Demodulator<br />
The amplitude-shift keying demodulation uses a fullwave<br />
rectifier together with a lowpass filter (LPF)<br />
corresponding to the maximum data rate of 1Gb/s. The<br />
block diagram is shown in Figure 6. Full-wave<br />
rectification is easily achieved using both differential<br />
inputs. The diode function is implemented using highperformance<br />
transistors, resulting in wide input<br />
frequency range (3-30GHz) giving large IF flexibility.<br />
However, the summation is a differential-to-single-ended<br />
conversion. To regenerate the differential mode, the<br />
output of an additional common-mode block (C<strong>MB</strong>) acts<br />
as the corresponding inverted signal. A subsequent<br />
differential amplifier provides sufficient gain for bit<br />
slicing.<br />
Figure 6 : ASK demodulator block diagram.<br />
3. Measurement Results<br />
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The circuits were fabricated in the <strong>IHP</strong> 0.25 �m SiGe:C<br />
BiCMOS technology. The bipolar transistors of this<br />
technology have a maximum transit frequency fT of<br />
200 GHz and also a maximum frequency of oscillation<br />
fmax of 200 GHz. In the circuits mainly bipolar transistors<br />
and passives were used. The only MOS transistor so far<br />
is the switch in the modulator circuit. Figure 7 shows<br />
photos of the presented circuits. The oscillators were<br />
characterized using an on-wafer test-system with GSprobes.<br />
The supply voltage of the oscillators and mixer is<br />
3V and the voltage of the switch, demodulator and the<br />
LNA is 2.5 V.<br />
a) b)<br />
c)<br />
e)<br />
Figure 7 : Chip Photo of a) LNA, b) mixer, c) oscillator of<br />
the receive-path, d) oscillator and switch in the<br />
transmit-path, e) receiver test structure.<br />
d)
The LNA was measured on wafer with a 110 GHz vector<br />
network analyser. The maximum gain is 9.6 dB. The<br />
gain-maximum is reached at 61 GHz, which is exactly<br />
the target frequency of the requested ISM band (Figure<br />
8). The LNA has a bandpass characteristic resulting from<br />
the tuned transformers at input and output. With this<br />
characteristic, no additional bandpass filter is needed.<br />
Figure 8 : Gain curves of the 60 GHz LNA.<br />
The transmit path was measured by applying a<br />
rectangular waveform to the data input of the modulator<br />
while the integrated oscillator generates the RF power.<br />
Figure 9 shows the output of the switch measured with<br />
an oscillograph. The signal at the data input has a<br />
frequency of 200 MHz. The output amplitude is<br />
210 mVpp. The output frequency of the oscillator is<br />
65 GHz. This frequency is too high in comparison to the<br />
target of 61.25 GHz. A redesign of this oscillator is<br />
required.<br />
Figure 9 : Signal of the oscillator with switching the<br />
output on and off.<br />
The LC oscillator in the receive path has a tuning range<br />
from 56 GHz to 60 GHz. The chosen IF frequency for<br />
the VGA and the demodulator is 4 GHz. Figure 10 shows<br />
the tuning curve of the VCO.<br />
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Figure 10 : Tuning curve of the LC oscillator in the<br />
receiver.<br />
4. Summary and Conclusions<br />
Key circuit blocks for 60 GHz high data-rate transceiver<br />
system were successfully designed and fabricated in a<br />
SiGe:C BiCMOS technology. The adopted modulation<br />
scheme was ASK for simple configuration with high data<br />
rate.<br />
The measurement results show 9.6 dB gain of the LNA<br />
at 61 GHz, 4 GHz tuning range of the oscillator in the<br />
receiver with a centre frequency of 58 GHz and an ASK<br />
modulator with good isolation properties and 210 mVpp<br />
output voltage. Further measurements and a redesign is<br />
in progress.<br />
Acknowledgements<br />
The authors acknowledge the <strong>IHP</strong> technology team for<br />
chip fabrication and the modelling team for supplying<br />
accurate models of the devices.<br />
References<br />
[1] P. Smulders, “Exploiting the 60GHz band for local<br />
wireless multimedia access: prospects and future<br />
directions,” IEEE Communications Magazine,<br />
pp.140-147, Jan. 2002, pp. 118-121.<br />
[2] K. Ohta et al., “Wireless 1.25 Gb/s transceiver<br />
module at 60GHz band,” ISSCC Dig. Tech. Papers,<br />
pp. 298-299, Feb. 2002.<br />
[3] S. Reynolds et al., “60 GHz transceiver circuits in<br />
SiGe bipolar technology,” ISSCC Dig. Tech. Papers,<br />
pp. 442-443, Feb. <strong>2004</strong>.<br />
[4] W.Winkler et al., “60 GHz and 76 GHz oscillators in<br />
0.25 �m SiGe:C BiCMOS“, IEEE Int. Solid-State<br />
Circuits Conf., February 2003, pp. 454-455.<br />
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A Low-Parasitic Collector Construction for High-Speed SiGe:C HBTs<br />
B. Heinemann, R. Barth, D. Bolze, J. Drews, P. Formanek, Th. Grabolla, U. Haak, W. Höppner, D. Knoll,<br />
K. Köpke, B. Kuck, R. Kurps, S. Marschmeyer, H. H. Richter, H. Rücker, P. Schley, D. Schmidt,<br />
W. Winkler, D. Wolansky, H.-E. Wulf, and Y. Yamamoto<br />
<strong>IHP</strong><br />
Im Technologiepark 25, 15236 Frankfurt (Oder), Germany<br />
Abstract<br />
We present a new collector construction for high-speed<br />
SiGe:C HBTs that substantially reduces the parasitic base-collector<br />
capacitance by selectively underetching of the collector<br />
region. The impact of the collector module on RF performance<br />
is demonstrated in separate bipolar processes for npn and pnp<br />
devices. A minimum gate delay of 3.2ps was achieved for<br />
CML ring oscillators with npn transistors featuring f T / f max<br />
values of 300GHz/250GHz at BV CEO = 1.8V. For pnp devices<br />
with f T / f max values of 135GHz /140GHz at BV CEO = 2.5V a<br />
gate delay of 5.9ps is demonstrated. Further vertical scaling of<br />
the doping profiles increases f T to 380GHz at BV CEO = 1.5V<br />
for npn’s and 155GHz at BV CEO = 2.3V for pnp’s, but ring oscillator<br />
speed and f max degraded.<br />
Introduction<br />
The need for still higher device speeds has led to ingenious<br />
technologies for SiGe HBTs that try to minimize internal transit<br />
times and parasitic charging times. Record f T/f max values of<br />
300GHz and above (1), (2) and very high circuit speeds, such<br />
as ring oscillator gate delays below 4 ps (3), (4), (5) resulted.<br />
Including the highest performance level, a selectively-implanted<br />
collector (SIC) is employed to provide a locally enhanced<br />
Collector Pedestal<br />
Base Poly-Si<br />
Emitter Poly-Si<br />
SiGe Base<br />
SiGe base<br />
Highly Doped Collector<br />
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collector doping, reducing both the base-collector transit time<br />
and the external base-collector capacitance (C BC ). However,<br />
conventional collector designs (Figs. 1b, c) consume more Si<br />
area for the base-collector transition than it is needed to form a<br />
low resistance current path from the active transistor to the external<br />
collector region. To address this issue, we developed a<br />
new collector construction for high speed SiGe HBTs. Substantially<br />
reduced parasitic base-collector capacitances were<br />
achieved by an undercut of the collector region (Fig. 1a). Using<br />
different types of HBTs, we show peak f T values and CML gate<br />
delays for both npn and pnp transistors that surpass the best in<br />
class data reported so far (1), (3), (6).<br />
Device Fabrication<br />
To test the new collector module, we developed a bipolar<br />
process that is shown schematically in Table I. This process is<br />
based on our 0.25 �m BiCMOS flow with elevated extrinsic<br />
base regions (4). In this work, the final RTP step was changed<br />
enabling a vertical scaling of doping profiles. On different wafers,<br />
npn and pnp transistors were produced in the same flow<br />
by inverting the doping types. The key feature of the new collector<br />
design is a selectively underetched collector pedestal<br />
(Fig. 1a). In Fig. 2, schematic drawings illustrate the fabrication<br />
of this module.<br />
Emitter Poly-Si<br />
Emitter Poly-Si<br />
Base Poly-Si SiGe Base Base Poly-Si<br />
SiGe Base<br />
a) b) c)<br />
Fig. 1. Schematic cross-section of the novel HBT structure a) with selectively underetched collector pedestal compared to previous device structures with<br />
differential b) and with selectively grown base layers c).<br />
SIC<br />
Highly Doped Collector<br />
0-7803-8684-1/04/$20.00 ©<strong>2004</strong> IEEE<br />
SIC<br />
Highly Doped Collector
Basic process flow<br />
Shallow trench isolation<br />
Deposition and structuring of poly resistors<br />
Implantation of collector contact regions<br />
Salicide protection layer for resistors<br />
Final RTA + Co salicidation<br />
2 level Al metall.<br />
After formation of shallow-trench isolation (STI), the collector<br />
module starts with the deposition of a first nitride layer<br />
that serves later as polish stop for a chemical-mechanical polishing<br />
(CMP) step. A first resist mask is patterned to remove<br />
the nitride layer over areas enclosing the transistor regions followed<br />
by the high-dose collector-well implant (Fig. 2 a). Next,<br />
a layer stack consisting of epitaxially-grown low-doped Si, of<br />
an oxide and a second nitride layer is deposited. Then, a second<br />
resist mask is applied to define a hard mask for the collector-pedestal<br />
etching (Fig. 2 b). In order to tailor the shape of<br />
the pedestal, the Si etching is performed in two steps. In the<br />
first step, the low-doped Si is removed by dry etching. Subsequently,<br />
a spacer is formed covering the side-walls of the hard<br />
mask and of the etched Si step. In the second step, the collector<br />
pedestal is undercut by a combination of dry and wet etching<br />
exploiting the different etch rates of the high-doped and lowdoped<br />
Si layers. Finally, the collector pedestal is leveled by<br />
CMP after filling up the etched regions with oxide (Fig. 2c).<br />
After removing the CMP-stop layer, poly resistors are fabricated.<br />
Next, a nitride layer, protecting the poly Si resistors, is<br />
deposited and structured to open the transistor regions. In the<br />
following epitaxy step, a Si buffer layer, the SiGe:C base layer,<br />
and a Si cap layer are grown differentially. The following<br />
process flow of the HBT module is performed as described in<br />
(4), involving the formation of the emitter and the self-aligned,<br />
elevated extrinsic base regions.<br />
After removing the nitride protection layer, the fabrication is<br />
completed with the following steps: implantation/anneal of<br />
Table I<br />
SCHEMATIC FLOW OF THE BIPOLAR PROCESS.<br />
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New collector module<br />
Deposition of nitride layer for CMP stop<br />
Opening of HBT regions<br />
High dose collector implant + RTA<br />
Si epitaxy<br />
Deposition of oxide/nitride layer stack<br />
Hard mask structuring for pedestal etching<br />
Forming pedestal spacers<br />
Pedestal etching<br />
Oxide fill and CMP<br />
Nitride wet etching<br />
HBT module<br />
Deposition of protection layer for poly resistors<br />
Opening of HBT regions<br />
HBT epitaxy<br />
Emitter window opening<br />
Emitter deposition<br />
Poly emitter structuring<br />
Selective growth of elevated extrinsic base<br />
Structuring base poly<br />
Wet etch of protection layer<br />
Reprints of<br />
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collector contact regions, applying a salicide blocking mask for<br />
the poly resistors, cobalt salicidation, and structuring of two<br />
metal layers.<br />
Fig. 3 shows the novel collector structure as TEM cross-section<br />
in comparison with a schematic drawing. In contrast to<br />
conventional constructions, the external, dielectrically-isolated<br />
base layer has a single crystalline part on the isolation. This allows<br />
us to optimize the RF performance by varying the collector<br />
window enclosure of the emitter window largely relieved of<br />
concerns arising from facet leakage or increasing RB. Device Results<br />
Gummel and output characteristics as well as fT (IC ) and<br />
fmax (IC ) curves are shown for both types of HBTs in Figs. 4 -<br />
6. Our extraction procedure for fT and fmax is outlined in Figs.<br />
6 and 9.<br />
Vertical scaling in combination with the new collector design<br />
has led to significantly improved fT values (Fig. 6) and<br />
CML ring oscillator (RO) gate delays (Figs. 7, 8) compared to<br />
our previous results. The base width is reduced due to the lower<br />
thermal budget. Simultaneously, parasitic CBE is decreased because<br />
of a reduced indiffusion of the emitter doping. Furthermore,<br />
the high collector doping is shifted closer to the base.<br />
E.g., for the npn HBT with peak fT =300GHz (Fig. 6) the total<br />
CBC at VCB =0V is reduced from 3fF to 2.5fF compared to our<br />
conventionally fabricated reference devices, despite a doubling<br />
of the area specific base-collector capacitance. This is due to a<br />
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STI<br />
Resist<br />
CMP Stop Layer<br />
Collector Implantation<br />
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large reduction of contributions to CBC from the perimeter of<br />
the device attributed to the new collector construction. The<br />
high fT and low CBC are primarily responsible for the shorter<br />
gate delays compared to our reference collector construction<br />
(4). Further improvements of fmax and of the gate delay can be<br />
expected for an optimized collector depletion width and a reduced<br />
RB .<br />
A further increase of the peak fT values was achieved for<br />
both types of bipolar transistors (dashed lines in Fig. 6, npn:<br />
300GHz -> 380GHz, pnp: 135GHz -> 155GHz) by shrinking<br />
the deposited base layer thickness. For the npn an even more<br />
aggressive collector profile was introduced in addition. However,<br />
the fmax values (see Fig. 6) and RO gate delays deteriorated.<br />
While in the pnp case, only a moderate degradation of<br />
the minimum gate delay �min from 5.9ps to 6.0ps was observed,<br />
�min increased substantially in the npn case<br />
(3.2ps ¯ >3.8ps). In future, lateral scaling of the transistor dimensions<br />
assisted by the new collector design will help us to<br />
balance fT and fmax also for higher fT values.<br />
Conclusions<br />
Resist<br />
Si 3 N 4<br />
Fig. 2. Schematic drawings of the novel collector structure after applying a) the 1st and b) 2nd mask of the collector pedestal module and c) after filling the<br />
underetched collector pedestal with oxide and before CMP.<br />
Compared to previously demonstrated concepts, the new<br />
collector design achieves lower collector capacitances, while<br />
maintaining low collector resistances and small collector-substrate<br />
junction areas. It supports heat dissipation due to the absence<br />
of deep trenches and a precise tailoring of the basecollector<br />
width for best RF performance. The new collector<br />
module paves the way for very aggressive lateral scaling at<br />
highest level of RF performance.<br />
Acknowledgment<br />
The authors thank the <strong>IHP</strong> pilotline staff for excellent support,<br />
F. Korndörfer for RF measurements, and G. Weidner for<br />
TEM cross-section preparations.<br />
Highly-doped Collector<br />
a) b) c)<br />
SiO 2<br />
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Si<br />
Emitter<br />
Base Poly-Si<br />
Emitter Si<br />
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a)<br />
b)<br />
SiGe Base<br />
Spacer<br />
Collector Pedestal<br />
References<br />
Fill Oxide<br />
Collector Pedestal<br />
SiGe Base<br />
Base Poly-Si<br />
Fig. 3. Cross-sections of the final HBT structure: a) schematic drawing<br />
and b) a TEM image.<br />
(1) J.-S. Rieh et al., "Performance and design considerations for high speed<br />
SiGe HBTs of f T/f max=375GHz/210GHz," Int. Conf. on InP and Related<br />
Met., p. 374, 2003.<br />
(2) J.-S. Rieh et al., " SiGe HBTs for milimeter-wave applications with simultaneously<br />
optimized f T and f max of 300GHz," RFIC Symp., p. 395, <strong>2004</strong>.<br />
(3) J. Böck et al., "SiGe bipolar technology for automotive radar applications,"<br />
in Proc. BCTM, p. 84, <strong>2004</strong>.<br />
(4) H. Rücker et al., "SiGe:C BiCMOS technology with 3.6 ps gate delay,"<br />
IEDM Tech. Dig., p. 121, 2003.<br />
(5) B. Jagannathan et al., "3.9 ps SiGe HBT ECL ring oscillator and transistor<br />
design for minimum gate delay," IEEE Electron Device Lett., vol 24, pp.<br />
324-326, May 2003.<br />
(6) B. Heinemann et al., "A complementary BiCMOS technology with high<br />
speed npn and pnp SiGe:C HBTs," IEDM Tech. Dig., p 117, 2003.
Base, Collector Current (A)<br />
10 -12<br />
10 -11<br />
10 -10<br />
10-9 10 -8<br />
10 -7<br />
10-6 10 -5<br />
10 -4<br />
10 -3<br />
10-2 10 -1<br />
pnp<br />
VCB = 0V<br />
T=300K<br />
npn<br />
-1.0 -0.8 -0.6 -0.4 0.4 0.6 0.8 1.0<br />
Base-Emitter Voltage (V)<br />
10 -12<br />
10 -11<br />
10 -10<br />
10-9 10 -8<br />
10 -7<br />
10-6 10 -5<br />
10 -4<br />
10 -3<br />
10-2 10 -1<br />
Fig. 4. Gummel plots of separately fabricated npn and pnp SiGe:C HBTs<br />
measured at VCB =0V with reference base doping (solid) and with<br />
reduced base width (dashed). Drawn emitter area of two transistors in<br />
parallel: AE=2 x (0.175 x 0.84)�m 2 . T=300K.<br />
f T , f max (GHz)<br />
200<br />
150<br />
100<br />
50<br />
0<br />
f max<br />
A E=2x(0.175x0.84)�m 2<br />
10 -4<br />
10 -3<br />
10 -2<br />
Collector Current (A)<br />
V CE=1.5V<br />
T=300K<br />
Fig. 6. Transit frequency f T and maximum oscillation frequency f max vs.<br />
collector current for transistors with reference base doping (solid) and<br />
with reduced base width (dashed). Corresponding Gummel plots and<br />
output characteristics are shown in Figs. 4, 5. Deembedded small-signal<br />
current gain h 21 and unilateral gain U vs. frequency were used for<br />
extrapolation of f T and f max at 30GHz with -20dB per frequency<br />
decade.<br />
�� (ps)<br />
5<br />
4<br />
3<br />
f T<br />
pnp<br />
400<br />
350<br />
npn<br />
300 fT 250<br />
200<br />
150<br />
100<br />
10 -4<br />
10 -3<br />
10 -2<br />
0<br />
Collector Current (A)<br />
Fig. 8. CML ring oscillator gate delay � vs. current per gate at different voltage<br />
swings for oscillators with npn SiGe:C HBTs. T=300K,<br />
V EE= ¯ 2.5V.<br />
50<br />
200 �V(mV)<br />
300<br />
400<br />
A E =0.175x0.84�m 2<br />
f max<br />
npn<br />
3.2ps<br />
1 10<br />
Current per Gate (mA)<br />
Collector Current (mA)<br />
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3<br />
2<br />
1<br />
0<br />
pnp npn<br />
10<br />
�I B=10�A, T=300K<br />
-3 -2 -1 0<br />
0<br />
0 1 2<br />
Collector-Emitter Voltage (V)<br />
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Selected Publications<br />
Fig. 5. Output characteristics of separately fabricated npn and pnp SiGe:C<br />
HBTs in the high injection regime with reference base doping<br />
(solid) and with reduced base width (dashed). Drawn emitter area<br />
of two transistors in parallel: AE=2 x (0.175 x 0.84)�m 2 . T=300K.<br />
The same devices with 2 transistors in parallel were used for the<br />
high frequency measurements shown in Fig. 6.<br />
� (ps)<br />
10<br />
5<br />
Fig. 7. CML ring oscillator gate delay � vs. current per gate for oscillators<br />
consisting of 53 stages with npn and pnp SiGe:C HBTs, respectively.<br />
T=300K, |V EE |=2.5V, differential voltage swing 300mV.<br />
f T, f max (GHz)<br />
400<br />
350<br />
300<br />
250<br />
200<br />
150<br />
0-7803-8684-1/04/$20.00 ©<strong>2004</strong> IEEE<br />
Fig. 9. f T and f max for two npn transistors extrapolated from various frequency<br />
points with -20dB per frequency decade. Corresponding f T<br />
and f max vs. I C curves extrapolated at 30GHz are shown in Fig. 6.<br />
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pnp<br />
5<br />
A E=0.175x0.42�m 2<br />
f max<br />
A E=0.175x0.84�m 2<br />
�V=300mV<br />
5.9ps<br />
Ref. (4)<br />
npn<br />
3.2ps<br />
1 10<br />
Current per Gate (mA)<br />
f T<br />
npn<br />
A E =2x(0.175x0.84)�m 2<br />
5 15 25 35 45<br />
Extrapolation Frequency (GHz)
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Integration of High-Performance SiGe:C HBTs with Thin-Film SOI CMOS<br />
H. Rücker, B. Heinemann, R. Barth, D. Bolze, J. Drews, O. Fursenko, T. Grabolla, U. Haak,<br />
W. Höppner, D. Knoll, S. Marschmeyer, N. Mohapatra, H. H. Richter, P. Schley, D. Schmidt,<br />
B. Tillack, G. Weidner, D. Wolansky, H.-E. Wulf, and Y. Yamamoto<br />
<strong>IHP</strong>, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany<br />
Abstract<br />
A new scheme for the integration of high-performance<br />
HBTs with thin-film SOI CMOS is demonstrated. The thickness<br />
incompatibility problem of thin-body SOI CMOS and<br />
high-performance SiGe HBTs is solved by forming HBTs on<br />
silicon islands in the BOX. Low-resistance collector wells are<br />
realized by ion implantation into the SOI substrate. SiGe:C<br />
HBTs with fT/fmax values of 220 GHz/230 GHz and a BVCEO<br />
of 2.0 V and fully-depleted CMOS transistors with 90 nm<br />
gate length are fabricated on SOI wafers with 30 nm Si thickness.<br />
Introduction<br />
SOI BiCMOS is a promising technology for mixed-signal<br />
designs. The SOI substrate can be used to enhance the performance<br />
of FET devices and on-chip passive circuit components,<br />
and to minimize isolation problems. Scaled SOI [1]<br />
and bulk [2] CMOS technologies with fT and fmax values in<br />
the 200 GHz range can facilitate the implementation of an<br />
increasing number of RF functions. However, highperformance<br />
HBTs remain indispensable for many mm-wave<br />
applications and high bandwidth communication systems due<br />
to their high voltage capability, high output resistance, low<br />
1/f noise, and the large number of proven RF circuit concepts.<br />
Moreover, integration of SiGe HBTs can significantly<br />
� Definition of active MOS areas<br />
� Gate oxide formation & poly deposition<br />
� Pre-doping of n+ and p+ gates<br />
� Gate structuring & dummy spacer formation<br />
� Selective growth of elevated S/D regions<br />
� S/D implantation<br />
� Wet etching of MOS dummy spacers<br />
� S/D extension and halo implantation<br />
� Spacer formation<br />
� Final RTA<br />
� Co salicidation<br />
� Metallization<br />
Fig. 1: SOI BiCMOS flow<br />
SOI CMOS flow<br />
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extend the accessible frequency range of RF CMOS technologies<br />
since SiGe HBTs continue to provide higher RF<br />
performance than FETs of the same technology node.<br />
The major challenge for SOI BiCMOS integration lies in<br />
the different layer thicknesses needed for HBTs and CMOS.<br />
The silicon thickness of about 1 �m required for previously<br />
demonstrated high-performance HBTs on SOI [3] is incompatible<br />
with advanced SOI CMOS. On the other hand, the<br />
performance of HBTs on thin SOI is limited by an increased<br />
collector resistance [4]. Here, we describe a new approach to<br />
integrate high-performance SiGe HBTs on thin-SOI substrates.<br />
The process is compatible with fully-depleted SOI<br />
CMOS without compromising HBT performance. The key<br />
new process feature is the formation of low-resistive collectors<br />
in the silicon substrate below the buried oxide (BOX).<br />
The HBTs are fabricated in windows of the BOX which are<br />
filled by selective silicon epitaxy. This technology does not<br />
use an epitaxially-buried subcollector or deep trench isolation<br />
therefore facilitating an easy BiCMOS integration in a costeffective<br />
manner.<br />
Device structure and fabrication<br />
The devices were fabricated on UNIBOND SOI wafers<br />
with 150 nm BOX and 30 nm Si thickness. The flow of the<br />
BiCMOS process is shown schematically in Fig. 1. The HBT<br />
HBT module<br />
� Deposit MOS protection layer<br />
� Window opening in BOX for HBTs<br />
� Selective Si epitaxy in BOX windows<br />
� Collector well and SIC implantation<br />
� HBT base epitaxy<br />
� Emitter window opening<br />
� Deposition & structuring of As doped Emitter<br />
� Formation of elevated extrinsic base regions<br />
� Base structuring<br />
� Wet etch MOS protection layer
Replacement<br />
spacer<br />
Buried oxide<br />
Substrate<br />
Elevated S/D<br />
Fig. 2: Cross section of a MOSFET after selective growth of elevated S/D<br />
regions<br />
(a)<br />
(b)<br />
Nitride<br />
Inside spacer<br />
Selective Si epitaxy<br />
Collector well<br />
Fig. 3: Schematic cross sections illustrating the fabrication of HBT collector<br />
wells. (a) After dry etching BOX windows and inside spacer formation (b)<br />
After selective epitaxy and collector well implantation. The two windows in<br />
the BOX are used for the active HBT region and the collector contact.<br />
module is fabricated after CMOS gate formation. For the<br />
CMOS process, a replacement spacer concept was adopted<br />
[5]. After structuring pre-doped poly-Si gates, dummy spacers<br />
are formed and elevated S/D regions are grown by selective<br />
epitaxy (Fig. 2). All MOSFET channel and S/D implants<br />
are performed after the HBT module. Consequently, the<br />
CMOS doping profiles are not affected by the HBT integration.<br />
The threshold voltages of the CMOS devices are adjusted<br />
by halo implants. Halos and S/D extensions are<br />
implanted after HBT fabrication and after removing the<br />
dummy spacers from the gates.<br />
The HBT module starts with the formation of windows in<br />
the BOX (Fig. 3). A sequence of dry etching, inside spacer<br />
formation and wet etching of the BOX is used to form windows<br />
which widen towards the bottom of the BOX. The<br />
windows are filled by selective Si epitaxy. The particular<br />
shape of the window reduces the collector resistance and<br />
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Fig. 4: SEM cross section of FD SOI MOSFET with elevated S/D<br />
regions and 90 nm gate length<br />
Fig. 5: SEM cross section of an HBT on SOI substrate. The highly<br />
conductive collector well is formed in the Si substrate below the buried<br />
oxide.<br />
ensures a facet-free Si surface in the active transistor area.<br />
Next, the collector wells are implanted and selectivelyimplanted<br />
collector (SIC) pedestals are formed. During the<br />
subsequent HBT process, CMOS regions are protected by an<br />
oxide/nitride layer stack which is opened in active HBT regions.<br />
The HBT stack with the C-doped SiGe base is grown<br />
by non-selective epitaxy. The fabrication of the emitter and<br />
the self-aligned elevated extrinsic base regions is performed<br />
as described in [6]. The back-end-of-line process with aluminium<br />
metallization was adopted from a 0.25 �m BiCMOS<br />
process [7]. Cross sections of the final MOS and HBT structures<br />
are shown in Figs. 4 and 5.<br />
A major concern for SOI devices is self-heating. In the present<br />
concept, the thermal resistance of the HBTs is not increased<br />
by the use of SOI wafers. This is due to the absence<br />
of the BOX below the active HBT regions. This is in contrast<br />
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100<br />
Drain Current (A/�m)<br />
10 -11<br />
10 -10<br />
10 -9<br />
10 -8<br />
10 -7<br />
10 -6<br />
10 -5<br />
10 -4<br />
10 -3<br />
V D =-1.2V V D =1.2V<br />
V D =-0.05V<br />
PMOS<br />
Reprints of<br />
Selected Publications<br />
V D =0.05V<br />
NMOS<br />
-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2<br />
Gate Voltage (V)<br />
Fig. 6: Transfer characteristics of NMOS and PMOS (Lgate=90nm) FD SOI<br />
transistors.<br />
Drain Current (�A/�m)<br />
500<br />
400<br />
PMOS<br />
NMOS<br />
V GS =1.2 V<br />
300<br />
V = GS<br />
1.0 V<br />
200 -1.2 V<br />
0.8 V<br />
100<br />
-1.0 V<br />
-0.8 V<br />
0.6 V<br />
0<br />
-1.2<br />
-0.6 V<br />
-0.8 -0.4 0.0 0.4 0.8 1.2<br />
Drain Voltage (V)<br />
Fig. 7: Output characteristics of NMOS and PMOS (Lgate=90nm) FD SOI<br />
transistors<br />
to previous approaches to SiGe HBTs on SOI which showed<br />
a significant increase of the thermal resistance due to the low<br />
thermal conductance of the buried oxide [8].<br />
Device Results<br />
A. CMOS transistors<br />
Measured transfer and output characteristics of fullydepleted<br />
NMOS and PMOS transistors with physical gate<br />
length of 90 nm and a nitrided gate oxide with<br />
Tox(acc) = 2.4 nm are shown in Figs. 6 and 7. At Vdd = 1.2 V,<br />
NMOS transistors demonstrate an Ion = 460 �A/�m and<br />
Ioff = 5 nA/�m and PMOS transistors show Ion = 210 �A/�m<br />
and Ioff = 0.4 nA/�m. The threshold voltages of NMOS and<br />
PMOS devices are 0.4 V. The sub-threshold swing at<br />
VDS = 0.05 V is 85 and 80 mV/dec for NMOS and PMOS<br />
devices, respectively.<br />
Base, Collector Current (A)<br />
10 -3<br />
10 -5<br />
10 -7<br />
10 -9<br />
10 -11<br />
10 -13<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
300<br />
200<br />
T=300K<br />
A =0.21 x 0.84 �m E<br />
0.4 0.6 0.8 1.0<br />
2<br />
V =0V CB 100<br />
0<br />
Base-Emitter Voltage (V)<br />
Current Gain<br />
Fig. 8: Gummel characteristics of an HBT with drawn emitter areas of<br />
0.21 x 0.84 �m 2 .<br />
Collector Current (mA)<br />
5<br />
4<br />
3<br />
2<br />
A = 0.21 x 0.84 �m E<br />
I (�A) B<br />
30<br />
25<br />
20<br />
15<br />
10<br />
2<br />
1<br />
5<br />
BV =2.0V<br />
CEO<br />
0<br />
0.0 0.5 1.0 1.5 2.0 2.5<br />
Collector-Emitter Voltage (V)<br />
Fig. 9: HBT output characteristics at high injection.<br />
B. HBT DC characteristics<br />
The Gummel plot of an HBT on SOI with drawn emitter<br />
area of 0.21 x 0.84 �m 2 is shown in Fig. 8. The devices have<br />
a current gain of 250 at VBE=0.7 V and ideal Gummel characteristics<br />
over more than five decades of current. Common<br />
emitter output characteristics at fixed base currents are plotted<br />
in Fig. 9 for high current injection, i.e, up to 1.5 times the<br />
collector current density at peak fT. Due to the heat contact of<br />
the devices to the substrate wafer there is only a weak indication<br />
of self-heating at high collector currents. The devices<br />
have an open-base E-C breakdown voltage BVCEO = 2.0 V<br />
and a B-C breakdown voltage BVCBO = 5.8 V. An Early voltage<br />
of 180 V was extracted from the output characteristics at<br />
fixed VBE = 0.7 V (Fig. 10).
Collector Current (�A)<br />
1.5<br />
1.0<br />
0.5<br />
0.0<br />
V A =180 V<br />
V BE =0.7 V<br />
A E =0.21 x 0.84�m 2<br />
0 1 2<br />
Collector-Emitter Voltage (V)<br />
Fig. 10: Collector current vs. collector-emitter voltage at VBE=0.7V<br />
C. HBT RF characteristics<br />
The cutoff frequency fT and the maximum oscillation frequency<br />
fmax were extracted from s-parameter measurements<br />
extrapolating at a frequency of 30 GHz with a -20 dB/decade<br />
slope from �h21� and Mason’s unilateral gain U, respectively.<br />
Fig. 11 shows fT and fmax as a function of collector<br />
current. A peak fT value of 220 GHz and a peak fmax value of<br />
230 GHz are achieved.<br />
The demonstrated fT values of the present SOI process exceed<br />
those of our previously reported 0.25 �m BiCMOS<br />
process on bulk Si wafers [6] by about 20 GHz. This improvement<br />
was achieved although the collector resistance of<br />
the HBTs on SOI wafers (RC=36 � @ AE=0.21 x 0.84 �m 2 )<br />
is about twice as high as that of the reference HBTs on bulk<br />
Si due to the different collector design. Main causes for the<br />
increased speed of the present HBTs are: (1) a steeper base<br />
doping profile due to the reduced final RTA for the 90 nm<br />
SOI CMOS flow, and (2) an optimized collector profile facilitated<br />
by SIC implantation before base epitaxy.<br />
Conclusions<br />
In summary, we have demonstrated a new integration<br />
scheme for high-performance SiGe HBTs on thin-film SOI.<br />
The thickness incompatibility problem of SOI CMOS and<br />
high-performance SiGe HBTs was solved by forming HBTs<br />
on Si islands in the BOX using implanted collector wells<br />
below the BOX. SiGe:C HBTs with fT/fmax values of<br />
220 GHz/230 GHz and fully-depleted CMOS transistors with<br />
90 nm gate length were integrated on thin-body SOI wafers.<br />
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f T , f max (GHz)<br />
250<br />
200<br />
150<br />
100<br />
50<br />
0<br />
10 -5<br />
V CE =1.5 V<br />
Reprints of<br />
Selected Publications<br />
This new scheme opens the way for BiCMOS technologies<br />
combining state-of-the-art SOI CMOS and bipolar performance.<br />
Acknowledgment<br />
The authors thank the team of the <strong>IHP</strong> pilot line for excellent<br />
support<br />
References<br />
[1] N. Zamdmer et al., “A 243-GHz Ft and 208-GHz Fmax, 90-nm SOI<br />
CMOS SoC technology with low-power millimeter wave digital and RF<br />
circuit capability”, VLSI Technology Symposium <strong>2004</strong>, pp. 98-99.<br />
[2] K. Kuhn et al., “A comparison of state-of-the-art NMOS and SiGe HBT<br />
devices for analog/mixed-signal/RF circuit applications”, VLSI Technology<br />
Symposium <strong>2004</strong>, pp.224-225.<br />
[3] K. Washio et al., “A 0.2�m 180-GHz-fmax 6.7-ps-ECL SOI/HSR selfaligned<br />
SEG SiGe HBT/CMOS technology for microwave and highspeed<br />
digital applications” IEEE TED vol. 49, p. 271, 2002.<br />
[4] J. Cai et al., “Vertical SiGe-base bipolar transistor on CMOS-compatible<br />
SOI-substrate”, BCTM 2003.<br />
[5] H. v. Meer and K. De Meyer, “The spacer/replacer concept: A viable<br />
route for sub-100 nm ultrathin-film fully-depleted SOI CMOS”, IEEE<br />
EDL vol. 23, pp. 46-48, 2002.<br />
[6] H. Rücker et al., “SiGe:C BiCMOS technology with 3.6 ps gate delay”,<br />
IEDM 2003, pp. 121-124.<br />
[7] D. Knoll et al., “BiCMOS integration of SiGe:C heterojunction bipolar<br />
transistors”, BCTM 2002, pp. 162-166.<br />
[8] M. Mastrapasqua et al., “Minimizing thermal resistance and collector-tosubstrate<br />
capacitance in SiGe BiCMOS on SOI”, IEEE EDL vol. 23, 145-<br />
147, 2002.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 101<br />
f max<br />
10 -4<br />
f T<br />
A E =2 x (0.21 x 0.84)�m 2<br />
10 -3<br />
Collector Current (A)<br />
10 -2<br />
Fig. 11: Transit frequency fT and maximum oscillation frequency fmax vs.<br />
collector current.
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102<br />
Reprints of<br />
Selected Publications<br />
A modular, low-cost SiGe:C BiCMOS process<br />
featuring high-fT and high-BVCEO transistors<br />
Dieter Knoll, Bernd Heinemann, Rainer Barth, Katrin Blum, Johannes Borngräber,<br />
Jürgen Drews, Karl-Ernst Ehwald, Gerhard Fischer, Alexander Fox, Thomas Grabolla,<br />
Ulrich Haak, Wolfgang Höppner, Falk Korndörfer, Beate Kuck, Steffen Marschmeyer,<br />
Harald Richter, Holger Rücker, Peter Schley, Detlef Schmidt, Rene Scholz,<br />
Biswanath Senapati, Bernd Tillack, Wolfgang Winkler, Dirk Wolansky, Christoph Wolf,<br />
Hans-Erich Wulf, Yuji Yamamoto, and Peter Zaumseil<br />
<strong>IHP</strong>, Im Technologiepark 25, 15 236 Frankfurt (Oder), GERMANY<br />
tel.: (+49) 335-5625-176, fax: (+49) 335-5625-327, e-mail: knoll@ihp-miroelectronics.com<br />
Abstract. We demonstrate a BiCMOS process<br />
which uses only 22 mask steps to fabricate four<br />
types of SiGe:C HBTs, in combination with a<br />
triple-well, 2.5V CMOS core and a full menu of<br />
passive elements. Key process feature is a 2-mask<br />
HBT module. We show that transistors with peak<br />
fT values ranging from 30GHz (@ 7V BVCEO) upto<br />
130GHz (@ 2.1V BVCEO) can be fabricated with<br />
this low-cost module. Among the passives are<br />
varactors, polysilicon resistors, and a 2fF/µm 2<br />
MIM-capacitor. Five layers of Al are available,<br />
including 2µm and 3µm thick upper layers. SOC<br />
ability of the process is demonstrated by a 1M-<br />
SRAM yield of typically 70%.<br />
I. INTRODUCTION<br />
BiCMOS RF performance has strongly been<br />
improved during the last years by the integration of<br />
SiGe:C HBTs which reach meanwhile transit and<br />
maximum oscillation frequencies (fT, fmax) inexcess<br />
of 200GHz [1-3]. For many applications, however,<br />
cost plays the key role. Therefore, companies develop<br />
not only high-end platforms, which are costly in the<br />
most cases, but also release low-cost derivatives to<br />
cover a wide spectrum of market segments [4, 5].<br />
Here, we present a modular SiGe:C BiCMOS<br />
platform, which compromises cost and performance<br />
at a level not published so far. In comparison to <strong>IHP</strong>’s<br />
previous low-cost process [5], the new one includes<br />
some improvements which can be summarized as<br />
follows: (1) The highest available HBT-fT was<br />
increased from 80GHz to 130GHz, while the<br />
collector-emitter breakdown voltage (BVCEO) lowered<br />
from 2.4V to 2.1V only. This improvement was<br />
achieved by adding a new chain of collector implants<br />
to the 1-mask HBT module of the previous process,<br />
and shrinking the HBT vertical dimensions. (2) HBTs<br />
with up to 20µm emitter length can be fabricated with<br />
same RF performance as sub-µm devices. This is an<br />
important result for devices which do not use a<br />
buried, highly-doped subcollector, and was achieved<br />
by improved transistor layouts. (3) The flow for the<br />
CMOS process core was modified resulting in a<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
strong yield increase for VLSI segments. The process<br />
now features a 1M-SRAM yield of typically 70%. (4)<br />
The thickness of the MIM-cap nitride layer was<br />
reduced to double the capacitance density. The new<br />
capacitor combines 2fF/µm 2 density with a second<br />
order voltage coefficient of less than 10ppm/V 2 .(5)A<br />
fifth, 3µm thick Al layer was added to the 2µm thick<br />
upper metal level of the previous process to get higher<br />
quality factors of BEOL-based passive elements.<br />
Further process features are a MOS and a p + n<br />
junction varactor with tuning ranges of 3.2:1 and<br />
1.7:1, respectively, and several polysilicon resistors<br />
with up to 2.3kΩ sheet resistance.<br />
For fabricating the full device menu, the new<br />
process uses only 22 mask steps.<br />
STI (1), DEEP N IMP (2)<br />
HP-HBT IMP (3)<br />
NWELLIMP(4),PWELLIMP(5)<br />
GATE STACK DEPOSITION<br />
HBT MODULE (6)<br />
GATE (7), SPACER, NSD IMP (8), PSD IMP (9)<br />
SALBLOCK (10), Co SALICIDE, CONT (11)<br />
MET1 (12), VIA1 (13), MIM (14)<br />
MET2 (15), VIA2 (16), MET3 (17), VIA3 (18)<br />
MET4 (19), VIA4 (20), MET5 (21),PAD(22)<br />
Figure 1. Flow diagram of the BiCMOS process. The<br />
numbers included illustrate the mask step sequence.<br />
II. BiCMOS PROCESS FLOW<br />
Fig. 1 shows a flow diagram of the complete<br />
process. In comparison to the previous, 19-mask<br />
BiCMOS process, we added 3 mask steps, the first<br />
one for the fabrication of the new, high-fT HBT, and<br />
the further ones for the integration of the 5 th Al layer.
“C”<br />
CoSi<br />
“E”<br />
“B”<br />
SiGe:C<br />
STI<br />
Oxide Spacer n + Emitter<br />
Figure 2. SEM cross-section of a SiGe:C HBT,<br />
fabricated with a CMP-based HBT module.<br />
The particular transistor structure, shown in Fig. 2,<br />
results from the application of the previously<br />
described 1-mask HBT module which uses CMP for<br />
separating the highly doped emitter from the external<br />
base [5]. CMOS processing steps such as the gate RIE<br />
and the PMOS S/D implantation (PSD) are<br />
simultaneously used for structuring and doping the<br />
HBT external base regions, respectively.<br />
EMITTER<br />
SIC<br />
COLLWELL<br />
SIC<br />
COLLWELL<br />
GATE=EXT. BASE<br />
SIC<br />
COLLWELL<br />
COLLWELL<br />
p + Gate<br />
Poly<br />
Figure 3. Schematic cross-sections of the different<br />
HBTs fabricated in the 22-mask BiCMOS process.<br />
Fig. 3 shows cross-sections of the 4 types of HBTs<br />
fabricated by the new process. The collector regions<br />
W<br />
NSD<br />
HBT1<br />
NWELL<br />
DEEP N IMP<br />
STI<br />
DEEP N IMP<br />
NSD<br />
NSD<br />
SIC NSD<br />
HP-HBT IMP<br />
HBT2<br />
NWELL<br />
HBT3<br />
NWELL<br />
DEEP N IMP<br />
HBT4<br />
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of HBT1, HBT2, and HBT3 are formed identically to<br />
the previous process. For the collector region of the<br />
new, high-fT HBT4, we use an implant chain (masked<br />
HP-HBT IMP, see Fig. 1) taken from our first high<br />
performance BiCMOS generation [6, 7]. Compared to<br />
the epi process applied previously, we reduced, by a<br />
few nm, the widths of the Si layers grown before and<br />
after SiGe:C base layer deposition, respectively.<br />
III. HBT PERFORMANCE<br />
Fig. 4 shows fT and fmax as a function of the<br />
collector current for HBT4s differing in the emitter<br />
width. The transistors reach a peak fT value of<br />
130GHz and fmax values up to 150GHz, at 2.1V<br />
BVCEO (Fig. 5), and a current gain of about 300 (Fig.<br />
6). DC and RF parameters of the higher-voltage<br />
HBTs are summarized in Table 1. These transistors<br />
show combinations of fT and BVCEO values ranging<br />
from 30GHz/7V up to 90GHz/2.1V.<br />
f T or f max (GHz)<br />
140<br />
120<br />
100<br />
80<br />
60<br />
40<br />
20<br />
A E,eff =10x(w E,eff x0.82)µm 2<br />
w E,eff =0.24µm<br />
10 -4<br />
f max<br />
Figure 4. Transit (fT) and max. oscillation frequency<br />
(fmax) vs. collector current for HBT4s differing in the<br />
effective emitter width (by extrapolating the 30GHz,<br />
de-embedded h21 and U values, respectively).<br />
Device<br />
Parameter<br />
Value Unit Remark<br />
HBTs Beta 300 VBE= 0.7V<br />
1-4 BVEBO 2.5 V @ 1µA<br />
fT/fmax * 30/70 GHz VCE= 2V<br />
HBT1 BVCEO >7 V 0.5mA<br />
BVCBO >20 V @ 0.1µA<br />
fT/fmax * 50/100 GHz VCE= 2V<br />
HBT2 BVCEO 4 V 0.5mA<br />
BVCBO 17 V @ 0.1µA<br />
HBT3<br />
fT/fmax *<br />
fT/fmax #<br />
BVCEO<br />
90/90<br />
90/95<br />
2.1<br />
GHz<br />
V<br />
VCE= 1.5V<br />
0.5mA<br />
BVCBO 7.7 V @ 0.1µA<br />
HBT4<br />
fT/fmax* 130/138<br />
fT/fmax # 130/150<br />
BVCEO 2.1<br />
GHz<br />
V<br />
VCE= 1.5V<br />
0.5mA<br />
BVCBO 6.8 V @ 0.1µA<br />
*AE,eff= (0.4x0.82) µm 2 ; # AE,eff= (0.24x0.82) µm 2<br />
Table 1. Parameters of the four types of HBTs<br />
fabricated in the 22-mask BiCMOS process<br />
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f T<br />
10 -3<br />
w E,eff =0.4µm<br />
V CE =1.5V<br />
10 -2<br />
Collector Current (A)
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Collector Current (A)<br />
Base or Collector Current (A)<br />
Reprints of<br />
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0.020<br />
0.016<br />
A = 10x(0.24x0.82) µm E,eff 100<br />
80<br />
0.012<br />
60<br />
40<br />
0.008<br />
20<br />
0.004<br />
0.000<br />
0.0 0.5 1.0 1.5 2.0<br />
0<br />
2.5<br />
2<br />
I (µA) B<br />
Collector-Emitter Voltage (V)<br />
Figure 5. HBT4 output characteristics.<br />
Fig. 6. Gummel plot of an HBT4.<br />
Fig. 7 demonstrates very similar RF performance<br />
for HBTs with short and long emitter fingers. This is<br />
an important result for a technology which does<br />
without a costly module for fabricating an epitaxially<br />
buried, highly-doped subcollector. It was achieved by<br />
improved device layouts facilitating a good RB<br />
scaling behavior without compromising RC.<br />
f T or f max (GHz)<br />
10 -3<br />
10 -5<br />
10 -7<br />
10 -9<br />
10 -11<br />
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0<br />
Base-Emitter Voltage (V)<br />
80<br />
70<br />
60<br />
50<br />
40<br />
30<br />
20<br />
10<br />
0<br />
A E,eff = 10x(0.24x0.82) µm 2<br />
V CE =2V<br />
l E,eff<br />
10 -5<br />
fT<br />
10 -4<br />
Fig. 7. Transit (fT) and max. oscillation frequency<br />
(fmax) vs. collector current for HBT1s differing in the<br />
emitter length (effective emitter width is 0.4µm).<br />
Fig. 8 compares yield data of arrays with different<br />
HBT types. Obviously, the yield of HBT4-arrays is<br />
only slightly lower compared to that of the lower<br />
doped devices demonstrating that the high collector<br />
doping of HBT4 does not lead to serious defect<br />
issues.<br />
I C<br />
f max<br />
I B<br />
10 -3<br />
V CB =0V<br />
0.82µm 20µm<br />
f T<br />
Collector Current (A)<br />
f max<br />
10 -2<br />
Yield of 4k HBT-Arrays (%)<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Fig. 8. Wafer yield of 4k arrays with different types of<br />
HBTs (AE,eff= 4096x(0.4x0.82) µm 2 ).<br />
IV. VLSI ABILITY OF THE PROCESS<br />
As test vehicle for the VLSI ability of the new<br />
process we used a 1M-SRAM with a 6-transistor cell.<br />
To study the impact of HBT integration on the yield<br />
of this 6-million transistor device, lots were fabricated<br />
with and without HBT module. Fig. 9 demonstrates a<br />
typical SRAM yield of around 70% for both cases<br />
showing that our HBT integration scheme is modular<br />
and has no negative impact on the yield of dense<br />
CMOS sections. Moreover, it shows that the new<br />
BiCMOS process guarantees high yield for VLSI<br />
CMOS segments necessary for a cost effective<br />
fabrication of RF-SOC’s. Note that we considered an<br />
SRAM to be a good device only in the case that it<br />
showed a Bit Error Count (BEC) of zero for all of the<br />
24 tests we applied in total (“solid 0”, “solid 1”, and<br />
several “checkerboard” tests were carried out at four<br />
different supply voltages ranging from 1.2V to 3.2V).<br />
1M-SRAM Wafer Yield (%)<br />
100<br />
90<br />
80<br />
70<br />
100<br />
80<br />
60<br />
40<br />
I CEs (@V CB =2V) meas. on 45 wafer sites<br />
B D<br />
A C<br />
CMOS<br />
20<br />
SRAMSmeasuredon45wafersites<br />
BEC= 0<br />
E<br />
HBT2<br />
HBT1<br />
HBT4<br />
60<br />
0 5 10 15 20 25 30 35<br />
Wafer ID<br />
G<br />
F<br />
H<br />
BiCMOS lots<br />
0 20 40 60 80 100 120 14 0 16 0 180 200 220 240<br />
Fig. 9. Yield trend chart for 1M-SRAMs fabricated in<br />
a complete BiCMOS flow or a flow w/o HBT module.<br />
The MOS parameters of the BiCMOS process are<br />
summarized in Table 2.<br />
V. PASSIVE ELEMENTS<br />
The data of passive elements available in the<br />
process are also summarized in Table 2. These<br />
elements, such as the accumulation type MOS<br />
varactor with wide tuning range or the 250Ω, low-<br />
TCR polysilicon resistor show state-of-the-art<br />
properties. Predefined inductors with inductance<br />
I<br />
J<br />
Lot ID (A-M)<br />
K<br />
L<br />
M
values ranging from 1 to 15nH and quality factors<br />
ranging from 6 (for a 15nH inductor @ 2.4GHz) to 16<br />
(for a 1nH inductor @ 5.8GHz) can also be used.<br />
Device<br />
Parameter<br />
Value Unit Remark<br />
IDS<br />
IOFF<br />
570<br />
3<br />
µA/µm<br />
pA/µm VDS= NMOS/<br />
Isolated<br />
NMOS<br />
VT<br />
LEFF<br />
0.62<br />
0.22<br />
V<br />
µm<br />
2.5V<br />
IDS<br />
IOFF<br />
290<br />
3<br />
µA/µm<br />
pA/µm VDS=<br />
PMOS<br />
VT -0.51 V<br />
2.5V<br />
LEFF 0.185 µm<br />
MOS<br />
Tuning<br />
range<br />
3.2:1<br />
Varactor<br />
Q 75/25<br />
@5GHz for<br />
low/high C<br />
p<br />
Tuning<br />
range<br />
1.7:1<br />
+ n<br />
Varactor<br />
Q 35/20<br />
@5GHz for<br />
low/high C<br />
Salicide RS 6 Ωsq<br />
Resistor TCR 2800 ppm/°C<br />
RS 250 Ωsq p + Poly-Si<br />
Resistor<br />
TCR(a)<br />
TCR(b)<br />
-21<br />
110<br />
ppm/°C<br />
ppm/°C<br />
poly<br />
(-30)-27°C<br />
27-125°C<br />
Poly-Si RS 2300 Ωsq low-doped<br />
Resistor TCR -2500 ppm/°C poly<br />
Unit C 2 fF/µm 2<br />
VCC2 17 V 1pA/µm 2<br />
Table 2. MOS devices and passive elements of the 22mask<br />
BiCMOS process.<br />
Fig. 10 shows the C(V) characteristics of the new,<br />
2fF/µm 2 MIM-cap, demonstrating a very low second<br />
order voltage coefficient of less than 10ppm/V 2 .For<br />
this MIM-cap, a much thinner nitride layer is used,<br />
compared to the previous process. However, lifetime<br />
(see insertion of Fig. 10) and breakdown voltage<br />
(Table 2) are high enough for the targeted<br />
applications of the BiCMOS process.<br />
Normalized Capacitance<br />
1.0004<br />
1.0003<br />
1.0002<br />
TTBD (sec)<br />
10 3<br />
10 5<br />
10 7<br />
10 1<br />
T= 125°C<br />
6 8 10 12 14 16<br />
1.0001<br />
1.0000<br />
0.9999<br />
VCC1= 34.4ppm/V VCC2= 8.3ppm/V<br />
-6 -4 -2 0 2 4 6<br />
2<br />
Voltage (V)<br />
T= 27°C<br />
Voltage (V)<br />
Fig. 10. C(V) characteristics of the 2fF/µm 2 MIMcapacitor<br />
(A= (202x102) µm 2 ). Inserted is a lifetime<br />
extrapolation curve.<br />
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One benefit we take from the fifth, thick metal<br />
layer is demonstrated by the low losses of<br />
transmission lines fabricated with this layer (Fig. 11).<br />
S 21 Magnitude (dB)<br />
-1<br />
-2<br />
-3<br />
-4<br />
-5<br />
-6<br />
-7<br />
T-Line Length: 5.05mm<br />
T-Line Width: 12.2µm<br />
0 20 40 60 80 100 120<br />
Frequency (GHz)<br />
Fig. 11. S12 magnitude vs. frequency for a<br />
transmission line.<br />
VI. SUMMARY AND CONCLUSIONS<br />
In summary, we have demonstrated a new SiGe:C<br />
BiCMOS process of exceptional simplicity, flexibility<br />
and performance. It offers four different HBT types,<br />
including a 130GHz-fT and a 7V-BVCEO transistor, by<br />
adding only two mask levels to standard RF CMOS.<br />
The combination of this two-mask HBT module with<br />
a highly integrated digital CMOS backbone and<br />
advanced passive elements meets the needs of the vast<br />
majority of applications in a cost-effective way.<br />
IX. REFERENCES<br />
[1] B.A. Orner et al., “A 0.13µm BiCMOS technology<br />
featuring a 200/280GHz (fT/fmax) SiGeHBT”,Proc. of the<br />
2003 BCTM, pp. 203-206.<br />
[2] H. Rücker et al., “SiGe:C BiCMOS technology with<br />
3.6ps gate delay”, IEDM 2003 Tech Dig., pp. 121-124.<br />
[3] T. Hashimoto et al., “Direction to improve SiGe<br />
BiCMOS technology featuring 200-GHz HBT and 80nm<br />
gate CMOS”, IEDM 2003 Tech. Dig., p. 129-132.<br />
[4] N. Feilchenfeld et al., “High performance, low<br />
complexity 0.18µm SiGe BiCMOS technology for wireless<br />
circuit applications”, Proc. of the 2002 BCTM,p.197-200.<br />
[5] D. Knoll et al., “A flexible, low-cost, high performance<br />
SiGe:C BiCMOS process with a one-mask HBT module”,<br />
IEDM 2002 Tech. Dig., pp. 783-786.<br />
[6] B. Heinemann et al., “Cost-effective high-performance<br />
high-voltage SiGe:C HBTs with 100GHz fT and BVCEO xfT products exceeding 220VGHz”, IEDM 2001 Tech. Dig., pp.<br />
348-351.<br />
[7] D. Knoll et al., “BiCMOS integration of SiGe:C<br />
heterojunction bipolar transistors”, Proc. of the 2002<br />
BCTM, pp. 162-166.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 105
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106<br />
Reprints of<br />
Selected Publications<br />
A Two Mask Complementary LDMOS Module<br />
Integrated in a 0.25 µm SiGe:C BiCMOS Platform<br />
K.E. Ehwald, A. Fischer, F. Fuernhammer, W. Winkler, B. Senapati, R. Barth, D. Bolze,<br />
B. Heinemann, D. Knoll, H. Ruecker, D. Schmidt, I. Shevchenko, R. Sorge, H.-E. Wulf<br />
<strong>IHP</strong>, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany,<br />
Tel: +49 335 /5625 780, Fax: +49 335/ 5625 327, Email: Ehwald@ihp-microelectronics.com<br />
Abstract:<br />
The integration of RF n-and p-LDMOS transistors into a<br />
CMOS or BiCMOS platform allows the use of<br />
complementary circuit techniques and enables efficient<br />
solutions for linear RF power amplifiers, power<br />
switches, DC/DC converters and high voltage IO<br />
circuits. We demonstrate the modular integration of high<br />
performance n-LDMOS devices and a record p-LDMOS<br />
transistor into a low-cost 0.25µm SiGeC RF-BiCMOS<br />
technology. In addition to n-LDMOS transistors on psubstrate<br />
with breakdown voltages near 30V, isolated n-<br />
LDMOS- and p-LDMOS transistors can be<br />
manufactured on the same wafer and achieve<br />
breakdown voltages of 11.5V and 13.5V and fT/fmax<br />
values of 23/48 GHz or 13/30 GHz, respectively.<br />
1. Introduction<br />
RF LDMOS transistors are promising candidates to<br />
realize integrated power amplifiers for wireless<br />
applications and other high-speed, high-voltage circuits,<br />
e.g. for IO ports. Integration of n-LDMOS devices in RF<br />
BiCMOS technologies has been demonstrated previously<br />
[1,2]. In this paper we demonstrate the additional<br />
integration of p-LDMOS transistors into a low cost<br />
0.25µm BiCMOS process to enable the application of<br />
complementary circuit techniques. The approach<br />
described in [1] for the n-LDMOS integration into a<br />
0.25µm BiCMOS process, was applied in this work<br />
analogously to integrate the p-LDMOS devices. In<br />
addition to the new p-LDMOS and to the n-LDMOS<br />
devices described in [1], a new high performance<br />
n-LDMOS transistor, isolated from the p-substrate by a<br />
high energy implanted n-buried layer, was also realized.<br />
This way, n- and p-LDMOS transistors both isolated<br />
from the p-substrate can be manufactured at the same<br />
wafer. The underlying RF SiGe:C BiCMOS process with<br />
only 19 mask steps was published in [3]. It offers 2.5V nand<br />
p-MOS standard transistors, an isolated n-MOS<br />
transistor, three kinds of npn HBT’s, three poly resistors,<br />
MIM capacitors and four metal layers with a thick top<br />
metal enabling high Q inductors. The implementation of<br />
the new complementary LDMOS module into this<br />
SiGe:C BiCMOS platform is an excellent base to realize<br />
cost-effective, highly-integrated digital radio transceiver<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
architectures at microwave frequencies as well as<br />
integrated fast power switches, high voltage I/O’s and<br />
other internal high voltage circuits, e.g. for embedded<br />
flash memories.<br />
2. Technology and Device Construction<br />
The integration scheme for the n- and p-LDMOS<br />
transistors is shown in Fig. 1. As for the n-LDMOS, also<br />
for the p-LDMOS the thin gate oxide (5nm), the gate<br />
polysilicon, the highly doped S/D-regions and the<br />
correspondent well implants of the standard MOS<br />
transistors are used together with a special LDD doping<br />
profile in the drift region, which enables its full depletion<br />
already at medium drain voltages, and a high breakdown<br />
voltage. The salicide blocker mask, necessary for the<br />
poly resistors, prevents the silicide formation in the drift<br />
region between the highly doped drain and the gate.<br />
Using this scheme, four preferred types of LDMOS<br />
constructions (n-LDMOS1, n-LDMOS2, n-LDMOS3<br />
and p-LDMOS) can be realized on the same wafer. The<br />
position of the well- and LDD implants in these<br />
constructions is visible from schematic cross sections in<br />
Figs. 2a-2d. To ensure optimum connection to the gate<br />
inversion layer, the masked LDD implantations n-LDD1<br />
and p-LDD for n-and p-LDMOS are carried out<br />
immediately after structuring the poly gates before<br />
forming the gate spacers. A blanket n-LDD2<br />
implantation (P and shallow BF2 [1] ) is employed after<br />
the high dose S/D implants, but before S/D-RTA. Fig. 2a<br />
shows the n-LDMOS1 device as described in [1]. This<br />
device construction is applicable up to drain voltages of<br />
about 30V. The drift region outside of the p-well is<br />
doped by the n-LDD2 implantation only, resulting in a<br />
doping profile with a reduced net concentration in this<br />
area. The masked n-LDD1 implant is restricted to a small<br />
part of the drift region near the gate, but overlaps the<br />
poly gate and the p-well. A simplification of this layout<br />
is possible, if a BVDS value of about 16-17 V is<br />
sufficient, corresponding to a (drawn) drift length ≤<br />
0.8µm. In this case the n-LDD1 implantation mask can<br />
be open in the whole drift and gate region, without<br />
degrading the static or dynamic electrical parameters, but<br />
reducing the sensitivity to mask misalignment. Figs. 2b<br />
and 2c show the n-LDMOS2 and n-LDMOS3 device<br />
constructions with substrate connected and with isolated
p-well, respectively, both with the n-LDD1 being<br />
implanted in the complete drift region.<br />
Fig. 2d shows the cross section of the p-LDMOS<br />
device. Here, similar as for n-LDMOS2, the well<br />
implantations are masked in the drain area and in the<br />
drift region near the drain and the mask window for the<br />
p-LDD implantation is open completely in the active<br />
area of the transistor.<br />
Note, that the integration of the four LDMOS<br />
transistor constructions on the same wafer requires only<br />
2 additional masks on top of the SiGe:C BiCMOS flow,<br />
resulting in a total number of only 21 mask steps for the<br />
complete process.<br />
3. Electrical Results and Discussion<br />
Typical electrical results of the four LDMOS<br />
constructions for different drift lengths are summarized<br />
in Table 1. The parameters of the n-LDMOS1 transistors<br />
for drift lengths of 1.0 and 0.6 µm are very similar to<br />
those of the corresponding devices described in [1],<br />
showing that the modified process flow has no<br />
significant impact on the electrical parameters of the n-<br />
LDMOS devices. Also, the throughout n-LDD1<br />
implantation, applied to the 0.6µm n-LDMOS2 device,<br />
causes no essential drawbacks with respect to its static or<br />
dynamic parameters. This shows, that for this drift length<br />
the electrical field distribution in the drift region at a<br />
voltage close to breakdown is not changed significantly<br />
by a higher net doping in the very small LDD region “A”<br />
between the p-well edge and the n + drain (Fig. 2b). This<br />
is in contrast to the results obtained for a drift length of<br />
1.4µm with a much larger LDD region ”A”, where the<br />
breakdown voltage is drastically reduced from 29V to<br />
about 18V, if the n-LDD1 doping was implanted in the<br />
complete active transistor region (compare n-LDMOS1<br />
and n-LDMOS2 with LDrift = 1.4µm in Fig. 3).<br />
The isolated n-LDMOS3 transistor shows RF<br />
characteristics very similar to n-LDMOS1 and<br />
n-LDMOS2, reaching fT/fmax of 24GHz/48GHz<br />
respectively (Table 1). However, BVDS is limited by the<br />
n + -drain to p-well breakdown to about 11.5V. So, BVDS<br />
for nLDMOD3 is nearly independent from the driftlength<br />
in the range between 0.8µm and 0.4µm, as shown<br />
in Fig. 4.<br />
DC characteristics of the p-LDMOS device are<br />
shown in Figs. 5a–5c. A BVDS value of 13.5V combined<br />
with a RON of 11.5 Ωmm was obtained (Table 1). Similar<br />
to the isolated n-LDMOS3, BVDS does not rise if the drift<br />
length is increased above 0.6µm. It is limited then by the<br />
vertical breakdown between the p + -drain and the highenergy<br />
implanted buried layer. The relatively low RON<br />
value of the p-LDMOS results from the fact, that in<br />
contrast to the n-LDD1 and n-LDD2 implantations of the<br />
n-LDMOS devices, calculated for breakdown voltages<br />
up to 30V, the p-LDD implantation could be optimized<br />
for a relatively low breakdown voltage and a fixed low<br />
drift length.<br />
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Figs. 6 and 7 show for the p-LDMOS transistor the<br />
results of S-parameter measurements, using an HP 8510<br />
network analyzer. At VDS= 8V, fT values up to 13.5 GHz<br />
and fmax values up to 32 GHz were measured. These are,<br />
according to our knowledge, the highest cutoff<br />
frequencies for p-LDMOS transistors published up to<br />
now. DC and RF modeling of the different LDMOS<br />
transistors was carried out using BSIM3V3 with adapted<br />
sub-circuits. The excellent fitting of RF and DC<br />
measurement data is shown for the p-LDMOS in Figs. 5a<br />
and 6 and for the isolated n-LDMOS transistor in Figs. 8<br />
and 9. Based on these models complementary power<br />
amplifiers and DC/DC converters, taking advantage of<br />
the modular LDMOS technology module described here,<br />
are currently in development .<br />
4. Summary and Conclusions<br />
Complementary high performance RF LDMOS<br />
transistors with isolated wells were integrated into a lowcost<br />
0.25µm SiGe:C RF-BiCMOS platform, using two<br />
additional masks. The n- and p-LDMOS devices are<br />
characterized and modeled. BVDS of 11.5V and -13.5V<br />
as well as fT/fmax values of 23/48 GHz and 13.5/32 GHz<br />
were demonstrated for isolated n-LDMOS and p-<br />
LDMOS, respectively, in addition to n-LDMOS<br />
transistors with p-well connected to p-substrate, offering<br />
breakdown voltages up to 30V. The described approach<br />
to integrate complementary RF LDMOS transistors can<br />
be extended to 0.18µm and 0.13µm CMOS and<br />
BiCMOS technology generations. This enables costeffective<br />
solutions for power devices in future “system-<br />
on-a-chip” wireless and broadband applications such as<br />
handset-power amplifiers, integrated laser drivers, power<br />
switches and high voltage circuits for I/O interfaces and<br />
Flash programming.<br />
References<br />
[1] K.-E. Ehwald, B. Heinemann, W. Roepke, W.<br />
Winkler, H. Rücker, F. Fuernhammer, D. Knoll, R.<br />
Barth, B. Hunger, H.E. Wulf, R. Pazirandeh, and N.<br />
Ilkov, “High Performance RF LDMOS Transistors with<br />
5nm Gate Oxide in a 0.25µm SiGe:C BiCMOS<br />
Technology", IEDM Tech Dig., pp. 895 (2001)<br />
[2] B. Szelag, H. Baudry, D. Muller, A. Giry, D.<br />
Lenoble, B. Reynard, D. Pache, A. Monroy, “Integration<br />
and Optimization of a high performance RF Lateral<br />
DMOS in an advanced BiCMOS Technology”,<br />
ESSDERC 2003, Proceedings of the 33 nd European<br />
Solid-State Device Research Conference<br />
[3] D. Knoll, K.-E. Ehwald, B. Heinemann, A. Fox, K.<br />
Blum, H. Rücker, F. Fürnhammer, B. Senapati, R. Barth,<br />
U. Haak, W. Höppner, J. Drews, R. Kurps, S.<br />
Marschmeyer, H.H. Richter, T. Grabolla, B. Kuck, O.<br />
Fursenko, P. Schley, B. Tillack, Y. Yamamoto, K.<br />
Köpke, H.-E. Wulf, D. Wolansky and W. Winkler,<br />
“A Flexible, Low-Cost, High Performance SiGe:C<br />
BiCMOS Process with a One-Mask HBT Module”,<br />
IEDM Tech Dig., pp. 775 (2002)<br />
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108<br />
SHALLOW<br />
TRENCH<br />
DEEP<br />
n-WELL<br />
p-WELL<br />
n-WELL<br />
GATE OX &<br />
POLY DEP.<br />
Reprints of<br />
Selected Publications<br />
Fig. 1: Integration of n- and p-LDMOS devices into the<br />
RF-BiCMOS process flow.<br />
S G<br />
p + n +<br />
p-well<br />
-<br />
p-substrate<br />
Fig. 2a: n-LDMOS1 device as described in [1]<br />
p + n +<br />
p-substrate<br />
Fig. 2b: n-LDMOS2 device with blanket n-LDD1 and<br />
n-LDD2 implantations.<br />
B<br />
S G<br />
p-well<br />
BIPOLAR<br />
MODULE<br />
GATE<br />
PATTERNING<br />
n/p -LDMOS<br />
(masked)<br />
GATE<br />
SPACER<br />
n-LDD1 n-LDD2<br />
+n-LDD2 (P+BF2) S G<br />
n +<br />
silicide<br />
n + S/D<br />
p + S/D<br />
n-LDMOS<br />
(maskless)<br />
RESISTOR<br />
SALICIDE<br />
4LM, MIM<br />
BACK-END<br />
STI<br />
n-LDD1 + n-LDD2<br />
region “A”<br />
n-LDD1+ n-LDD2<br />
p-well<br />
n-buried layer<br />
p-substrate<br />
Fig. 2c: Substrate isolated n-LDMOS3 device with<br />
blanket n-LDD1 and n-LDD2 implantations.<br />
D<br />
n +<br />
n +<br />
D<br />
D<br />
n +<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
Fig. 2d: Schematic cross-section of the p-LDMOS<br />
device.<br />
I D (A/µm)<br />
10 -11<br />
10 -12<br />
10 -13<br />
10 -14<br />
n-LDMOS2:<br />
Maskless<br />
LDMOS<br />
implant<br />
0.6µm<br />
0.4µm<br />
1.4µm<br />
L =0.8µm<br />
DRIFT<br />
n-LDMOS1:<br />
Masked<br />
LDMOS<br />
implant<br />
1.4µm<br />
V G = 0<br />
0 10 20 30<br />
V (V) DS<br />
Fig. 3: Breakdown characteristics of transistors n-<br />
LDMOS1 and n-LDMOS2 for different drift lengths<br />
I D (A/µm)<br />
10 -11<br />
10 -12<br />
10 -13<br />
L DRIFT =0.6µm<br />
L DRIFT =0.4µm<br />
L DRIFT =0.8µm<br />
V G = 0<br />
10<br />
0 2 4 6 8 10 12<br />
-14<br />
V [V] DS<br />
Fig. 4: Breakdown characteristics of the isolated n-<br />
LDMOS3 transistor for different drift lengths.<br />
I D (µA/µm)<br />
n + p +<br />
0 - 0.75 V<br />
S G<br />
n-well<br />
p-LDD + n-LDD2<br />
n-buried layer<br />
p- substrate<br />
-50 - 1 V<br />
-100<br />
- 1.25 V<br />
- 1.5 V<br />
-150 - 1.75 V<br />
-200<br />
- 2 V<br />
- 2.25 V<br />
-250 V = - 2.5 V<br />
GS<br />
Measured<br />
Simulated<br />
-12 -10 -8 -6<br />
V (V) DS<br />
-4 -2 0<br />
Fig. 5a: Output characteristics of the p-LDMOS device.<br />
D<br />
p +
-I D (A/µm)<br />
10 -5<br />
10 -7<br />
10 -9<br />
10 -11<br />
10 -13<br />
10 -15<br />
V DS = -0.1V<br />
-10V<br />
-2 -1 0<br />
V (V) G<br />
Fig. 5b: Subthreshold characteristics of the p-LDMOS<br />
device.<br />
-I D (A/µm)<br />
10 -9<br />
10 -11<br />
10 -13<br />
10 -15<br />
V G = 0<br />
-12 -8 -4 0<br />
V [V] DS<br />
Fig. 5c: Breakdown characteristic of the p-LDMOS<br />
device.<br />
40<br />
f T , f max (GHz)<br />
30<br />
20<br />
V DS = - 8V<br />
f max<br />
Measuerd<br />
Simulated<br />
10<br />
V = - 4V fT DS<br />
0<br />
-2.5 -2.0 -1.5 -1.0 -0.5<br />
V (V) GS<br />
Fig. 6: Measured and simulated fT and fmax vs. VGS<br />
characteristics of the p-LDMOS device.<br />
Parameter Unit<br />
n-LDMOS 1<br />
n-LDMOS 1<br />
n-LDMOS 1<br />
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(dB)<br />
h , U<br />
21 0.5 0.5<br />
, G<br />
max<br />
20<br />
15<br />
10<br />
5<br />
0<br />
-5<br />
10 9<br />
10 10<br />
Reprints of<br />
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10 11<br />
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U 0.5<br />
0.5<br />
G max<br />
V DS = 8V<br />
V GS = 2.4V<br />
h 21<br />
Frequency (Hz)<br />
Fig. 7: Current gain and power gains vs. frequency of<br />
the p-LDMOS device.<br />
I D (µµA/µm)<br />
300<br />
200<br />
100<br />
Meas.<br />
Sim.<br />
V GS<br />
2.0 V<br />
1.5 V<br />
1.0 V<br />
0<br />
0 4<br />
V (V) DS<br />
8<br />
Fig. 8: Measured and simulated output characteristics of<br />
the isolated n-LDMOS3 device.<br />
100<br />
f T , f max (GHz)<br />
10<br />
f MEAS = 10GHz<br />
V DS =8V<br />
0.5 1.0 1.5<br />
V (V) GS<br />
2.0 2.5<br />
f T<br />
f max<br />
Meas.<br />
Simul.<br />
Fig. 9: Measured and simulated fT and fmax vs. VGS<br />
characteristics of the isolated n-LDMOS3 device.<br />
n-LDMOS 2<br />
n-LDMOS 3<br />
p-LDMOS<br />
Remarks<br />
This This [1] This [1] This This This<br />
work work<br />
work work work work<br />
LDrift µm 1.4 1.0 0.6 0.6 0.6 0.6<br />
BVDS V 29 26 26 16 15 16 11.5 -13.5 @ 10pA/µm<br />
ID, SAT µA/µm 150 150 125 150 125 150 150 -90 @IVGI= 1.5V,VD= 5V<br />
ILeakage pA/µm
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APPLIED PHYSICS LETTERS VOLUME 85, NU<strong>MB</strong>ER 7 16 AUGUST <strong>2004</strong><br />
Structure and thickness-dependent lattice parameters of ultrathin epitaxial<br />
Pr 2O 3 films on Si(001)<br />
T. Schroeder, T.-L. Lee, and J. Zegenhagen a)<br />
European Synchrotron Radiation Facility, 6, Rue Jules Horowitz, 38043 Grenoble, France<br />
C. Wenger, P. Zaumseil, and H.-J. Müssig<br />
<strong>IHP</strong>, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany<br />
(Received 10 March <strong>2004</strong>; accepted 19 May <strong>2004</strong>)<br />
Pr2O3 grown heteroepitaxially on Si(001) is a promising candidate for applications as a high-k<br />
dielectric in future silicon-based microelectronics devices. The technologically important thickness<br />
range from 1 to 10 nm has been investigated by synchrotron radiation-grazing incidence x-ray<br />
diffraction. The oxide film grows as cubic Pr2O3 phase with its (101) plane on the Si(001) substrate<br />
in form of two orthogonal rotation domains. Monitoring the evolution of the oxide unit-cell lattice<br />
parameters as a function of film thickness from 1 to 10 nm, the transition from almost perfect<br />
pseudomorphism to bulk values is detected. © <strong>2004</strong> American Institute of Physics.<br />
[DOI: 10.1063/1.1771465]<br />
In microelectronics, the good microprocessing capability,<br />
the high dielectric breakdown strength, and the quality of<br />
the thermally and electrically stable Si–SiO 2 interface made<br />
SiO 2 films the gate dielectric of choice over the last 40<br />
years. 1 However, for generations of ultralarge-scale integration<br />
circuits, the SiO 2 gate must be replaced by an alternative<br />
high-k dielectric and many candidates are studied. 2 Among<br />
these, thin epitaxial praseodymium sesquioxide �Pr 2O 3� films<br />
on Si(001) substrates show outstanding dielectric properties<br />
for use as gate insulators. 3,4 To optimize the performance of<br />
this materials system, we studied the structural aspects of the<br />
dielectric layer to correlate them with the electric properties<br />
of devices with a Pr 2O 3 gate. In this letter, we report a synchrotron<br />
radiation-grazing incidence x-ray diffraction (SR-<br />
GIXRD) study on the morphological properties of the heteroepitaxial<br />
system Pr 2O 3/Si�001� for oxide film thicknesses<br />
of technological importance �1 to 10 nm�.<br />
The boron-doped Si(001) substrates were cleaned by a<br />
standard procedure and an HF dip removed the native oxide<br />
layer immediately before the wafers were loaded into the<br />
ultrahigh vacuum chamber. The Pr 2O 3 layers were grown by<br />
molecular-beam epitaxy, as reported elsewhere. 5 Before exposure<br />
to air, the hygroscopic Pr 2O 3 films were protected by<br />
an amorphous Si capping layer of several nm thickness. 6 The<br />
Pr–oxide layer thickness was determined by ex situ x-ray<br />
reflectivity and quantitative fluorescence measurements of<br />
the Pr L lines. Samples of 1, 2, 4, 6, and 10 nm thick Pr 2O 3<br />
films were studied ex situ by SR-GIXRD at the insertion<br />
device beamline ID 32 of the European Synchrotron Radiation<br />
Facility using a beam energy of 11 keV �0.1127 nm�.<br />
For grazing incidence diffraction studies, a Kappa-six-circle<br />
diffractometer was used with the incident angle of the beam<br />
on the sample surface fixed to 0.3°. Substrate and oxide reflections<br />
are indexed with respect to their bulk lattices, intensities<br />
are given in counts per second.<br />
The first question to answer is the vertical stacking of<br />
the ultrathin Pr 2O 3 epilayer on the Si(001) substrate. Figure<br />
a)<br />
Author to whom correspondence should be addressed; electronic mail:<br />
zegenhagen@esrf.fr<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
1(a) shows a specular �–2� measurement on a 4 nm thick<br />
Pr2O3 film on Si(001) which provides this information by<br />
revealing all oxide and substrate reflections situated on the<br />
�00L� crystal truncation rod (CTR). Aside from the substrate<br />
peaks, the observed oxide reflection suggests that (a) the oxide<br />
consists of only one phase and (b) this phase grows with<br />
a single orientation on Si(001). Comparing the experimentally<br />
determined d spacing of this oxide reflection �d<br />
=0.198 nm� with those of the different Pr2O3 phases known<br />
from literature 7 allows us to assign this peak to the (404)<br />
reflection of the cubic Pr2O3 phase (space group: Ia3). This<br />
result is found for all ultrathin Pr2O3 films studied in this<br />
work except for the 1 nm thick Pr2O3 film. In the latter case,<br />
the limited oxide thickness did not result in any detectable<br />
oxide peak on the �00L� CTR. Our study corroborates the<br />
results of �–2� scans performed with laboratory x-ray<br />
sources on thicker Pr2O3 layers ��15 nm� on Si(001). 4,6<br />
The second question of interest is the azimuthal orientation<br />
of the oxide layer on the Si(001) surface. The answer is<br />
given by the hk in-plane scan ��=0.1� along the bulk<br />
Si �11 ¯0� direction in Fig. 1(a) recorded for a 4 nm Pr2O3 layer on Si(001). This scan is representative of all samples<br />
studied. Since the Si peaks are very sharp [full width at half<br />
maximum (FWHM) of 0.002°], the broad oxide reflections<br />
(FWHM of 3°) can be easily distinguished. Two oxide reflections<br />
are observed and can be assigned to the Pr2O3�040� and<br />
to the Pr2O3�404 ¯� in-plane reflections.<br />
This reciprocal space information gathered in Fig. 1(a)<br />
determines the real space orientation of the Pr2O3 layer on<br />
the Si(001) surface. As the Si(001) surface unit cell is rotated<br />
around the Si(001) surface normal by 45° with respect to the<br />
bulk lattice unit cell, the Si(001) surface unit-cell vectors a1 and a2 point along the �110� bulk Si direction. 8 The clean<br />
Si(001) surface is characterized by a �2�1� reconstruction<br />
and Si terraces separated by a monatomic step height separate<br />
two �2�1� domains which are rotated by 90° with respect<br />
to each other. 8 This is sketched in Fig. 1(a). It depicts<br />
the orientation of the two �2�1� Si rotation domains [terraces<br />
(1) and (2)] with respect to the bulk �11 ¯0� direction.<br />
0003-6951/<strong>2004</strong>/85(7)/1229/3/$20.00 1229<br />
© <strong>2004</strong> American Institute of Physics
Scanning tunneling microscopy studies have shown the initial<br />
Pr2O3 growth on the �2�1� reconstructed Si(001)<br />
surface. 5 The specular �–2� scan of Fig. 1 proves that the<br />
cubic Pr2O3 grows with its rectangular (101) plane on the Si<br />
surface. The highest number of coincidence lattice points<br />
between the oxide and the semiconductor results when the<br />
oxide in-plane unit-cell vectors b1=�101 ¯� and b2=�010� are<br />
aligned along the in-plane Si(001) surface unit-cell directions<br />
a1 and a2. The dimensions of the latter are given in case of<br />
r r<br />
the �2�1� reconstruction by �a1�=0.768 nm and �a2� r r<br />
=0.384 nm so that the substrate spacings 2·�a 1� and 3·�a2 �<br />
match the oxide unit-cell dimensions �b1�=1.5771 nm and<br />
�b2�=1.1152 nm within 3% respectively. The azimuthal orientation<br />
of the oxide layer unit cells on the �2�1� reconstructed<br />
terraces (1) and (2) is shown in Fig. 1(a) by the<br />
dashed rectangles denoted domains (1) and (2). Accordingly,<br />
the existence of the two orthogonal oxide domains (1) and<br />
(2) on the Si(001) surface causes in the in-plane hk scan of<br />
Fig. 1(a) along the bulk Si �11 ¯0� direction the presence<br />
of the Pr2O3�404 ¯� and Pr2O3�040� in-plane reflections,<br />
respectively.<br />
As strain relaxation and associated defects due to the<br />
lattice mismatch between oxide and Si might compromise<br />
the Pr2O3 gate performance, the change in the lattice param-<br />
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1230 Appl. Phys. Lett., Vol. 85, No. 7, 16 August <strong>2004</strong> Schroeder et al.<br />
FIG. 1. (a) Specular �–2� scan (top) and in-plane hk scan ��=0.1� along<br />
Si�11 ¯ 0� (middle) of a 4 nm Pr 2O 3 filmonSi(001). Bottom: 90° rotation<br />
domain structure of the �2�1� Si(001) surface (gray dots: Second layer Si<br />
monomers; gray dots connected by black lines: First layer Si dimers). (b) hkl<br />
mesh scans ��=0.1� around the Si�22 ¯ 0� peak of the Pr 2O 3 �404 ¯ � reflections<br />
(coordinate system: Oxide unit-cell orientation).<br />
eters of the oxide as a function of film thickness must be<br />
accurately known.<br />
The azimuthal lattice parameter �b1� along the oxide<br />
�101 ¯� direction was determined for all samples with the help<br />
of the Pr2O3�404 ¯� reflection. The Pr2O3�404 ¯� diffraction<br />
peaks were studied by hkl mesh scans ��=0.1� around the<br />
Si�22 ¯0� substrate peak shown in Fig. 1(b). The very sharp<br />
Si�22 ¯0� peak is situated in the center appearing as a single<br />
point. In contrast, the Pr2O3�404 ¯� reflection exhibits a broad<br />
shape. The oxide peak is centered around the Si�22 ¯0� substrate<br />
peak for films of 1 and 2 nm thickness but the oxide<br />
reflection moves along the hk ¯ diagonal toward smaller reciprocal<br />
space values when the film thickness is increased to 4,<br />
6, and 10 nm. The variation of �b1� was extracted and the<br />
result is plotted in Fig. 2(b). The bulk oxide unit-cell value<br />
�b1� of 1.577 nm is indicated by the dotted line and is 2.6%<br />
r<br />
bigger than the Si(001) substrate spacing of 2·�a 1� =1.536 nm (dashed–dotted line). This lattice misfit<br />
r<br />
��b1��2·�a1�� compresses the oxide film along its �101 ¯� direction.<br />
Films of 1 and 2 nm thickness exhibit pseudomorphic<br />
growth behavior but �b1� relaxes in thicker films toward<br />
the oxide bulk value reached at 10 nm film thickness. Note<br />
that the intensity of the oxide spots of the thicker films (4, 6,<br />
and 10 nm) is asymmetric toward the Si�22 ¯0� reflection indicating<br />
that the compressed �101 ¯� oxide lattice planes in the<br />
vicinity of the Si substrate are also present in thicker films<br />
pointing toward a gradual relaxation of strain.<br />
In addition, the hkl mesh scans allow one to extract the<br />
domain sizes of the oxide layer along the oxide [010] and the<br />
�101 ¯� directions by determining the FWHM values along the<br />
respective directions. 9 The result is plotted in Fig. 2(b). As<br />
the Pr2O3�404 ¯� oxide reflection exhibits for all film thicknesses<br />
an anisotropic spot shape, i.e., the spots are elongated<br />
along the oxide [010] direction, a bigger domain size is always<br />
found along the �101 ¯� direction. The better evolved<br />
long-range order of the oxide along the latter direction is due<br />
to the smaller lattice mismatch between substrate and epilayer<br />
along this azimuth, as pointed out in the following.<br />
The azimuthal lattice parameter �b2� along the oxide<br />
[010] direction was monitored by studying the Pr2O3�040� reflections. Figure 2(a) summarizes the in-plane hk scans at<br />
l=0.1 of the Pr2O3�040� diffraction peaks performed for 1, 2,<br />
4, 6, and 10 nm thick Pr2O3 layers on Si(001). A strong shift<br />
of the position of this oxide reflection along the hk ¯ diagonal<br />
toward bigger reciprocal space values is detected when the<br />
film thickness is doubled from 1 to 2 nm [bottom panel in<br />
Fig. 2(a)]. This shift continues for the 4 nm film but saturates<br />
for the 6 and 10 nm thick films [top panel in Fig. 2(a)]. The<br />
Pr2O3�040� diffraction peaks of the thicker films show a<br />
shoulder structure toward lower reciprocal values indicated<br />
by the arrow. Again, this demonstrates that strained (010)<br />
oxide planes are present in the thicker films (4, 6, and<br />
10 nm) toward the Si substrate. The main positions of the<br />
various Pr2O3�040� reflections were used to extract the value<br />
of �b2� plotted in Fig. 2(b). The bulk oxide unit-cell length<br />
�b2� of 1.115 nm along the [010] direction (dotted lines) is<br />
r<br />
smaller by 3.3% than the substrate-induced value of 3·�a 1� =1.152 nm (dashed–dotted line). This lattice misfit<br />
r<br />
��b2��3·�a1�� extends the oxide film along its [010] direc-<br />
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Appl. Phys. Lett., Vol. 85, No. 7, 16 August <strong>2004</strong> Schroeder et al. 1231<br />
FIG. 2. (a) hk in-plane scans ��=0.1� of the Pr 2O 3 �040� reflections of<br />
different oxide film thicknesses. (b) Oxide unit-cell lattice parameters (top)<br />
and domain sizes (bottom) as a function of thickness.<br />
tion. Surprisingly, instead of a pseudomorphic growth, the<br />
1 nm thick oxide film shows an unit-cell length �b 2� of<br />
1.168 nm which is bigger than the substrate-induced value of<br />
1.152 nm. A possible explanation could be the formation of a<br />
silicate at the oxide/Si interface. Photoemission studies suggest<br />
the growth of such a �Pr 2O 3� y�SiO 2� x interface layer of<br />
about 2 nm thickness. 10 As such an interface reaction at the<br />
oxide/Si affects the structure factors of the Pr 2O 3 layer, further<br />
support for the presence of an interfacial phase is given<br />
by an analysis of the Pr 2O 3�040� diffraction intensities.<br />
Figure 2 shows that the intensity of the Pr 2O 3�040� diffrac-<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
tion peaks reasonably scales with the oxide thickness for 4,<br />
6, and 10 nm thick layers, but a strong decrease in intensity<br />
is occurring for the 1 and 2 nm thick Pr 2O 3 layer. In contrast<br />
to the 1 nm film, the position of the Pr 2O 3�040� reflection of<br />
the 2 nm thick oxide points to a more bulklike lattice constant.<br />
Figure 2(b) shows that the value �b 2�=1.129 nm is already<br />
close to the bulk Pr–oxide unit-cell length of<br />
1.115 nm. The bulk value of �b 2� is adopted for all oxide<br />
films from 4 nm thickness.<br />
Figure 2(b) shows the vertical unit-cell length �b 3� along<br />
the oxide [010] direction for the various film thicknesses<br />
studied. These values were deduced from Pr 2O 3�404� reflections<br />
in specular �–2� scans which were detectable for all<br />
films thicker than 1 nm. The 2 and 4 nm thick films show a<br />
�b 3� value of 0.84 nm which reduces to 0.816 and 0.81 nm<br />
for the 6 and 10 nm thick oxide layer, respectively. All these<br />
(101) layer spacings are bigger than the oxide bulk value of<br />
0.788 nm (dotted line). The presence of a �Pr 2O 3� y�SiO 2� x<br />
phase may explain these results. X-ray diffraction (XRD)<br />
studies on unprotected Pr 2O 3 layers ��15 nm� show after<br />
exposure to air in the specular �–2� scans a peak at slightly<br />
smaller angles than the Pr 2O 3�404� reflection, indicating an<br />
increase of the Pr 2O 3�101� lattice spacing to a value of<br />
0.832 nm. 6 Transmission electron microscopy (TEM) studies<br />
suggest as a possible origin of this peak an enhanced silicate<br />
formation due to oxygen diffusion to the Si substrate. 6 As the<br />
(101) layer spacing of 0.84 nm derived in this work is close<br />
to this reported value, further evidence is given for the strong<br />
influence of an interfacial silicate layer on the properties of<br />
Pr 2O 3 films thinner than 4 nm. It is noted that the increased<br />
value of �b 3� (with respect to the bulk) in case of the 6 and<br />
10 nm thick film is due to the fact that specular �–2� scans<br />
probe the whole oxide layer thickness.<br />
In conclusion, we determined the structure and orientation<br />
of the Pr 2O 3 epilayer on the Si(001) surface and monitored<br />
quantitatively the thickness dependence of the film lattice<br />
parameters over the technologically important thickness<br />
range �1 to 10 nm�. The interface structure between oxide<br />
and Si(001) substrate deviates from the oxide bulk structure,<br />
possibly due to silicate formation. As the oxide/Si interface<br />
is of utmost importance for the performance of microelectronics<br />
devices, further studies are underway to disclose its<br />
detailed structure.<br />
1<br />
T. Hori, Gate Dielectrics and MOS ULSIs, Springer Series in Electronics<br />
and Physics Vol. 34 (Springer, Berlin, 1996).<br />
2<br />
G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys. 89, 5243<br />
(2001).<br />
3<br />
H.-J. Müssig, H. J. Osten, E. Bugiel, J. Dabrowski, A. Fissel, and T.<br />
Gumminskaja, IEEE International Integrated Reliability Workshop, Final<br />
<strong>Report</strong> (IEEE, New York, 2001), p.1.<br />
4<br />
H. J. Osten, E. Bugiel, and A. Fissel, Solid-State Electron. 47, 2161<br />
(2003).<br />
5<br />
H.-J. Müssig, J. Dabrowski, K. Ignatovich, J. P. Liu, V. Zavodinsky, and<br />
H.-J. Osten, Surf. Sci. 504, 159(2002).<br />
6<br />
P. Zaumseil, E. Bugiel, J. P. Liu, and H.-J. Osten, Solid State Phenom.<br />
82–84, 789(2002).<br />
7<br />
A. F. Wells, Structural Inorganic Chemistry (Clarendon, Oxford, 1975).<br />
8<br />
J. Dabrowski and H.-J. Müssig, Silicon Surfaces and Formation of Interfaces<br />
(World Scientific, Singapore, 2000).<br />
9<br />
M. Henzler, Prog. Surf. Sci. 42, 297 (1993).<br />
10<br />
A. Fissel, J. Dabrowski, and H. J. Osten, J. Appl. Phys. 91, 8986 (2002).
Silicate layer formation at Pr 2O 3/Si„001… interfaces<br />
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D. Schmeißer<br />
Angewandte Physik-Sensorik, BTU Cottbus, Postfach 10 13 44, D-03013 Cottbus, Germany<br />
H.-J. Müssig a) and J. Dąbrowski<br />
<strong>IHP</strong>, Im Technologiepark 25, D-15236 Frankfurt (Oder), Germany<br />
(Received 30 January <strong>2004</strong>; accepted 17 May <strong>2004</strong>)<br />
We studied Pr2O3/Si�001� interfaces by synchrotron radiation photoelectron spectroscopy and by ab<br />
initio calculations. We show that the interface formed during molecular-beam epitaxy under the<br />
oxygen partial pressure above 1�10−8 mbar consists of a mixed Si–Pr oxide, such as<br />
�Pr2O3��SiO�x�SiO2�y. Neither an interfacial SiO2 nor an interfacial silicide is formed. The silicate<br />
formation is driven by a low energy of O in a PrOSi bond and by the strain in the subsurface SiOx layer. We expect that this natural interfacial Pr silicate will facilitate the integration of the high-k<br />
dielectric Pr2O3 into future complementary metal–oxide–semiconductor technologies. © <strong>2004</strong><br />
American Institute of Physics. [DOI: 10.1063/1.1769582]<br />
Reprints of<br />
Selected Publications<br />
APPLIED PHYSICS LETTERS VOLUME 85, NU<strong>MB</strong>ER 1 5 JULY <strong>2004</strong><br />
The main problem arising from the scaling of metal–<br />
oxide–semiconductor (MOS) field effect transistors concerns<br />
a large increase of the leakage current flowing through the<br />
device as the SiO 2 gate layer thickness decreases. Therefore,<br />
SiO 2 will fail to meet the industrial demands on the leakage<br />
current and long-time reliability, so that another material will<br />
have to be introduced. Its electrical properties will be similar<br />
to those of SiO 2 but its dielectric constant k will be up to 10<br />
times higher. 1<br />
For ultrathin gate dielectrics, the interface to the Si substrate<br />
is a major factor determining the electrical properties<br />
of the MOS structure. In order to maintain a high-quality<br />
interface, a high channel mobility, and good current–voltage<br />
characteristics, it is important to have a low defect density<br />
and no silicide phase at or near the channel interface.<br />
Pr 2O 3, grown epitaxially on Si�001� may possibly replace<br />
SiO 2 as gate dielectric in sub-0.1 �m complementary<br />
MOS technology. 2 Here, we analyze the interfacial stoichiometry<br />
of the Pr 2O 3/Si�001� system using synchrotron radiation<br />
photoelectron spectroscopy (SR-PES) and ab initio calculations.<br />
We arrive at a ternary phase diagram for the<br />
interface composition. The ab initio results allow us to pinpoint<br />
some energy factors in the thermodynamics of silicate<br />
and silicide formation and to gain insight into atomic-scale<br />
aspects of the interface.<br />
The calculations were done within the density-functional<br />
theory framework, 3 using fhimd. 4 We treated trivalent Pr�III�<br />
with two f electrons in the core and tetravalent Pr�IV� with<br />
one f electron in the core as species with distinct pseudopotentials<br />
and we calibrated the pseudopotential energy difference<br />
between Pr�III� and Pr�IV� atoms by adding a constant<br />
offset so that the experimental difference in formation enthalpies<br />
of bulk Pr 2O 3 and PrO 2 (Ref. 5) is reproduced. The<br />
supercells for interface calculations consisted of six Si layers<br />
covered by up to four Pr oxide layers and passivated by H<br />
atoms on the other side. Calculations for bulk Pr 2O 3, PrO 2,<br />
Pr 2Si 2O 7, and amorphous SiO 2 were performed with supercells<br />
of approximately 1�1�1 nm 3 .<br />
In the experiment, Si�001� 2�1 surfaces were obtained<br />
by a suitable cleaning procedure. 6 Films with thickness from<br />
a) Electronic mail: muessig@ihp-microelectronics.com<br />
about 1 nm to 3 nm were prepared in situ by electron-beam<br />
evaporation of reduced Pr 6O 11 from a Mo crucible. As a rule,<br />
the sample was kept at 600 °C, the deposition rate was<br />
0.1 nm/min, and the O 2 partial pressure was in the range of<br />
10 −8 mbar. For comparison, some depositions were done on<br />
preoxidized (native oxide) Si�001� at room temperature (RT).<br />
The composition of these films was analyzed by SR-PES and<br />
the information on the depth profile was obtained by varying<br />
the photoelectron energy; details of the spectrometer and of<br />
the beam line are given elsewhere. 7<br />
Si2p electrons from Si bulk atoms give rise to a characteristic<br />
doublet at the binding energy of 99.3 eV. After Pr 2O 3<br />
deposition, the doublet is still visible (Fig. 1), but it is shifted<br />
by about 2 eV. This shift does not depend on the film thickness,<br />
indicating that it is chemical in its nature. 8 Moreover,<br />
the shift is clearly different from that known for Si in SiO 2<br />
�4 eV� and closely resembles the value typical to Pr silicates<br />
�2 eV�. 9 The shift of 4 eV is detectable only when the film is<br />
grown on SiO 2.<br />
The oxidation of a Si atom leads to its positive charging<br />
and, consequently, to the increase of the Si2p binding energy<br />
with respect to electrically neutral Si atoms in the Si crystal.<br />
Si atoms in SiO 2 have four O neighbors resulting in a Si2p<br />
shift of 4 eV. In a Pr silicate, the four O neighbors of Si have<br />
FIG. 1. Si 2p data for an epitaxial Pr 2O 3 film on Si�001� with the thickness<br />
of about 1.5 nm.<br />
0003-6951/<strong>2004</strong>/85(1)/88/3/$22.00 88<br />
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FIG. 2. Emission around the O 1s core level for various Pr 2O 3 films: (a)<br />
Thick Pr 2O 3 oxide on SiO 2, 600 °C deposition; �b 1� and �b 2� epitaxial films<br />
of different thickness, 600 °C deposition; and (c) SiO 2 alloying with Pr 2O 3,<br />
RT deposition.<br />
Pr neighbors. Since Pr is more electropositive than Si, electron<br />
transfer from Pr in Si–O–Pr competes with the electron<br />
transfer from Si, reducing the positive charge of Si and the<br />
Si2p binding energy is decreased.<br />
Associating the 101 eV line with a silicate is consistent<br />
with our observation that after Pr 2O 3 is deposited at RT on a<br />
preoxidized sample, a similar line develops overnight. The<br />
latter finding means that native SiO 2 is thermodynamically<br />
unstable in contact with Pr 2O 3. Indeed, we do not observe<br />
SiO 2 after Pr 2O 3 deposition on bare substrates. This is a good<br />
news, since a SiO 2 interfacial layer would reduce the effective<br />
dielectric constant of the stack more dramatically than a<br />
silicate layer does.<br />
These conclusions are further supported by comparison<br />
of the O1s emission from bulklike Pr 2O 3 deposited on oxidized<br />
Si�001� at 600 °C, with the emission typical for the<br />
epitaxial Pr 2O 3/Si�001� system (Fig. 2). Because the negative<br />
charge on O increases from SiO 2 through silicates to<br />
Pr 2O 3, one observes a corresponding decrease of the O 1s<br />
binding energy. RT deposition leads to alloying between<br />
Pr 2O 3 and SiO 2:NoPr 2O 3 signal is seen.<br />
Finally, we note that while the energy of the silicate Si2p<br />
emission remains constant, its intensity depends on the deposition<br />
parameters, the film thickness, and the photon energy.<br />
From these dependencies, we derive the distribution of Si<br />
concentration in the film, and the ternary diagram of the<br />
Si–Pr–O system (Fig. 3). The intensity ratio between the<br />
FIG. 3. The ternary phase diagram of the SiuOuPr system.<br />
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Si2p emission of the substrate and of the silicate allows one<br />
to calculate the silicate film thickness; the ratio between the<br />
Si2p and Pr4d emission (not shown) provides information on<br />
the silicate composition. The mole fractions of Pr, Si, and O<br />
calculated in this way are plotted in the phase diagram in<br />
Fig. 3. All data are located within a narrow triangle bordered<br />
by two quasibinary cuts: Between SiO 2 and Pr 2O 3, and between<br />
SiO and Pr 2O 3. The Pr/Si ratio of unity �Pr 2Si 2O 7� is<br />
observed at the film thickness of about 1 nm and corresponds<br />
to a stable bulk Pr silicate. 10 The existence of two quasibinary<br />
cuts indicates that the oxygen content in the film depends<br />
on the preparation conditions.<br />
We did not observe formation of PruSi bonds. If such<br />
bonds existed in concentrations above the detection limit, the<br />
phase diagram would contain points starting from SiO 2 toward<br />
the Si/Pr=1 intersection at zero oxygen content. Silicide<br />
formation occurs only in the course of vacuum annealing<br />
at elevated temperatures. 11<br />
A theoretical hint confirming the stability of the film<br />
with respect to silicide formation comes from a comparison<br />
of formation energies of various interfacial structures at different<br />
chemical potentials of oxygen, �. Wedefine�=0 for<br />
oxygen in amorphous SiO 2 in thermal equilibrium with bulk<br />
Si, that is, 0.5 � O2=5.2 eV below the computed energy of O<br />
in O 2 (the experimental 0.5 � O2 is 4.7 eV). We make a simplifying<br />
assumption of a chemically sharp Pr 2O 3/Si�001� interface.<br />
A stoichiometric interface corresponds to 50% of the<br />
interfacial bonds being PrSi (silicide type) and 50% being<br />
PrOSi (silicate type). First O atoms are removed from the<br />
film when � drops below � PrOPr=−1.6 eV, and are inserted<br />
into interfacial PrSi bonds when � rises above � PrOSi<br />
=−0.6 eV. In the oxygen-rich regime above, � SiOx �1.0 eV,<br />
SiuSi bonds of the substrate are oxidized and strained SiO x<br />
is formed. The charge state of all Pr atoms remains +3.<br />
Since the energy of O is lower between Pr and Si atoms<br />
than between Si atoms (by 0.6 eV), a silicide can be formed<br />
only when not enough O is available. Otherwise, O is extracted<br />
from SiuOuSi bonds and inserted between Si and<br />
Pr, reducing the Si (sub)oxide and oxidizing the silicide.<br />
Pr silicate begins to form when first SiO 2 molecules dissolve<br />
in the Pr 2O 3 film. This corresponds to substitution of<br />
two O −2 atoms by �SiO 4� −4 . In other words, two O atoms are<br />
removed from the Pr 2O 3 film to the reservoir of O with energy<br />
�, a Si atom is added from Si bulk, and four O atoms<br />
are taken from the reservoir and placed between Pr and Si. If<br />
Si is in equilibrium with bulk Si, Pr is in equilibrium with<br />
Pr 2O 3, and O is in equilibrium with the reservoir, we can<br />
now estimate the silicate formation energy E f from:<br />
Ef = �2�PrOPr −2�� + �4� −4�PrOSi��2�� − 0.4� eV,<br />
�1�<br />
where the energy of O is approximated by � PrOPr. A positive<br />
E f means that the silicate is stable. The conclusion is that<br />
already at � o�0.4 eV a process collecting two O atoms on a<br />
Si atom and dissolving the resulting SiO 2 moiety in the<br />
Pr 2O 3 film becomes energetically favorable, due to the low<br />
energy of oxygen between Pr and O atoms �� PrOSi�. Since<br />
� o�� SiOx , the dissolution of oxidized Si in the epitaxial<br />
Pr 2O 3 is promoted by the elastic stress in the native oxide.<br />
On the other hand, calculations for bulk Pr 2Si 2O 7,Pr 2O 3, and<br />
amorphous SiO 2 show that the mixing of the bulk materials
is favorable by about 1 eV per Si atom. This means that the<br />
interfacial PruOuSi bonds are strained.<br />
We now consider the structures associated with epitaxial<br />
silicate. We computed total energies for numerous models of<br />
interfacial silicates with various stoichiometries, atomic arrangements,<br />
and lateral periodicities (from 3�1 to 3�3,<br />
measured in Si�001� surface lattice periodicity). Some of<br />
these structures are remarkably stable, becoming the favorable<br />
phase at ��0.5 eV, i. e., before Si is oxidized to SiOx. This value is close to �o, indicating that the PruOuSi<br />
bonds in these structures are as strained as at the interface.<br />
The estimate of Eq. (1) is further confirmed by a direct<br />
calculation for a single SiO2 molecule dissolved in a three<br />
monolayer thick Pr2O3/Si�001� film. The silicate formation<br />
begins at �1=1.05 eV when film surface is allowed to buckle<br />
due to the additional volume introduced by the SiO2 molecule,<br />
and at �2=0.55 eV when the surface is smoothed by<br />
depositing half a monolayer of Pr2O3 (Fig. 4). The corresponding<br />
energy difference �Ef =2��1−� 2�=1.0 eV turns<br />
out to be equal to �E0.5=E 3.5−E 4=E 3.5−E 3, where En is the<br />
energy of the film with n atomic layers of Pr2O3. A high Si concentration in the silicate is stabilized if the<br />
Si atoms are intercalated between Pr2O3 planes, forming a<br />
stacked structure. An example corresponding to the Si/Pr<br />
ratio of 3, is shown in Fig. 5. Above �3�0.8, this structure<br />
has a lower energy than Pr2O3/Si�001�, and above �4�1.0 it<br />
becomes the lowest-energy interfacial silicate among the<br />
structures considered by us. Note that not all SiuSi bonds<br />
in this silicate are oxidized; a complete oxidation is difficult<br />
without simultaneous excessive oxidation of the substrate.<br />
Since �3 is relatively high and numerous PruOuSi bonds<br />
in the film are strained, we expect that these SiuSi bonds<br />
are weak spots: When some of them are broken, the film may<br />
lower its energy by relaxation of the accumulated strain.<br />
We conclude with the following summary:<br />
(1) Oxidation of the substrate during Pr2O3 deposition from<br />
aPr6O11 source produces a stable silicate buffer layer.<br />
(2) A substantial Pr content in the buffer makes the capaci-<br />
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FIG. 4. A SiO 2 moiety dissolved in ultrathin Pr 2O 3 film (a) causes the<br />
surface to buckle. (b) Filling the trenches with 0.5 monolayer Pr 2O 3 flattens<br />
the surface and reduces the energy. Si is shown white, O is light gray, Pr is<br />
dark gray.<br />
FIG. 5. A hypothetical intercalated silicate at the interface between Pr 2O 3<br />
and Si�001�. Si is white, O is light gray, Pr is dark gray. Note the presence<br />
of SiuSi bonds in the film.<br />
tance loss due to the presence of the buffer less severe.<br />
(3) A substantial SiO 2 content in the buffer should facilitate<br />
structural accommodation of the film to the substrate.<br />
(4) SiuSi bonds in the buffer may lead to strain-induced<br />
dangling bond formation and charge trapping.<br />
This work was financially supported by the Deutsche<br />
Forschungsgemeinschaft. Calculations were performed on<br />
Cray-T3E supercomputer cluster in von Neumann Institute<br />
for Computing, Jülich, Germany (Project No. HFO06).<br />
1<br />
G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys. 89, 5243<br />
(2001).<br />
2<br />
H.-J. Müssig, H. J. Osten, E. Bugiel, J. Dąbrowski, A. Fissel, T. Guminskaya,<br />
K. Ignatovich, J. P. Liu, P. Zaumseil, and V. Zavodinsky, 2001<br />
IEEE International Integrated Reliability Workshop—Final <strong>Report</strong> (IEEE,<br />
New York, 2001), p.1.<br />
3<br />
A. Fissel, J. Dąbrowski, and H. J. Osten, J. Appl. Phys. 91, 8968(2002).<br />
4<br />
M. Bockstedte, A. Kley, J. Neugebauer, and M. Scheffler, Comput. Phys.<br />
Commun. 107, 187(1997).<br />
5<br />
H. Bergman, Gmelin Handbuch der Anorganischen Chemie, Seltenerdelemente,<br />
Teil C1 (Springer, Berlin, 1974).<br />
6<br />
B. S. Swartzentruber, Y.-W. Mo, M. B. Webb, and M. G. Lagally, J. Vac.<br />
Sci. Technol. A A7, 2901(1989).<br />
7<br />
D. R. Batchelor, R. Follath, and D. Schmeißer, Nucl. Instrum. Methods<br />
Phys. Res. A 467, 470 (2001).<br />
8<br />
C. D. Wagner, W. M. Riggs, L. E. Davis, and J. F. Moulder, Handbook of<br />
X-ray Photoelectron Spectroscopy (Perkin–Elmer, Eden Prairie, MN,<br />
1978).<br />
9<br />
J. X. Wu, Z. M. Wang, M. S. Ma, and S. Li, J. Phys.: Condens. Matter 15,<br />
5857 (2003).<br />
10<br />
J. Felsche, Z. Kristallogr. 133, 304 (1971).<br />
11<br />
H.-J. Müssig, J. Dąbrowski, K. Ignatovich, J. P. Liu, V. Zavodinsky, and<br />
H. J. Osten, Surf. Sci. 504, 159(2002).<br />
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Silicon-based light emission after ion implantation<br />
M. Kittler a,c, *, T. Arguirov b,c , A. Fischer a , W. Seifert a,c<br />
a <strong>IHP</strong> microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany<br />
b BTU Cottbus, Lehrstuhl Experimentalphysik II, Materialwissenschaften, Universitätsplatz 3-4, 03044 Cottbus, Germany<br />
c <strong>IHP</strong>/BTU Joint Lab, Universitätsplatz 3-4, 03044 Cottbus, Germany<br />
Reprints of<br />
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Electroluminescence of boron and phosphorus implanted samples has been studied for various implantation and annealing conditions.<br />
Phosphorus implantation is found to have a similar effect on light emission as boron implantation. The band-to-band luminescence<br />
of phosphorus implanted diodes is observed to increase by more than one order of magnitude upon rising the sample<br />
temperature from 80K to 300K and a maximum internal quantum efficiency of 2% has been reached at 300K. The remarkably high<br />
band-to-band luminescence is attributed to a high bulk Shockley–Read–Hall lifetime, likely promoted by the gettering action of the<br />
implanted phosphorus. The anomalous temperature behavior of the efficiency can be explained by a temperature dependence of the<br />
lifetime characteristic of shallow traps.<br />
Ó <strong>2004</strong> Published by Elsevier B.V.<br />
1. Introduction<br />
There is substantial need for efficient light emitters<br />
that are compatible with standard silicon-based integrated<br />
circuit technology for development of on-chip<br />
optical interconnection. Ng et al. [1] demonstrated that<br />
light-emitting diodes (LED) operating efficiently at<br />
room temperature can be formed by implantation of<br />
boron into silicon.<br />
Recently, we found that such light emission can also<br />
be produced after phosphorus implantation into p-type<br />
Si [2]. Fig. 1 shows electroluminescence (EL) data measured<br />
on a n + –p diode under forward bias. Detailed<br />
investigations by photoluminescence (PL) revealed that<br />
the luminescence spectrum of implanted Si samples consists<br />
of the band-to-band line (BB) and the defect-band<br />
lines (D1–D4), see e.g. [2]. The intensity of the BB line<br />
was observed to become stronger with increasing temperature<br />
whereas the intensity of the D-lines decreased.<br />
0925-3467/$ - see front matter Ó <strong>2004</strong> Published by Elsevier B.V.<br />
doi:10.1016/j.optmat.<strong>2004</strong>.08.045<br />
Optical Materials xxx (<strong>2004</strong>) xxx–xxx<br />
*<br />
Corresponding author. Tel.: +49 335 5625 130; fax: +49 335 5625<br />
333.<br />
E-mail address: kittler@ihp-microelectronics.com (M. Kittler).<br />
www.elsevier.com/locate/optmat<br />
At room temperature, the BB line is found to dominate,<br />
with no D lines detectable. The achievement of the<br />
strong room temperature luminescence (and of the<br />
anomalous temperature behavior of the luminescence)<br />
has been attributed in Ref. [1] to the formation of<br />
implantation related dislocation loops and the introduction<br />
of a local strain field that modifies the Si band structure<br />
and provides spatial confinement of charge carriers,<br />
thus preventing non-radiative recombination. This<br />
explanation is not convincing to us. Indeed, it is known<br />
that the local strain field at dislocations causes a modification<br />
of the band structure, namely the formation of<br />
shallow one-dimensional bands about 80meV from the<br />
valence and the conduction bands, respectively (see<br />
Ref. [3] and references therein). However, the onedimensional<br />
dislocation-related bands do not form the<br />
band-to-band line. It is well accepted that they are the<br />
cause for the D4 line which is shown in the low-temperature<br />
EL spectrum given in the insert of Fig. 1. Accordingly,<br />
dislocations should not be the (direct) cause for<br />
the strong luminescence in ion implanted Si. The goal<br />
of this work is to improve the understanding of the origin<br />
of the implantation induced BB light emission, in or-<br />
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Internal efficciency, %<br />
0.8<br />
0.7<br />
0.6<br />
0.5<br />
0.4<br />
0.3<br />
0.2<br />
Electroluminescence<br />
0.1<br />
Phosphorous implant<br />
0.0<br />
50 100 150 200 250 300<br />
Temperature, K<br />
der to provide ways for a further increase of room temperature<br />
luminescence.<br />
2. Experimental<br />
D4<br />
BB<br />
300K<br />
80K<br />
0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25<br />
Photon energy, eV<br />
Fig. 1. Temperature dependence of the integrated intensity of the<br />
band-to-band electroluminescence of a n + –p diode. The inset shows<br />
the EL spectra at 300K and 80K, respectively.<br />
Si epilayers of a few micrometer thickness were<br />
grown by chemical vapor deposition on (100) oriented<br />
8 in. Czochralski-grown silicon wafers. The resistivity<br />
of the substrates and of the epilayers was about<br />
10Xcm and the conductivity was either n- or p-types.<br />
Implantation was performed through a 15nm scattering<br />
oxide. Boron was implanted into the n-type material at<br />
energies ranging from 50 to 250 keV and doses from<br />
2 · 10 12 to 2 · 10 14 cm 2 , while phosphorus was implanted<br />
into the p-type material at energies between<br />
135 and 500keV and doses in the range from 4 · 10 12<br />
to 4 · 10 14 cm 2 . After implantation, the samples were<br />
heat treated in a furnace at 1000°C for 20min in nitrogen<br />
atmosphere or by rapid thermal annealing (RTA) at<br />
1040°C for 10s in nitrogen atmosphere, respectively. Finally,<br />
the wafers received a 400°C/30min anneal in<br />
hydrogen atmosphere. This way p–n junctions were<br />
formed in the wafers. After the annealing step crystal defects<br />
were observed in the samples, predominantly at the<br />
depth of the maximum dopant concentration. The defect<br />
density was higher for larger implantation doses. Examples<br />
of an analysis by transmission electron microscopy<br />
(TEM) can be found in Ref. [4].<br />
Luminescence was measured in the temperature<br />
range between 80 and 300 (330) K. For PL, an argon laser<br />
(514nm) was used for excitation. The ohmic contacts<br />
needed for EL investigations were prepared by evaporating<br />
Al on the front side of the samples and rubbing<br />
a Ga/In eutectic on the rear side. A 1-mm 2 opening in<br />
the aluminium layer was left as a window for the lumi-<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
nescence measurement. Forward biases up to 1.5V were<br />
applied to the LED structures to inject excess charge<br />
carriers. The current densities were in the range of one<br />
to a few tenths of A/cm 2 . All measurements were done<br />
at a modulation frequency of 30Hz.<br />
Absolute light power measurements were realized by<br />
comparing the diode spectrum with the spectrum of a<br />
commercially available infrared emitter with<br />
k = 950nm and known emitter characteristics. For correct<br />
absolute luminescence measurements, the ratio of<br />
the systemÕs spectral responsivity at 950nm and<br />
1127nm (BB line) was taken into account. The spectral<br />
responsivity was determined by measurements on a<br />
black body emitter at 3000K. The power of the BB line<br />
emission was obtained by integrating over the whole<br />
band edge luminescence peak in the spectrum. The internal<br />
quantum efficiency was calculated from the measured<br />
external efficiency by ginternal = gexternal/0.013,<br />
which takes into account the refractivity of Si.<br />
3. Results<br />
PL measurements revealed the existence of the bandto-band<br />
line and also D band luminescence originated<br />
by crystal defects/dislocations. The peak energy of the<br />
BB line (wavelength around 1.1lm) shifts to smaller<br />
energies with increasing temperature. The temperature<br />
behavior of the peak position follows the behavior of<br />
the band gap. The difference between the energy of the<br />
band-to-band line and the band gap corresponds to<br />
the energy of the transverse optical (TO) phonon.<br />
Accordingly, the band-to-band line can be described as<br />
a one-phonon line. On the low-energy shoulder also<br />
the two-phonon line becomes visible. Its intensity is<br />
about one order of magnitude smaller than that of the<br />
one-phonon line. Further details about PL observations<br />
are given in Ref. [2].<br />
Fig. 2 shows the internal quantum efficiency of EL<br />
under identical conditions (I F<br />
0.8Acm 2 ) at room<br />
temperature for different boron implanted p + –n LED.<br />
A clear influence of the implantation conditions and<br />
the annealing can be seen. Furnace anneal causes always<br />
a higher efficiency than RTA for identical implantation<br />
conditions. The highest efficiency in our boron implanted<br />
samples—close to 1%—appears for 50 keV, i.e.<br />
for the smallest implantation energy, and at the highest<br />
implantation dose of 2 · 10 14 cm 2 . This trend, i.e. increase<br />
of efficiency with decreasing energy and increasing<br />
dose, is in agreement with data reported in Ref. [1]<br />
where an efficiency of about 1.6% was measured at room<br />
temperature for boron implantation at 30keV and<br />
1 · 10 15 cm 2 .<br />
Fig. 3 shows the maximum internal quantum efficiencies<br />
of EL at room temperature that were obtained for<br />
different phosphorus implanted n + –p LED. Again fur-
η internal<br />
2%<br />
1%<br />
0%<br />
nace anneal is found to yield a higher efficiency than<br />
RTA. Also, reduction of implantation energy and increase<br />
of implantation dose result in an increase of efficiency.<br />
An efficiency higher than 1.5% was measured for<br />
135keV and 4 · 10 13 cm 2 . By optimizing the P implantation<br />
(lower energy and higher dose) we believe to be<br />
able to increase the light emission efficiency at 300 K<br />
to 5%. The best value we could reach until now at room<br />
temperature for phosphorous implanted diodes is about<br />
2%.<br />
4. Discussion<br />
4.1. Model<br />
B, 240 keV<br />
RTA Furnace RTA<br />
internal<br />
η<br />
1%<br />
0%<br />
B, 50 keV<br />
Furnace<br />
P, 500 keV<br />
2%<br />
4x10 14 cm -2<br />
P, 135 keV<br />
4x10 13 cm -2<br />
B, 30 keV<br />
Furnace<br />
Furnace<br />
RTA<br />
1x10 15 cm -2<br />
2x10 14 cm -2<br />
2x10 12 cm -2<br />
Fig. 2. Internal quantum efficiency (T = 300K) of the band-to-band<br />
EL of boron implanted p + –n diodes for different implantation and<br />
annealing conditions. The efficiency is larger for small implantation<br />
energies and increases with the implantation dose. For comparison,<br />
experimental data reported by Ng et al. [1] is given, too.<br />
Fig. 3. Internal quantum efficiency of the band-to-band EL of<br />
phosphorus implanted n + –p diodes at T = 300K, for different implantation<br />
and annealing conditions. Furnace anneal and low implantation<br />
energy yield the best results.<br />
Recombination in Si consists of three components,<br />
each associated with a distinct mechanism, namely multiphonon<br />
or Shockley–Read–Hall (SRH) recombination<br />
via deep levels in the band-gap, Auger recombination<br />
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M. Kittler et al. / Optical Materials xxx (<strong>2004</strong>) xxx–xxx 3<br />
with the energy given to a third carrier and the radiative<br />
band-to-band recombination [5]. The recombination<br />
rates R of these mechanisms depend on the excess carrier<br />
concentration Dn in the following manner<br />
for the SRH recombination rate<br />
RSRH ¼ Dn 1=sSRH; ð1Þ<br />
for the radiative recombination rate<br />
RBB Dn 2 B; ð2Þ<br />
and for the Auger recombination rate<br />
RAuger Dn 3 C: ð3Þ<br />
The inverse of the SRH lifetime,s SRH, is the rate<br />
determining coefficient in (1). Note that 1/s SRH is proportional<br />
to the concentration Nimp of deep levels/impurities.<br />
B denotes the radiative recombination coefficient<br />
in (2) and C is the Auger recombination coefficient in<br />
(3).The radiative recombination coefficient B (for the<br />
band-to-band recombination) was experimentally determined<br />
in perfect Si to be 10 14 cm 3 s 1 at 300K [6].For<br />
Auger recombination, the coefficients for electrons and<br />
holes differ slightly. In the estimate shown below, we<br />
have used a mean value of C 10 31 cm 6 s 1 at 300K<br />
[7].<br />
The internal quantum efficiency is defined by the ratio<br />
of the radiative recombination rate RBB and the overall<br />
recombination rate, i.e.<br />
g i ¼ RBB=ðRSRH þ RBB þ RAugerÞ: ð4Þ<br />
Fig. 4 depicts the calculated internal quantum efficiency<br />
gi as a function of the excess charge carrier<br />
density Dn according to (4). The calculation was done<br />
η internal<br />
0.1<br />
0.01<br />
τSRH<br />
1 ms<br />
30 µs<br />
P: 135 keV<br />
RTA<br />
target 5%<br />
1E-3<br />
1E16 1E17 1E18<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 121<br />
F<br />
F<br />
P: 500 keV<br />
100 µs<br />
F<br />
∆n (cm -3 )<br />
10 µs<br />
B: 30 keV, W.L. Ng et al.<br />
Fig. 4. Internal quantum efficiency gi vs excess carrier concentration<br />
Dn, calculated using relation (4) with SRH lifetime sSRH as parameter.<br />
Experimental data points for n + –p diodes implanted with phosphorus<br />
at energies of 135keV and 500keV, respectively, are indicated, together<br />
with data from Ng et al. [1]. Solid symbols refer to furnace annealing,<br />
open symbols to RTA. The position of the experimental data in the gi<br />
vs Dn plot allows to judge about the SRH lifetime. An efficiency target<br />
of 5% is believed to be reachable for phosphorus implantation.
Nachdrucke<br />
ausgewählter Publikationen<br />
122<br />
Reprints of<br />
Selected Publications<br />
4 M. Kittler et al. / Optical Materials xxx (<strong>2004</strong>) xxx–xxx<br />
for 300K by using the above given values for the coefficients<br />
B and C, with the SRH lifetime sSRH as<br />
parameter.<br />
4.2. Efficiency of light emission<br />
The efficiency for light emission is largely governed<br />
by the SRH lifetime, i.e. the quality of the Si material.<br />
In nearly perfect Si material with s SRH =10 3 s, the<br />
maximum of the quantum efficiency gi is expected to<br />
reach about 30%. This value is in agreement with Trupke<br />
et al. [8] who concluded from their experimental<br />
data that the internal quantum efficiency of Si at room<br />
temperature may exceed 20%.<br />
The second factor of importance for radiative recombination<br />
is the excess carrier density Dn. High Dn values<br />
can be reached in the case of EL, sufficiently large forward<br />
bias exceeding the diffusion voltage of the p–n<br />
junction (UF > Ud) provided. Under such bias conditions,<br />
the densities of both majority and minority carriers<br />
in the base region of the diode close to the junction<br />
become larger than the equilibrium density of the majority<br />
carriers, see e.g. Spenke [9]. According to diode simulations,<br />
excess electron and hole densities (Dn, Dp,<br />
Dn Dp) exceeding the doping level in the diode base<br />
by a factor of 100 can be reached in our n + –p diode at<br />
UF > Ud. The same is true for p + –n diodes produced<br />
by B implantation.<br />
<strong>4.3</strong>. Influence of implantation and annealing<br />
Results of a calculation for n + –p diodes obtained<br />
with the process and device simulator ‘‘ISE TCAD’’<br />
Excess Carrier Density ∆n (cm –3)<br />
10 17<br />
2 x 10 16<br />
10 13<br />
P Implant: 135 keV<br />
U F = 1.2 V<br />
T = 300 K<br />
Furnace<br />
10 14<br />
-2<br />
Implantation Dose (cm )<br />
RTA<br />
500 keV<br />
5 x 10 14<br />
Fig. 5. Excess carrier density in the base of our n + –p diodes vs<br />
phosphorus implantation dose, calculated with a process and device<br />
simulator ‘‘ISE TCAD’’ for a diode forward bias of 1.2V. A (100)<br />
substrate with a boron doping concentration of 5 · 10 14 cm 3 was<br />
assumed. The curves were obtained for an implantation energy of<br />
135keV. Implantation at 500keV leads to lower carrier densities (see<br />
data points at the right). The furnace anneal is found to result in higher<br />
excess carrier concentrations than RTA.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
are given in Fig. 5. We assumed phosphorus implantation<br />
at 135keV, a (100) substrate with a boron concentration<br />
of 5 · 10 14 cm 3 , annealing according to the<br />
conditions given above in ‘‘Experimental’’, and a diode<br />
forward bias of 1.2V. The calculations show that the excess<br />
carrier density Dn in the base increases with the<br />
implantation dose. Furthermore, furnace anneal yields<br />
a higher excess carrier density than RTA. This means<br />
that the phosphorus depth profile resulting from furnace<br />
anneal produces a higher emitter efficiency than the corresponding<br />
RTA profile.<br />
4.4. Analysis of experimental data<br />
Here we will analyze phosphorus implanted samples<br />
in detail. The internal quantum efficiency was measured<br />
at room temperature under a forward bias of about<br />
1.2V. After implantation at 500keV with a dose of<br />
4 · 10 14 cm 2 we found an efficiency of about 1.16%<br />
for the furnace annealed sample and about 0.6% for<br />
the RTA sample. By applying the process and device<br />
simulator we calculated an excess carrier density, Dn,<br />
of 1.2 · 10 17 cm 3 for the furnace annealed sample and<br />
of 5 · 10 16 cm 3 for the RTA sample, respectively, for<br />
the above given conditions. The corresponding data<br />
points are presented in the gi vs Dn plot of Fig. 4 as full<br />
and open circles, respectively. According to these data,<br />
we may expect a SRH lifetime slightly above 10ls in<br />
the p-type base region of the n + –p diode. Data points<br />
for samples that were implanted with phosphorus at<br />
135keV and a dose of 4 · 10 13 cm 2 are also shown in<br />
Fig. 4. Again, the furnace annealed sample is shown as<br />
full circle and the RTA sample as open circle. In this<br />
case the SRH lifetime is expected to be roughly 30ls.<br />
The higher lifetime in the 135keV/4 · 10 13 cm 2 samples<br />
might be due to a more efficient phosphorus gettering as<br />
compared to the 500keV/4 · 10 14 cm 2 samples.<br />
EBIC measurements (see Ref. [10]) of the P implanted<br />
samples yielded a lower limit for the diffusion length of<br />
electrons (minority carriers) of Ln 200lm inthep-<br />
type base. This value corresponds to a lifetime of<br />
sn 10ls indicative of a high material quality and is<br />
in agreement with our expectations, although a direct<br />
comparison between lifetimes under conditions of EL<br />
and EBIC is difficult.<br />
We also have analyzed the data of Ng [1] given for a<br />
LED formed by implantation of boron at 30keV with a<br />
dose of 1 · 10 15 cm 2 in n-type Cz–Si substrate followed<br />
by furnace anneal. The room temperature efficiency of<br />
the LED was reported to be about 1.6% and the lifetime<br />
of 18ls was measured in base region. For the given<br />
implantation and annealing conditions we obtained an<br />
excess carrier density of Dn =2· 10 17 cm 3 from process<br />
and device simulation for a bias of UF = 1.2V. The corresponding<br />
data point of this sample is presented in Fig.<br />
4 as a full square. Accordingly, we expect a SRH lifetime
τ /τ (100Κ)<br />
100<br />
10<br />
1<br />
∆E = 45meV<br />
low injection<br />
β = 0.01<br />
high injection<br />
β = 100<br />
100 150 200<br />
T (K)<br />
250 300<br />
Fig. 6. Temperature behavior of the SRH lifetime calculated for<br />
shallow traps with an energetic position of DE = 45meV from the band<br />
edge. The lifetime is found to increase with temperature for both, low<br />
injection (b = 0.01) and high injection (b = 100).<br />
of approximately 10ls in the n-type base region of the<br />
diode. This value is close to the lifetime of 18ls that<br />
was determined directly (see Ref. [1]).<br />
4.5. Anomalous temperature behavior of light emission<br />
For excess carrier densities of about Dn 100 between 100 and<br />
300K, and even for high injection—b = 100—there still<br />
appears a lifetime increase by a factor of about 10.<br />
On the other hand, the radiative recombination coefficient<br />
drops upon increase of temperature approxi-<br />
[9] E. Spenke, in: W. Heywang and R. Müller, (Eds.), ‘‘pn-<br />
Übergänge’’, Band 5 in series, Halbleiter-ElektronikÔ, Springer-<br />
Verlag, Berlin–Heidelberg–New York (1979).<br />
[10] C.J. Wu, D.B. Wittry, J. Appl. Phys. 49 (1978) 2827.<br />
[11] H.J. Leamy, L.C. Kimerling, S.D. Ferris, in: O. Johari (Ed.),<br />
Proc. Workshop on Microelectronic Device Fabrication and<br />
Nachdrucke<br />
ausgewählter Publikationen<br />
Reprints of<br />
Selected Publications<br />
M. Kittler et al. / Optical Materials xxx (<strong>2004</strong>) xxx–xxx 5<br />
mately according to B(T) / (300K/T) 3/2<br />
[13].<br />
Nevertheless, the lifetime increase overcompensates the<br />
decrease of B(T). Thus, the description based on relations<br />
(1)–(4) allows to explain the anomalous temperature<br />
behavior of the light emission efficiency shown<br />
e.g. in Fig. 1. Hence, this, modelÕ does not require a<br />
quantum confinement at dislocations to explain the efficient<br />
light emission from Si, as suggested in Ref. [1].<br />
Even the existence of spatial indirect excitons, mentioned<br />
by Sun et al. [14], seems not to be necessary for<br />
explanation of the anomalous temperature behavior.<br />
5. Summary<br />
We can state that the experimental efficiency data fit<br />
well with the g i vs Dn plot shown in Fig. 4. This holds<br />
for the influence of annealing (furnace vs RTA), for the<br />
influence of implantation energy and dose and also for<br />
data of the boron implanted diode given in the literature.<br />
Moreover, a tentative explanation of the anomalous temperature<br />
behavior of the light emission could be given.<br />
This demonstrates that high luminescence may satisfactorily<br />
be explained by high bulk SRH lifetimes and large<br />
excess carrier densities that can be reached by forward<br />
biasing of the LED. Accordingly, we believe that a room<br />
temperature efficiency in the range of 5% is a value that<br />
might be realized, see also Fig. 4.<br />
Acknowledgement<br />
The financial support for this research by the HWP<br />
grant of the Federal Government of Germany and the<br />
State of Brandenburg is gratefully acknowledged.<br />
References<br />
[1] W.L. Ng, M.A. Lourenco, R.M. Gwilliam, S. Ledain, G. Shao,<br />
K.P. Homewood, Nature 410 (2001) 192.<br />
[2] M. Kittler, T. Arguirov, W. Seifert, SPIE Proc. Int. Soc. Opt.<br />
Eng. 5327 (<strong>2004</strong>) 164.<br />
[3] V. Kveder, M. Kittler, W. Schröter, Phys. Rev. B 63 (2001)<br />
115208.<br />
[4] T. Arguirov, M. Kittler, W. Seifert, D. Bolze, K.E. Ehwald, P.<br />
Formanek, J. Reif, in: H. Richter, M. Kittler (Eds.), Proc. 10th<br />
International Autumn Meeting on Gettering and Defect Engineering<br />
in Semiconductor Technology (GADEST 2003), Solid<br />
State Phenom. 95–96 (<strong>2004</strong>) 289.<br />
[5] D.K. Schroder, in: M. Kittler (Ed.), Proc. 3rd International<br />
Autumn Meeting on Gettering and Defect Engineering in Semiconductor<br />
Technology (GADEST Õ89), Solid State Phenom. 6–7<br />
(1989) 383.<br />
[6] H. Schlangenotto, H. Maeder, W. Gerlach, Phys. Stat. Sol. (a) 21<br />
(1974) 357.<br />
[7] J. Dziewior, W. Schmid, Appl. Phys. Lett. 31 (1977) 346.<br />
[8] T. Trupke, J. Zhao, A. Wang, R. Corkish, M.A. Green, Appl.<br />
Phys. Lett. 82 (2003) 2996.<br />
Quality Control with the SEM, IIT Research Institute, Chicago,<br />
IL 60616, Scan. Electron Micros. (Part IV) (1976) 529.<br />
[12] M. Kittler, W. Seifert, Phys. Stat. Sol. (a) 138 (1993) 687.<br />
[13] R.N. Hall, Proc. Inst. Elect. Eng. 106B (17) (1960) 983.<br />
[14] J.M. Sun, T. Dekorsky, W. Skorupa, B. Schmidt, M. Helm,<br />
Appl. Phys. Lett. 83 (2003) 3885.<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 123
Erschienene Publikationen Published Papers<br />
Erschienene Publikationen<br />
Published Papers<br />
(1) Distribution and Properties of Oxide Precipitates<br />
in Annealed Nitrogen-doped 300 mm<br />
Si Wafers<br />
V.D. Akhmetov, H. Richter, W. Seifert, O. Lysytskiy,<br />
R. Wahlich, T. Müller, M. Reiche<br />
European Journal of Applied Physics 27, 159<br />
(<strong>2004</strong>)<br />
Spatial distribution and properties of oxide were examined<br />
in 300 mm nitrogen (N) doped CZ-Si. Experimentally<br />
grown materials with N ranging from 10 13 cm -3<br />
to 10 15 cm -3 were studied by infrared light scattering<br />
tomography, scanning infrared microscopy, transmission<br />
electron microscopy and electron beam induced<br />
current. It was established that an increasing N content<br />
improves the uniformity of the radial distribution<br />
of precipitates in the bulk of the wafer, the density of<br />
precipitates reaching a level of 10 9 cm -3 . The width of<br />
the denuded zone varies in the range from 15 µm to<br />
70 µm depending on radial position and N doping level.<br />
Electron microscopy revealed lower oxide precipitate<br />
densities of about 10 5 to 10 8 cm -3 . The results are interpreted<br />
in terms of existence of agglomerates of nanometer<br />
size precipitate nuclei and/or by the defectinduced<br />
strain relaxation around the precipitates.<br />
(2) Effects of Various Ci/Ti and Co/TiN Layer<br />
Stacks and the Silicide Rapid Thermal Process<br />
Conditions on Cobalt Silicide Formation<br />
S. Buschbaum, O. Fursenko, D. Bolze, D. Wolansky,<br />
V. Melnik, J. Nieß, W. Lerch<br />
Microelectronic Engineering 76, 311 (<strong>2004</strong>)<br />
The effects of cap layer type (Ti or TiN) and its thickness,<br />
Co thickness and rapid thermal processing (RTP)<br />
temperature on cobalt silicide formation are investigated<br />
by a combination of electrical and optical measurements.<br />
Various Co/TiN and Co/Ti layer stacks (thicknesses<br />
8-20 nm per layer) were deposited on (100) Si<br />
substrates. The first RTP step (RTP1) was performed<br />
by isochronal annealing at various temperatures between<br />
400 and 600°C for 30 s. It was observed that<br />
the temperature range for constant sheet resistance<br />
(Rs) values after the first RTP step (RTP1 process window)<br />
is smaller for the Co/TiN layer stacks than it<br />
124<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
is for the Co/Ti layer stacks. After the subsequent<br />
selective etch step the second RTP step (RTP2) was<br />
performed at 800°C for 30 s. Rs after RTP2 strongly<br />
depends on the initial Co thickness and its uniformity<br />
for both systems if the RTP1 temperature was above<br />
470°C. For the Co/TiN layer stacks the final Rs results<br />
are not influenced by the RTP1 temperature or<br />
its uniformity (above 470°C). In this case silicidation<br />
is independent of the cap thickness. However, in the<br />
Co/Ti system the reactive Ti influences the silicidation<br />
process by reducing the amount of available Co in<br />
a manner that depends on the RTP1 temperature and<br />
the Ti cap thickness.<br />
(3) Aluminum Gettering in Photvoltaic Silicon<br />
J. Chen, D. Yang, X. Wang, D. Que, M. Kittler<br />
European Physical Journal of Applied Physics<br />
27, 119 (<strong>2004</strong>)<br />
The effect of aluminum gettering on different silicon<br />
materials used for solar cells has been investigated by<br />
means of microwave photoconductivity decay (µ-PCD)<br />
and electron beam induced current (EBIC). µ-PCD<br />
measurement revealed that the lifetime of multicrystalline<br />
silicon (mc-Si) with a lower initial lifetime could<br />
be increased by high temperature gettering (1000°C),<br />
while that of mc-Si with a higher initial lifetime could<br />
not be increased, but was even degraded. EBIC results<br />
revealed that no significant improvement of diffusion<br />
length was observed in both contaminated and<br />
uncontaminated wafers, while 850°C Al gettering was<br />
employed. It is concluded that both the initial material<br />
quality and the thermal treatment have influences on<br />
the effect of Al gettering. In addition, dislocations with<br />
bright EBlC contrast were discovered in annealed mc-<br />
Si wafers, the origin of which is discussed.<br />
(4) Assessing the Performance of Two-Dimensional<br />
Dopant Profi ling Techniques<br />
N. Duhayon, P. Eyben, M. Fouchier, T. Clarysse,<br />
W. Vandervorst, D. Alvarez, S. Schoemann,<br />
M. Ciappa, M. Stangoni, W. Fichtner, P. Formanek,<br />
M. Kittler, V. Raineri, F. Giannazzo, D. Goghero,<br />
Y. Rosenwaks, R. Shikler, S. Saraf, S. Sadewasser,<br />
N. Barreau, T. Glatzel, M. Verheijen, S.A.M. Mentink,<br />
M. von Sprekelsen, T. Maltezopoulos, R. Wiesendanger,<br />
L. Hellemans<br />
Journal of Vacuum Science & Technology B 22<br />
(1), 385 (<strong>2004</strong>)
This article discusses the results obtained from an<br />
extensive comparison set up between nine different<br />
European laboratories using different two-dimensional<br />
(2D) dopant profiling techniques (SCM, SSRM, KPFM,<br />
SEM, and electron holography). This study was done<br />
within the framework of a European project (HERCU-<br />
LAS), which is focused on the improvement of 2Dprofiling<br />
tools. Different structures (staircase calibration<br />
samples, bipolar transistor, junctions) were used.<br />
By comparing the results for the different techniques,<br />
more insight is achieved into their strong and weak<br />
points and progress is made for each of these techniques<br />
concerning sample preparation, dynamic range,<br />
junction delineation, modeling, and quantification.<br />
Similar results were achieved for similar techniques.<br />
However, when comparing the results achieved with<br />
different techniques differences are noted.<br />
(5) Electron Holography on Silicon Microstructures:<br />
A Comparison with Scanning Probe<br />
Techniques<br />
P. Formanek, M. Kittler<br />
Journal of Physics: Condensed Matter 16, 193<br />
(<strong>2004</strong>)<br />
Two-dimensional dopant profiling is being strongly demanded<br />
by the semiconductor industry, and several<br />
techniques have been developed in recent years. We<br />
compare the performance of electron holography in<br />
a transmission electron microscope with other microscopic<br />
techniques. The advantages of electron holography<br />
are the high spatial resolution of a few nanometres<br />
and the direct interpretability of the measured<br />
two-dimensional electrostatic potential requiring no simulation.<br />
We demonstrate the detection of a 0.5 monolayer<br />
of boron in silicon and silicon germanium. We<br />
image a 35 nm wide potential dip of 25 mV in a boron-doped<br />
specimen, corresponding to detection of a<br />
2 x 10 17 B cm -3 dip between peaks of 2 x 10 18 B cm -3 .<br />
Moreover, we illustrate directly by electron holography<br />
the existence of a potential barrier at NiSi 2 precipitates<br />
in silicon, which was predicted earlier by the electronbeam-induced<br />
current technique.<br />
(6) Development of Spectroscopic Ellipsometry<br />
as in-line Control for Co SALICIDE Process<br />
O. Fursenko, J. Bauer, A. Goryachko, D. Bolze,<br />
P. Zaumseil, D. Krüger, D. Wolansky, E. Bugiel,<br />
B. Tillack<br />
Thin Solid Films 450, 248 (<strong>2004</strong>)<br />
Erschienene Publikationen Published Papers<br />
This work is aimed at in-line thickness and composition<br />
analysis of Co silicides by spectroscopic ellipsometry<br />
(SE). The silicides were formed by a two-step<br />
rapid thermal annealing (RTA) in nitrogen at different<br />
temperatures from initial Co layers deposited on Si<br />
(100) substrates and capped by a protective layer<br />
of TiN. The optical constants of Co, CoSi and CoSi<br />
films were calculated in the wavelength range of 240 x<br />
800 nm, describing the optical dispersions by harmonic<br />
oscillator models. These models were applied for<br />
in-line thickness and composition control of the main<br />
steps of Co SALICIDE process. The effects of the first<br />
RTA temperature and initial Co thickness on formation<br />
of silicide phases and their thickness were evaluated.<br />
For phase identification, additional methods (sheet resistance,<br />
Auger electron spectroscopy and X-ray diffraction)<br />
were used. Finally, the suitability of SE for<br />
layer thickness uniformity evaluation was demonstrated<br />
for the main steps of Co SALICIDE process.<br />
(7) Raman Investigation of Stress and Phase<br />
Transformation Induced in Silicon by Identation<br />
at High Temperatures<br />
S. Kouteva-Arguirova, V. Orlov, W. Seifert,<br />
J. Reif, H. Richter<br />
European Physics Journal – Applied Physics 27<br />
(1-3), 279 (<strong>2004</strong>)<br />
To study the material deterioration at and around the<br />
support contacts during processing of silicon wafers,<br />
we used Rockwell indentation at elevated temperatures<br />
as a model. Cz-silicon was subjected for 30 s to a load<br />
of 1.5 N, at temperatures between 70°C and 660°C.<br />
The resulting morphology was checked by scanning<br />
electron microscopy. Micro Raman spectroscopy was<br />
used to monitor residual stress and the occurrence<br />
of silicon polymorphs. We found strong compressive<br />
stress inside the indented area, with a dramatic drop<br />
and reversal to tensile stress at its boundary. The morphology<br />
shows a top hat profile, covered with a mesh<br />
of vein-like structures. Crystalline phases such as Si-III,<br />
Si-IV, Si-XII, and amorphous silicon are observed. Outside<br />
the spot, the situation depends strongly on the<br />
indentation temperature. Up to 400°C the material appears<br />
practically unstressed, with a high density of<br />
relaxation cracks. At 500°C and 600°C a transition is<br />
found from strong tensile stress at the boundary to<br />
another region of compressive stress extending over<br />
more than 40 µm, associated with a significantly lower<br />
crack density. At still higher temperature (660°C)<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 125
Erschienene Publikationen Published Papers<br />
the crack density tends to zero, and comparably weak<br />
stress seams to oscillate between compressive and<br />
tensile.<br />
(8) Baseband Processor for IEEE 802.11a Standard<br />
with embedded BIST<br />
M. Krstic, K. Maharatna, A. Troya, E. Grass,<br />
U. Jagdhold<br />
Facta Universitatis, Series: Electronics and<br />
Energetics 17, 231 (<strong>2004</strong>)<br />
In this paper results of an IEEE 802.11a compliant lowpower<br />
baseband processor implementation are presented.<br />
The detailed structure of the baseband processor<br />
and its constituent blocks is given. A design for<br />
testability strategy based on Built-In Self-Test (BIST) is<br />
proposed. Finally, implementational results and power<br />
estimation are reported.<br />
(9) Characterization of Ge Gradients in SiGe<br />
HBTs by AES Depth Profi le Simulation<br />
D. Krüger, A. Penkov, Y. Yamamoto, A. Goryachko,<br />
B. Tillack<br />
Applied Surface Science 224 (1-4), 51 (<strong>2004</strong>)<br />
We show that AES depth profiling extended by a simple<br />
profile simulation technique allows characterization<br />
of details in the Ge concentration gradients for SiGe<br />
hetero-bipolar transistors (HBTs). Using the mixingroughness-information<br />
depth (MRI) model to simulate<br />
the experimental data allows us to reveal concentration<br />
steps with a precision of about +or-2 at.% and<br />
small deviations from linear concentration gradients.<br />
The obtainable high lateral resolution of AES facilitates<br />
an application for process optimization and control in<br />
small microelectronic structures.<br />
(10) Diffusion and Segregation of Shallow As<br />
and Sb Junctions in Silicon<br />
D. Krüger, H. Rücker, B. Heinemann, V. Melnik,<br />
R. Kurps, D. Bolze<br />
Journal of Vacuum Science and Technology 22<br />
(1), 455 (<strong>2004</strong>)<br />
The diffusion and segregation of Sb and As is investigated<br />
after low-energy implantation and annealing,<br />
both rapid thermal processing and furnace annealing.<br />
We demonstrate that the absence of transient enhanced<br />
diffusion effects for Sb facilitates the fabrication<br />
of signifi cantly shallower junctions with less dopant se-<br />
126<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
gregation to the surface. It is shown that Sb implantation<br />
can be used to fabricate low-resistivity ultrashallow<br />
junctions suitable for source/drain extensions in n-type<br />
metal-oxide-semiconductor fi eld effect transistors.<br />
(11) Oxide Formation During Ion Bombardement<br />
of Small Silicon Structures<br />
D. Krüger, P. Formanek, E. Pippel, J. Woltersdorf,<br />
E. Bugiel, R. Kurps, G. Weidner<br />
Journal of Vacuum Science and Technology<br />
B 22 (3), 1179 (<strong>2004</strong>)<br />
The kinetics of high dose oxygen implantation and of<br />
surface sputtering in silicon are investigated by atomic<br />
force microscopy, transmission electron microscopy,<br />
transmission electron holography, and electron<br />
energy-loss spectroscopy. The implantation was performed<br />
into accurately defined submicrometer areas.<br />
The behavior of the erosion rate as a function of the<br />
implantation dose proved to be nonmonotonic. After<br />
native oxide sputtering, a period dominated by (i) implantation<br />
of oxygen and (ii) induced oxide formation<br />
with volume increase takes place, causing a maximum<br />
surface step around the bombarded area of about 1.1 to<br />
1.3 nm at bombardment doses below 2 x 10 16 O+ cm -2 .<br />
Subsequently, higher doses cause a sputtering of the<br />
surface with a sputter yield of about 0.32 Si atoms/<br />
O+. Electron holography revealed the double layer<br />
character of the implanted region, and electron energy-loss<br />
spectroscopy, especially near the relevant Si-<br />
L23 ionization edge, identified these two layers which<br />
are (i) amorphous silicon oxide and (ii) amorphized silicon.<br />
Electron energy-loss line scans show the oxygen<br />
distribution inside the implanted areas with a lateral<br />
resolution of about 1-2 nm. It was found that the interface<br />
between the oxidized layer and the amorphized<br />
silicon sharpens with increasing implantation dose.<br />
(12) Some Open Issues on Internetworking for<br />
the Next Generation<br />
P. Langendörfer, V. Tsaoussidis<br />
Computer Communications 27 (10), 908 (<strong>2004</strong>)<br />
In this survey we focus on open issues of the wireless<br />
Internet. Our main intention is to elaborate what has to<br />
be done to integrate mobile devices in the Internet in<br />
such way that users do not experience any difference<br />
between wireless and fixed connections. We concentrate<br />
on the layers on top of IP, i.e. transport protocols,<br />
middleware platforms and applications. We pro-
vide an overview of existing solutions and a discussion<br />
of open issues and promising research directions is<br />
given for each of these fields.<br />
(13) Solid State Reaction between Pr and SiO 2<br />
Studied by Photoelectron Spectroscopy and<br />
ab initio Calculations<br />
G. Lupina, J. Dabrowski, P. Formanek, D. Schmeißer,<br />
R. Sorge, C. Wenger, P. Zaumseil, H.-J. Müssig<br />
Materials Science in Semiconductor Processing<br />
7 (4-6), 215 (<strong>2004</strong>)<br />
We report on the structural and electrical properties of<br />
Pr-based high-k dielectric fi lms fabricated by solid-state<br />
reaction between metallic Pr and SiO 2 underlayers.<br />
A non-destructive depth profi ling using synchrotron radiation<br />
excited photoelectron spectroscopy (SR-PES),<br />
X-ray photoelectron spectroscopy (XPS) and transmission<br />
electron microscopy (TEM) were employed to examine<br />
the chemical composition and microstructure. Ab<br />
initio calculations were done to gain insight into the physical<br />
processes involved. SR-PES results indicate that<br />
Pr deposition at room temperature (RT) leads to the formation<br />
of a Pr silicide and a Pr oxide, what is in good<br />
agreement with the scenario expected from ab initio<br />
calculations. As revealed by TEM and electrical measurements,<br />
oxidation of the reacted structures, followed<br />
by annealing, results in a stacked dielectric composed<br />
of a SiO 2 -based buffer with an enhanced permittivity<br />
and a Pr silicate fi lm with a high dielectric constant. The<br />
leakage current density of 10 −4 A/cm 2 was measured<br />
for stacks with capacitance equivalent thickness (CET)<br />
of 1.5 nm prepared by evaporation of the Pr layer on<br />
a 1.8 nm SiO 2 fi lm, followed by oxidation in air ambient<br />
and annealing in N 2 atmosphere. The capacitance-voltage<br />
(C-V) curves exhibit a large fl atband voltage (V FB )<br />
shift indicating the presence of a positive charge in the<br />
stack. Switching away from the Al contacts to Au gate<br />
electrodes introduces a signifi cant reduction of the V FB<br />
by 1.3 eV, what is much more than the change expected<br />
from the work function difference between Al and<br />
Au (~0.9 eV). This in turn implies that V FB is strongly affected<br />
by the gate interface electrode.<br />
(14) A 64-Point Fourier Transform Chip for High<br />
Speed Wireless LAN Application Using<br />
OFDM<br />
K. Maharatna, E. Grass, U. Jagdhold<br />
IEEE Journal of Solid State Circuits 39 (3), 484<br />
(<strong>2004</strong>)<br />
Erschienene Publikationen Published Papers<br />
In this paper, we present a novel fi xed-point 16-bit wordwidth<br />
64-point FFT/IFFT processor developed primarily<br />
for the application in an OFDM-based IEEE 802.11a<br />
wireless LAN baseband processor. The 64-point FFT<br />
is realized by decomposing it into a two-dimensional<br />
structure of 8-point FFTs. This approach reduces the<br />
number of required complex multiplications compared<br />
to the conventional radix-2 64-point FFT algorithm. The<br />
complex multiplication operations are realized using<br />
shift-and-add operations. Thus, the processor does not<br />
use a two-input digital multiplier. It also does not need<br />
any RAM or ROM for internal storage of coeffi cients.<br />
The proposed 64-point FFT/IFFT processor has been<br />
fabricated and tested successfully using our in-house<br />
0.25-µm BiCMOS technology. The core area of this chip<br />
is 6.8 mm 2 . The average dynamic power consumption<br />
is 41 mW at 20 MHz operating frequency and 1.8 V supply<br />
voltage. The processor completes one parallel-toparallel<br />
(i.e., when all input data are available in parallel<br />
and all output data are generated in parallel) 64-point<br />
FFT computation in 23 cycles. These features show that<br />
though it has been developed primarily for application<br />
in the IEEE 802.11a standard, it can be used for any<br />
application that requires fast operation as well as low<br />
power consumption.<br />
(15) Fast Nondestructive Technique to Determine<br />
the Content of Components in a Strain-Compensated<br />
Crystalline Ternary Alloy<br />
A.Y. Nikulin, P. Zaumseil<br />
Journal of Applied Physics 95, 5249 (<strong>2004</strong>)<br />
The x-ray Bragg diffraction intensity profile for a model<br />
strain-compensated structure consisting of a thin<br />
SiGe alloy layer grown on a thick Si substrate is derived<br />
using a Laplace transform interpretation of the<br />
kinematical approximation of x-ray diffraction theory.<br />
It is shown that in the case of fully strain-compensated<br />
crystals a simplified x-ray phase-retrieval technique<br />
can be applied to determine the alloy composition<br />
from this x-ray diffraction data. An experimental intensity<br />
profile from an almost perfectly unstrained SiGe:<br />
C/Si structure is analyzed using this method.<br />
(16) Stability and Electronic Properties of Silicates<br />
in the System SiO 2 -Pr 2 O 3 -Si(001)<br />
D. Schmeißer, H.-J. Müssig<br />
Journal of Physics Condensed Matter 16, 153<br />
(<strong>2004</strong>)<br />
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Erschienene Publikationen Published Papers<br />
Pr 2 O 3 is one of the most promising hetero-oxides that<br />
are the candidates of choice to replace SiO 2 as the<br />
gate dielectric material for sub-0.1 µm CMOS technology.<br />
In order to enable process integration, however,<br />
hetero-oxides require substantial characterization. In<br />
particular, the basic interaction mechanisms at the interface<br />
to the silicon substrate are the key issues. A<br />
solid knowledge of these mechanisms is required to<br />
address reliability arguments. The challenges in material<br />
science are to understand the chemical bonding<br />
of the hetero-oxides and Si on a microscopic scale.<br />
We report on the specific variations in the electronic<br />
structure which are evident in the valence band features<br />
around resonant excitation at the Pr 4d threshold.<br />
We also determine the valence band discontinuities<br />
at the Pr 2 O 3 /Si(001) interface and follow the<br />
changes in the surface potentials to develop a band<br />
scheme, a prerequisite to understanding the properties<br />
of charge transport across that interface.<br />
(17) Pr 2 O 3 / Si(001) Interface Reactions and Stability<br />
D. Schmeißer, J. Dabrowski, H.-J. Müssig<br />
Materials Science and Engineering B 109, 30<br />
(<strong>2004</strong>)<br />
We show that an interfacial silicate is formed in a natural<br />
way between Si(001) and the deposited Pr 2 O 3 fi l m i f<br />
a suffi cient amount of oxygen is provided during deposition,<br />
as during electron beam evaporation from Pr 6 O 11<br />
source. We provide arguments from results of ab initio<br />
calculations and we present a ternary phase diagram of<br />
the Pr-O-Si system obtained for epitaxial fi lms from nondestructive<br />
depth profi ling data acquired by synchrotron<br />
radiation and photo-electron spectroscopy (SR-PES) at<br />
the undulator beam line U49/2-PGM2. The composition<br />
of the interfacial layer is (Pr 2 O 3 )(SiO) x (SiO 2 ) y with x+y<br />
between 2 and 6 and depends on the growth conditions<br />
and distance from the substrate. No interfacial<br />
SiO 2 and no interfacial silicide is formed during growth.<br />
The ternary phase diagram indicates that this non-stoichiometric<br />
pseudobinary alloy is stable on Si up to high<br />
temperatures, without phase separation into Pr 2 O 3 and<br />
SiO 2 . Therefore, a complete re-engineering of the CMOS<br />
process may be not necessary.<br />
(18) Silicate Layer Formation at Pr 2 O 3 /Si(001)<br />
Interfaces<br />
D. Schmeißer, H.-J. Müssig, J. Dabrowski<br />
Applied Physics Letters 85, 88 (<strong>2004</strong>)<br />
128<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
We studied Pr 2 O 3 /Si(001) interfaces by synchrotron<br />
radiation photoelectron spectroscopy and by ab initio<br />
calculations. We show that the interface formed during<br />
molecular-beam epitaxy under the oxygen partial pressure<br />
above 1×10 –8 mbar consists of a mixed Si-Pr oxide,<br />
such as (Pr 2 O 3 )(SiO) x (SiO 2 ) y . Neither an interfacial SiO 2<br />
nor an interfacial silicide is formed. The silcate formation<br />
is driven by a low energy of O in a PrOSi bond and<br />
by the strain in the subsurface SiO x layer. We expect that<br />
this natural interfacial Pr silicate will facilitate the integration<br />
of the high-k dielectric Pr 2 O 3 into future complementary<br />
metal-oxide-semiconductor technologies.<br />
(19) Pr 4 f Occupancy and VB/CB Band Offsets of<br />
Pr 2 O 3 at the Interface to Si (001) and SiC<br />
(0001) Surfaces<br />
D. Schmeißer, H.-J. Müssig<br />
Materials Science in Semiconductor Processing<br />
7, 221 (<strong>2004</strong>)<br />
Resonant photoelectron spectroscopy (PES) at the<br />
Pr 4 d and O1 s absorption edges is used to study the<br />
electronic properties at the interface of epitaxially<br />
grown Pr 2 O 3 on Si(001). In the electronic structure of<br />
bulk Pr 2 O 3 , the valence band (VB) states are predominant<br />
of Pr 6 s and O 2 p atomic parentage. The contribution<br />
of Pr 4 f states is identified from the strong increase<br />
of the VB features at the Pr 4 d resonances. The<br />
data at the O1s edge are caused by Raman scattering<br />
and resonant Auger decay and reflect the existence of<br />
charge transfer (CT) complexes. These complexes are<br />
the consequence of a mixed valency caused by ligandto-Pr<br />
4 f charge transfer states. The decrease of their<br />
intensity is attributed to an increase in covalent bandwidth<br />
between the ligand (O 2 p, Si 3 p) and Pr 4 f states.<br />
The CT complexes, originally localized now, become<br />
broadened and form gap states which fill the gap towards<br />
a metallic density of states. The metallic phase<br />
may be hindered upon alloying with SiO 2 or other<br />
oxides.<br />
(20) Structure and Thickness-dependent Lattice<br />
Parameters of Ultrathin Epitaxial Pr 2 O 3<br />
Films on Si(001) Studied by SR-GIXRD<br />
T. Schröder, T.-L. Lee, J. Zegenhagen, C. Wenger,<br />
P. Zaumseil, H.-J. Müssig<br />
Applied Physics Letters 85 (7), 1229 (<strong>2004</strong>)<br />
Pr 2 O 3 grown heteroepitaxially on Si(001) is a promising<br />
candidate for applications as a high-k dielectric
in future silicon-based microelectronics devices. The<br />
technologically important thickness range from 1 to<br />
10 nm has been investigated by synchrotron radiation-grazing<br />
incidence x-ray diffraction. The oxide film<br />
grows as cubic Pr 2 O 3 phase with its (101) plane on the<br />
Si (001) substrate in form of two orthogonal rotation<br />
domains. Monitoring the evolution of the oxide unit-cell<br />
lattice parameters as a function of film thickness from<br />
1 to 10 nm, the transition from almost perfect pseudomorphism<br />
to bulk values is detected.<br />
(21) Formation of Heavily P-doped Si Epitaxial<br />
Films on Si(100) by Multiple Atomic-Layer<br />
Doping Technique<br />
Y. Shimamune, M. Sakuraba, J. Murota, B. Tillack<br />
Applied Surface Science 224 (1-4), 202<br />
(<strong>2004</strong>)<br />
Phosphorus (P) incorporation process during Si epitaxial<br />
growth by SiH 4 reaction in ultraclean low-pressure<br />
chemical vapor deposition (CVD) and the electrical<br />
characteristics of the heavily P-doped epitaxial Si<br />
film on Si(100) have been investigated. Si layer growth<br />
on the P layer formed on Si(100) at 500°C at SiH 4 partial<br />
pressure of 6 Pa is observed when the surface P<br />
amount becomes below 7x10 14 cm -2 . It is also found<br />
that about 1.1x10 14 cm -2 P atoms segregate onto the<br />
Si surface and the other desorbs. On the other hand,<br />
by lowering the Si growth temperature to 450°C and<br />
increase in the SiH 4 partial pressure to 220 Pa, P incorporation<br />
occurs and about 1.5x10 14 cm -2 P atoms<br />
are buried at the initial position without segregation.<br />
By using the multiple atomic-layer doping technique,<br />
very low-resistive heavily P-doped epitaxial Si film on<br />
Si(100) can be formed with effective suppression of<br />
the electrically inactive P formation.<br />
(22) High Performance SiGe:C HBTs Using Atomic<br />
Layer Base Doping<br />
B. Tillack, Y. Yamamoto, D. Knoll, B. Heinemann,<br />
P. Schley, B. Senapati, D. Krüger<br />
Applied Surface Science 224, 55 (<strong>2004</strong>)<br />
We applied atomic layer processing for base doping of<br />
high performance SiGe:C heterojunction bipolar transistors<br />
(HBTs) fabricated within a 0.25 mm BiCMOS<br />
technology. B atomic layer doping (ALD) was performed<br />
at 400°C during an interruption of the epitaxial<br />
SiGe:C base layer deposition. Atomic level dopant location<br />
and dose control was achieved. Electrical pro-<br />
Erschienene Publikationen Published Papers<br />
perties of atomic layer and box-profile doped (standard)<br />
HBTs were compared, showing peak f T and f max<br />
for the ALD HBT of 113 and 127 GHz, and of 108 and<br />
123 GHz for the standard HBT, respectively. The internal<br />
base sheet resistances (RSBi) for the ALD and<br />
standard HBTs were comparable, indicating very similar<br />
active B dose for both doping variants. The HBT results<br />
demonstrate the capability of atomic layer processing<br />
for doping of advanced devices, with critical<br />
requirements for dose and location control.<br />
(23) Recombination Activity and Electrical Levels<br />
of Dislocations in p-type SiGe Structures:<br />
Impact of Copper Contamination and Hydrogenation<br />
O.F. Vyvenko, M. Kittler, W. Seifert<br />
Journal of Applied Physics 96 (11), 6425 (<strong>2004</strong>)<br />
The impact of copper contamination and subsequent<br />
hydrogenation on recombination activity and hole-trap<br />
levels of misfi t dislocations were investigated in p-type<br />
Si/Si 0.98 Ge 0.02 /Si structures. In the as-grown (noncontaminated)<br />
samples, dislocations were found to exhibit<br />
very low recombination activity, detectable with the<br />
electron-beam-induced current technique only at low<br />
temperatures. Deep-level transient spectroscopy revealed<br />
a dislocation-related hole-trap level at E t = E v +<br />
0.2 eV. The position of the observed level is close to the<br />
theoretically predicted hole-trap state of the intrinsic<br />
stacking fault of a dissociated dislocation. Contamination<br />
with a low copper concentration [5 (parts per 10 9 )<br />
ppb] gave rise to a large increase of the recombination<br />
activity of the dislocations and to the appearance<br />
of another dislocation-related defect level at E t = E v +<br />
0.32 eV. Hydrogenation of the samples by a treatment<br />
with an acid solution and subsequent reverse-bias anneal<br />
at380 K resulted in the evolution of the levels of substitutional<br />
copper and its complexes with hydrogen.<br />
(24) First Investigation of MIM Capacitors Using<br />
Pr 2 O 3 Dielectrics<br />
C. Wenger, J. Dabrowski, P. Zaumseil, R. Sorge,<br />
P. Formanek, G. Lippert, H.-J. Müssig<br />
Materials Science in Semiconductor Processing<br />
7 (4-6), 227 (<strong>2004</strong>)<br />
Metal-insulator-metal (MIM) capacitors with Pr 2 O 3 as<br />
high-k material have been investigated for the first<br />
time. We varied the thickness of the Pr 2 O 3 layers as<br />
well as the bottom electrode material. The layers are<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 129
Erschienene Publikationen Published Papers<br />
characterised using X-ray photoelectron spectroscopy<br />
(XPS), X-ray diffraction (XRD), transmission electron<br />
microscopy (TEM) and secondary ion mass spectroscopy<br />
(SIMS). Preliminary information on the interaction of<br />
water with the fi lms was obtained from XPS and ab initio<br />
pseudopotential calculations. The electrical characterisation<br />
shows that Pr 2 O 3 MIM capacitors can provide<br />
higher capacitance densities than Si 3 N 4 MIM capacitors<br />
while still maintaining comparable voltage coeffi cients<br />
of capacitance. The Pr 2 O 3 dielectric material seems to<br />
be suitable for use in silicon RF applications.<br />
(25) Circuit Applications of High-Performance<br />
SiGe:C HBTs Integrated in BiCMOS Technology<br />
W. Winkler, J. Borngräber, B. Heinemann, H. Rücker,<br />
R. Barth, J. Bauer, D. Bolze, E. Bugiel, J. Drews, K.-E.<br />
Ehwald, T. Grabolla, U. Haak, W. Höppner, D. Knoll,<br />
D. Krüger, B. Kuck, R. Kurps, S. Marschmeyer, H.H.<br />
Richter, P. Schley, D. Schmidt, R. Scholz, B. Tillack,<br />
D. Wolansky, H.-E. Wulf, Y. Yamamoto, P. Zaumseil<br />
Applied Surface Science 224 (1-4), 297 (<strong>2004</strong>)<br />
Carbon-doped SiGe (SiGe:C) bipolar devices have<br />
been developed and integrated in to a 0.25 µm CMOS<br />
platform. The resulting SiGe:C BiCMOS technology offers<br />
a wide spectrum of active and passive devices for<br />
wireless and wired communication systems. A highperformance<br />
variant of the bipolar transistor has been<br />
derived from the standard transistors by reduction of<br />
some transistor dimensions. With these alterations,<br />
f T and f max of the bipolar transistors reaches 120 and<br />
140 GHz, respectively. Circuit applications of the devices<br />
are demonstrated. Static and dynamic divider<br />
circuits have a maximum input frequency of 62 and 72<br />
GHz, respectively. Integrated LC oscillators with frequencies<br />
up to 60 GHz are also demonstrated.<br />
(26) Carbon and Boron in Heavily Doped SiGe:C/<br />
Si Epilayers Studied by FTIR<br />
V.D. Akhmetov, O. Lysytskiy, Y. Yamamoto,<br />
H. Richter<br />
Electrochemical Society Proceedings Vol.<br />
<strong>2004</strong>-07, 269 (<strong>2004</strong>)<br />
(27) Nitrogen in Thin Silicon Wafers Determined<br />
by Infrared Spectroscopy<br />
V.D. Akhmetov, O. Lysytskiy, H. Richter<br />
Electrochemical Society Proceedings Vol.<br />
<strong>2004</strong>-05, 109 (<strong>2004</strong>)<br />
130<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
(28) HICUM Modeling of SiGe-HBTs Fabricated in<br />
Wafer Bonded SOI Substrates<br />
A. Chakravorty, B. Senapati, G. Dalapati, R. Garg,<br />
C.K. Maiti, G.A. Armstrong, H.S. Gamble, P. Ashburn<br />
and H.A.W. El Mubarek<br />
Proc. International Conference on Computers<br />
and Devices for Communication, 42 (<strong>2004</strong>)<br />
(29) Accurate Modeling of SiGe:C HBTs using<br />
Adaptive Neuro-Fuzzy Inference System<br />
A. Chakravorty, R.F. Scholz, B. Senapati, D. Knoll,<br />
A. Fox, R. Garg, C.K. Maiti<br />
Proc. ISTDM, 264 (<strong>2004</strong>)<br />
(30) Electrical Deactivation and Diffusion of<br />
Boron in Preamorphized Ultrashallow Junctions:<br />
Interstitial Transport and F co-implant<br />
Control<br />
B. Colombeau, A.J. Smith, N.E.B. Cowern,<br />
W. Lerch, S. Paul, B.J. Pawlak, F. Christiano,<br />
X. Hebras, D. Bolze, C. Ortiz, P. Pichler<br />
Technical Digest IEDM, 971 (<strong>2004</strong>)<br />
(31) Preface<br />
J. Dabrowski, H.-J. Müssig<br />
Materials Science in Semiconductor Processing<br />
7 (4-6), 165 (<strong>2004</strong>)<br />
(32) Ab Initio Study of Pr Oxides for CMOS Technology<br />
J. Dabrowski, V. Zavodinsky<br />
Proc. NIC Symposium, 171 (<strong>2004</strong>)<br />
(33) Transistors and Atoms<br />
J. Dabrowski, H.-J. Müssig, E.R. Weber,<br />
W. Schröter<br />
Challenges in Process Simulation / ed. by<br />
J. Dabrowski, E.R. Weber, Berlin, Springer Verlag,<br />
1-38 (<strong>2004</strong>)<br />
(34) Model-driven Design of the WIN Platform<br />
J. deMeer<br />
Proc. ICSSEA, ISSN: 1637-5033, Vol. 3 (<strong>2004</strong>)<br />
(35) High-Level Behavioral SDL Model for the<br />
IEEE 802.15.3. MAC Protocol<br />
D. Dietterle, I. Babanskaja, K. Dombrowski,<br />
R. Kraemer<br />
Proc. WWIC <strong>2004</strong>, Febr. 05-07, <strong>2004</strong>, Frankfurt<br />
(Oder), Germany. - Berlin, Springer, 165 (<strong>2004</strong>)
(36) Mapping of High-Level SDL Models to Effi -<br />
cient Implementations for TinyOS<br />
D. Dietterle, J. Ryman, K. Dombrowski, R. Kraemer<br />
Proc. EUROMICRO Symposium on Digital System<br />
Design, IEEE Computer Society, 402 (<strong>2004</strong>)<br />
(37) A Two Mask Complementary LDMOS Module Integrated<br />
in a 0.25 µm SiGe:C BiCMOS Platform<br />
K.-E. Ehwald, A. Fischer, F. Fürnhammer,<br />
W. Winkler, B. Senapati, R. Barth, D. Bolze,<br />
B. Heinemann, D. Knoll, H. Rücker, D. Schmidt,<br />
I. Shevchenko, R. Sorge, H.-E. Wulf<br />
Proc. ESSDERC, 121 (<strong>2004</strong>)<br />
(38) Bluetooth Indoor Localization System<br />
G. Fischer, B. Dietrich, F. Winkler<br />
Proc. 1 st Workshop on Positioning, Navigation<br />
and Communication <strong>2004</strong>, Hannoversche Beiträge<br />
zur Nachrichtentechnik, 01, 147 (<strong>2004</strong>)<br />
(39) Cost-Effective Integration of an FN-programmed<br />
Embedded Flash Memory into a<br />
0.25 µm RF-BiCMOS Technology<br />
A. Fox, K.-E. Ehwald, P. Schley, R. Barth,<br />
S. Marschmeyer, V.E. Stikanov, A. Gromovyy,<br />
A. Hudyryev<br />
Proc. International Conference on <strong>Microelectronics</strong>,<br />
463 (<strong>2004</strong>)<br />
(40) Spectroscopic Ellipsometry for In-Line Process<br />
Control of SiGe:C HBT Technology<br />
O. Fursenko, J. Bauer, P. Zaumseil, D. Krüger,<br />
A. Goryachko, Y. Yamamoto, K. Köpke, B. Tillack<br />
Proc. ISTDM <strong>2004</strong>, Abstract book, 53 (<strong>2004</strong>)<br />
(41) A DC – 10 GHz Amplifi er With Digital Offset<br />
Correction<br />
H. Gustat<br />
Proc. ISTDM <strong>2004</strong>, Abstract book, 73 (<strong>2004</strong>)<br />
(42) A Fully-Integrated Low-Power Low-Jitter<br />
Clock Synthesizer with 1.2 GHz Tuning Range<br />
in SiGe:C BiCMOS<br />
H. Gustat, F. Herzel, I. Shevchenko<br />
Proc. ISTDM <strong>2004</strong>, Abstract book, 270 (<strong>2004</strong>)<br />
(43) Complementary SiGe BiCMOS<br />
B. Heinemann, J. Drews, D. Knoll, R. Kurps,<br />
S. Marschmeyer, H. Rücker, W. Winkler,<br />
Y. Yamamoto<br />
Erschienene Publikationen Published Papers<br />
Electrochemical Society Proc. SiGe: Materials,<br />
Processing, and Devices : The 1 st International<br />
Symposium, Vol. <strong>2004</strong>-07, 25 (<strong>2004</strong>)<br />
(44) A Low-Parasitic Collector Construction for<br />
High-Speed SiGe:C HBTs<br />
B. Heinemann, R. Barth, D. Bolze, J. Drews, P. Formanek,<br />
T. Grabolla, U. Haak, W. Höppner, D. Knoll,<br />
B. Kuck, R. Kurps, K. Köpke, S. Marschmeyer,<br />
H.H. Richter, H. Rücker, P. Schley, D. Schmidt, W.<br />
Winkler, D. Wolansky, H.-E. Wulf, Y. Yamamoto<br />
Technical Digest IEDM, 251 (<strong>2004</strong>)<br />
(45) Jitter and Phase-Noise in Oscillators and<br />
Phase-Locked Loops<br />
F. Herzel, W. Winkler, J. Borngräber<br />
Proc. SPIE, Fluctuations and Noise, Vol. 5473<br />
(<strong>2004</strong>)<br />
(46) Standardization of Defect Characterization<br />
Technique in Annealed CZ Si<br />
N. Inoue, K. Moriya, K. Kashima, R. Takeda,<br />
V. Akhmetov, O. Lysytskiy, K. Nakashima<br />
Proc. 4 th International Symposium on Advanced<br />
Science and Technology of Silicon Materials,<br />
123 (<strong>2004</strong>)<br />
(47) Kristallines Si für Solarzellen: Status und<br />
Herausforderungen<br />
M. Kittler<br />
Abhandlungen der Leibniz-Sozietät, Vol. 15, 69<br />
(<strong>2004</strong>)<br />
(48) Silicon-based Light Emission After Ion Implantation<br />
M. Kittler, T. Arguirov, W. Seifert<br />
Proc. SPIE, Optoelectronic Integration on Silicon,<br />
Vol. 5357, 164 (<strong>2004</strong>)<br />
(49) Die minimal erzielbare Rekombinationsaktivität<br />
von Versetzungen in Silicium:<br />
Schlussfolgerungen für Solarzellen und für<br />
perspektivische auf Si basierende Lichtemitter<br />
M. Kittler, W. Seifert<br />
Freiberger Siliciumtage 2003, in: Freiberger Forschungshefte:<br />
Werkstofftechnologie, B 327, 89<br />
(<strong>2004</strong>)<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 131
Erschienene Publikationen Published Papers<br />
(50) A Modular, Low-Cost SiGe:C BiCMOS Process<br />
Featuring High-FT and High-BV CEO Transistors<br />
D. Knoll, B. Heinemann, R. Barth, K. Blum,<br />
J. Borngräber, J. Drews, K.-E. Ehwald, G. Fischer,<br />
A. Fox, T. Grabolla, U. Haak, W. Höppner, F. Korndörfer,<br />
B. Kuck, S. Marschmeyer, H.H. Richter,<br />
H. Rücker, P. Schley, D. Schmidt, R.F. Scholz,<br />
B. Senapati, B. Tillack, W. Winkler, D. Wolansky,<br />
C. Wolf, H.-E. Wulf, Y. Yamamoto, P. Zaumseil<br />
Proc. BCTM, 241 (<strong>2004</strong>)<br />
(51) Remote Operations: A Middleware and Distributed<br />
Systems Architecture for Satellite<br />
On-Board Wireless Communication<br />
R. Kraemer, K. Dombrowski, D. Dietterle, P. Langendörfer,<br />
M. Methfessel<br />
Proc. Data Systems in Aerospace, Session 3B<br />
(<strong>2004</strong>)<br />
(52) GALS Baseband Processor for WLAN<br />
M. Krstic, E. Grass<br />
Proc. 4 th ACiD-WG Workshop (<strong>2004</strong>)<br />
(53) GALSifi cation of IEEE 802.11a Baseband<br />
Processor<br />
M. Krstic, E. Grass<br />
Proc. 14 th International Workshop on Power<br />
and Timing Modeling, Optimization and Simulation,<br />
Springer Verlag, LNCS Series 3254, 258<br />
(<strong>2004</strong>)<br />
(54) A Location Aware Revocation Approach<br />
D. Kulikowski, P. Langendörfer, K. Piotrowski<br />
Informatik , Bd. 2, GI-LNI (<strong>2004</strong>)<br />
(55) Plasma – A Middleware for Location-Based<br />
Services: Design, Implementations and Lessons<br />
Learned<br />
P. Langendörfer, O. Maye, Z. Dyka, R. Sorge,<br />
R. Winkler, R. Kraemer<br />
Middleware for Communication, John Wiley &<br />
Sons, 305 (<strong>2004</strong>)<br />
(56) PLASMADS: Smart Mobiles Meet Intelligent<br />
Environments<br />
P. Langendörfer, H. Maass, T. Falck<br />
Proc. 4 th Workshop on Applications and Services<br />
in Wireless Networks, IEEE Press (<strong>2004</strong>)<br />
132<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
(57) A 16-Bit CORDIC Rotator for High-Speed<br />
Wireless LAN<br />
K. Maharatna, A. Troya, S. Banerjee, E. Grass,<br />
M. Krstic<br />
Proc. IEEE PIMRC (<strong>2004</strong>)<br />
(58) Virtually Scaling-Free Adaptive CORDIC rotator<br />
K. Maharatna, A. Troya, S. Banerjee, E. Grass<br />
Proc. of IEEE Computers & Digital Techniques,<br />
Vol. 151, no. 6 (<strong>2004</strong>)<br />
(59) A Cordic Like Processor for Computation of<br />
Arctangent and Absolute Magnitude of a<br />
Vector<br />
K. Maharatna, A. Troya, M. Krstic, E. Grass,<br />
U. Jagdhold<br />
Proc. International Symposium on Circuits and<br />
Systems, Vol. II, 713 (<strong>2004</strong>)<br />
(60) Ultrathin Dielectric Films Grown by Solid<br />
Phase Reaction of Pr with Thermal SiO 2<br />
H.-J. Müssig, J. Dabrowski, C. Wenger, G. Lupina,<br />
R. Sorge, P. Formanek, P. Zaumseil, D. Schmeißer<br />
Materials Research Society Symposium Vol.<br />
811, 253 (<strong>2004</strong>)<br />
(61) High-k Dielectrics: The Example of Pr 2 O 3<br />
H.-J. Osten, J. Dabrowski, H.-J. Müssig, A. Fissel,<br />
V. Zavodinsky<br />
Challenges in Process Simulation, Springer Verlag<br />
Berlin, 259 (<strong>2004</strong>)<br />
(62) Applying Position Prediction as a Means for<br />
Performance-Tuning in Location-Aware Platforms<br />
A. Post, P. Langendörfer, R. Kraemer<br />
Proc. 1 st Workshop on Positioning, Navigation<br />
and Communication, Hannoversche Beiträge<br />
zur Nachrichtentechnik, Shaker Verlag, 179<br />
(<strong>2004</strong>)<br />
(63) Moneta: An Anonymity Providing Lightweight<br />
Payment System for Mobile Devices<br />
K. Piotrowski, P. Langendörfer, D. Kulikowski<br />
Proc. 2 nd International Workshop for Technology,<br />
Economy, Social and Legal Aspects of Virtual<br />
Goods (<strong>2004</strong>)
(64) Ensuring Anonymity in e-commerce Systems<br />
Using a Hidden Identity Approach: Discussion<br />
of Problems and Solutions<br />
K. Piotrowski, P. Langendörfer, O. Maye<br />
Proc. 7 th International Conference on Electronic<br />
Commerce Research (<strong>2004</strong>)<br />
(65) SiGe HBT Design for High-Frequency Applications<br />
H. Rücker, B. Heinemann, R. Barth, D. Knoll,<br />
P. Schley, R. Scholz, B. Tillack, W. Winkler<br />
Proc. ISTDM, 61 (<strong>2004</strong>)<br />
(66) Advances in SiGe HBT Technology in Europe<br />
H. Rücker, W. Winkler<br />
Proc. Compound Semiconductor IC Symposium,<br />
13 (<strong>2004</strong>)<br />
(67) Integration of High-Performance SiGe:C HBTs<br />
with Thin-Film SOI CMOS<br />
H. Rücker, B. Heinemann, R. Barth, D. Bolze,<br />
J. Drews, O. Fursenko, T. Grabolla, U. Haak,<br />
W. Höppner, D. Knoll, S. Marschmeyer, N. Mohapatra,<br />
H.H. Richter, P. Schley, D. Schmidt,<br />
B. Tillack, G. Weidner, D. Wolansky, H.-E. Wulf,<br />
Y. Yamamoto<br />
Technical Digest IEDM, 239 (<strong>2004</strong>)<br />
(68) The System Behavioral Model of IEEE 802.15.3<br />
Mac Protocol – Design and Profi ling<br />
J. Ryman, D. Dietterle, K. Dombrowski, P. Bubacz<br />
Proc. 2 nd International Workshop on Discrete-<br />
Event System Design (<strong>2004</strong>)<br />
(69) Analysis of Microwave Noise Sources in<br />
150 GHz SiGe HBTs<br />
P. Sakalas, M. Schröter, R.F. Scholz, H. Jiang,<br />
M. Racanelli<br />
IEEE RFIC Digest, 291 (<strong>2004</strong>)<br />
(70) A 1 GHz AGC Amplifi er in BiCMOS with 3µs<br />
Settling-Time for 802.11a WLAN<br />
K. Schmalz<br />
Proc. IEEE Norchip, 289 (<strong>2004</strong>)<br />
(71) Advanced Technique for Broadband on-Wafer<br />
RF Device Characterization<br />
R.F. Scholz, F. Korndörfer, B. Senapati, A. Rumiantsev<br />
Erschienene Publikationen Published Papers<br />
63 rd ARFTG Conference Digest, On Wafer Characterization,<br />
83 (<strong>2004</strong>)<br />
(72) Macro Model of Power RF LDMOSFET<br />
B. Senapati, K.-E. Ehwald, I. Shevchenko, F. Fürnhammer<br />
Proc. International Conference on Communications,<br />
Devices and Intelligent Systems, 23<br />
(<strong>2004</strong>)<br />
(73) Application of the VBIC Model for SiGe:C<br />
Heterojunction Transistors<br />
B. Senapati, R.F. Scholz, D. Knoll, B. Heinemann,<br />
A. Chakravorty<br />
Proc. International Conference on Mixed Design<br />
of Integrated Circuits and Systems, 94 (<strong>2004</strong>)<br />
(74) Self-Consistent Characterization of Gate<br />
Controlled Diodes for CMOS Technology<br />
Monitoring<br />
R. Sorge, P. Schley, K.-E. Ehwald<br />
Proc. ESSDERC, 389 (<strong>2004</strong>)<br />
(75) Modular Processor: A Flexible Library of<br />
ASIC Modules<br />
Z. Stamenkovic, G. Panic, U. Jagdhold, H. Frankenfeldt,<br />
K. Tittelbach-Helmrich, G. Schoof,<br />
R. Kraemer<br />
Proc. IASTED International Conference on Applied<br />
Simulation and Modelling, Acta Press, 428<br />
(<strong>2004</strong>)<br />
(76) Atomic Level Control of SiGe Epitaxy and<br />
Doping<br />
B. Tillack, Y. Yamamoto, J. Murota<br />
Proc. SiGe: Materials, Processing, and Devices:<br />
Proceedings of the 1 st International Symposium,<br />
Honolulu, ECS Vol. <strong>2004</strong>-07, 803 (<strong>2004</strong>)<br />
(77) A 117 GHz LC-Oscillator in SiGe:C BiCMOS<br />
Technology<br />
W. Winkler, J. Borngräber, B. Heinemann<br />
Proc. ISTDM, 71 (<strong>2004</strong>)<br />
(78) LC-Oscillators Above 100 GHz in Silicon-<br />
Based Technology<br />
W. Winkler, J. Borngräber, B. Heinemann<br />
Proc. ESSCIRC, 131 (<strong>2004</strong>)<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 133
Eingeladene Vorträge Invited Presentations<br />
(79) High-Frequency Low-Noise Amplifi ers and<br />
Low-Jitter Oscillators in SiGe:C BiCMOS<br />
Technology<br />
W. Winkler, J. Borngräber, F. Herzel, B. Heinemann,<br />
R. Scholz<br />
Proc. SPIE Fluctuations and Noise, Vol. 5470,<br />
185 (<strong>2004</strong>)<br />
(80) 60 GHz Transceiver Circuits in SiGe:C BiCMOS<br />
Technology<br />
W. Winkler, J. Borngräber, F. Herzel, H. Gustat,<br />
B. Heinemann, F. Korndörfer<br />
Proc. ESSCIRC, 83 (<strong>2004</strong>)<br />
Eingeladene Vorträge<br />
Invited Presentations<br />
(1) Determination of Optical Constants Using<br />
Swing Curves<br />
J. Bauer, U. Haak, G. Drescher<br />
Lithography Workshop, Pommelsbrunn, September<br />
17-19, <strong>2004</strong>, Germany<br />
(2) Mobile Application Patterns – Real Time or<br />
Ubiquity?<br />
J. deMeer<br />
UML/Java Workshop für Embedded und Realtime<br />
Systeme, TFH Berlin, July 29, <strong>2004</strong>, Germany<br />
(3) Presentations of the <strong>IHP</strong> PLASMA Platform<br />
J. deMeer, R. Kraemer<br />
Visit of the Middleware Research Labs – Toronto,<br />
Montreal, Nashville, March 27 – April 4,<br />
<strong>2004</strong>, Canada and USA<br />
(4) MEDman – Ubiquitous Medical Assistance<br />
J. deMeer<br />
EUREKA MEDEA+ Board Paris, May 25 and June<br />
3, <strong>2004</strong>, France<br />
(5) Mobile Nutzung von Sensornetzwerken auf<br />
der PLASMA-Plattform<br />
J. deMeer, P. Langendörfer<br />
Ringvorlesung des Instituts für Informatik und<br />
Gesellschaft der Universität Freiburg (Breisgau),<br />
June 28, <strong>2004</strong>, Germany<br />
134<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
(6) Mobile Nutzung von Sensornetzwerken auf<br />
der PLASMA-Plattform<br />
J. deMeer, P. Langendörfer<br />
Colloquium des Fachbereichs Informatik der Universität<br />
Passau, June 29, <strong>2004</strong>, Germany<br />
(7) Analog Design Challenges in Ultrawide-Band<br />
Technology<br />
B. Dietrich<br />
International Union of Radio Science, Landesausschuss<br />
in der Bundesrepublik Deutschland,<br />
Kleinheubacher Tagung Miltenberg, September<br />
24, <strong>2004</strong>, Germany<br />
(8) Complementary SiGe BiCMOS<br />
B. Heinemann, J. Drews, D. Knoll, R. Kurps,<br />
S. Marschmeyer, H. Rücker, W. Winkler, Y. Yamamoto<br />
SiGe: Materials, Processing, and Devices : The<br />
1 st International Symposium, Honolulu, October<br />
03-08, <strong>2004</strong>, Hawaii, USA<br />
(9) BiCMOS Integration of High-Speed<br />
SiGe:C HBTs<br />
B. Heinemann, H. Rücker<br />
Workshop Advances in Modeling and Simulation<br />
of Semiconductor Devices, Berlin, July 12-16,<br />
<strong>2004</strong>, Germany<br />
(10) Silicon-based Light Emission After Ion Implantation:<br />
Role of Defects and of Crystalline<br />
Perfection<br />
M. Kittler<br />
10 th Internat. Conf. on “Extended Defects in<br />
Semiconductors” EDS <strong>2004</strong>, Moscow, September<br />
<strong>2004</strong>, Russia<br />
(11) Si-basierte Lichtemitter für die On-chip-<br />
Datenübertragung<br />
M. Kittler<br />
FhG Inst. für Photonische Mikrosysteme, Dresden,<br />
October 7, <strong>2004</strong>, Germany<br />
(12) Energy Effi cient Middleware Design in Support<br />
of User Privacy<br />
P. Langendörfer<br />
Panel Discussion at 4 th Workshop on Applications<br />
and Services in Wireless Networks, Boston,<br />
August 09-11, <strong>2004</strong>, USA
(13) PLASMA: A Location-, Privacy- and Energyaware<br />
Middleware Platform<br />
P. Langendörfer<br />
North Eastern University, Boston, August 12,<br />
<strong>2004</strong>, USA<br />
(14) Are There Alternatives to Silicon Based Technology<br />
W. Mehr<br />
EMRS <strong>2004</strong> Spring Meeting Strasbourg, May 26,<br />
<strong>2004</strong>, France<br />
(15) Mikroelektronik – der große Schritt in<br />
kleinste Welten<br />
W. Mehr<br />
Tag der Wissenschaft an der Europa-Universität<br />
Frankfurt (Oder), November 10, <strong>2004</strong>, Germany<br />
(16) Alternative SOI-Strukturen<br />
H.-J. Müssig<br />
Siltronic AG Burghausen, March 25, <strong>2004</strong>,<br />
Germany<br />
(17) Neue Materialien in der Mikroelektronik –<br />
Trends und Anforderungen<br />
H.-J. Müssig<br />
Institut für Ionenstrahlphysik und Materialforschung<br />
Forschungszentrum Rossendorf, March<br />
29, <strong>2004</strong>, Germany<br />
(18) Welche Rolle spielen neue Materialien in<br />
der Mikroelektronik?<br />
H.-J. Müssig<br />
Tag der offenen Tür im <strong>IHP</strong>, Frankfurt (Oder),<br />
September 04, <strong>2004</strong>, Germany<br />
(19) Atomically Controlled Impurity Doping in<br />
Si-Based CVD<br />
J. Murota, M. Sakuraba, B. Tillack<br />
MRS Spring Meeting <strong>2004</strong>, San Francisco, April<br />
12-16, <strong>2004</strong>, USA<br />
(20) <strong>IHP</strong> – Institut für innovative Mikroelektronik<br />
H. Richter<br />
Hochschulinformationstag der TFH Wildau, May 7,<br />
<strong>2004</strong>, Germany<br />
Eingeladene Vorträge Invited Presentations<br />
(21) Defect Engineering und Wafer Design in der<br />
Siliziumtechnologie<br />
H. Richter<br />
Freiburger Materialforschungszentrum, Freiburg,<br />
July 9, <strong>2004</strong>, Germany<br />
(22) Si Crystal Growth and Defect Engenieering<br />
H. Richter<br />
The 4 th Int. Symp. On Advanced Science and<br />
Technology of Silicon Materials, Kona, Hawaii,<br />
November 22-26, <strong>2004</strong>, USA<br />
(23) SiGe HBT Design for High-Frequency Applications<br />
H. Rücker, B. Heinemann, R. Barth, D. Knoll,<br />
P. Schley, R. Scholz, B. Tillack, W. Winkler<br />
2 nd ISTDM <strong>2004</strong>, Frankfurt (Oder), May 16-19,<br />
<strong>2004</strong>, Germany<br />
(24) Advances in SiGe HBT Technology in Europe<br />
H. Rücker, W. Winkler<br />
Compound Semiconductor IC Symposium,<br />
Monterey, October 23-28, <strong>2004</strong>, USA<br />
(25) A Comparative SR-GIXRD, STM and LEED Study<br />
of the Structural Properties of Pr 2 O 3 Epilayers<br />
on Si(001) and Si(111)<br />
T. Schröder, H.-J. Müssig<br />
Hahn Meitner Institute Berlin, April <strong>2004</strong>, Germany<br />
(26) Modern Synchrotron Radiation Grazing Incidence<br />
Diffraction Studies: The Example<br />
of Epitaxial Pr 2 O 3 Layers on Si(001) and<br />
Si(111)<br />
T. Schröder, T.L. Lee, L. Libralesso, J. Zegenhagen,<br />
C. Wenger, P. Zaumseil, H.-J. Müssig<br />
Ecole Centrale de Lyon, Laboratory of Electronical<br />
Engineering, Lyon, July <strong>2004</strong>, France<br />
(27) Atomic Level Control of SiGe Epitaxy and<br />
Doping<br />
B. Tillack<br />
University of Hannover, Institute for Semiconductor<br />
Devices and Electronic Materials, July 8,<br />
<strong>2004</strong>, Germany<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 135
Vorträge Presentations<br />
(28) High-Performance, Low-Cost SiGe:C BiCMOS<br />
Technology<br />
B. Tillack, D. Knoll, B. Heinemann, K.-E. Ehwald,<br />
H. Rücker, R. Barth, P. Schley, W. Winkler<br />
Semicon Europe, Munich, April 20-22, <strong>2004</strong>,<br />
Germany<br />
(29) High-Performance, Low-Cost SiGe:C BiCMOS<br />
Technology<br />
B. Tillack, D. Knoll, B. Heinemann, K.-E. Ehwald,<br />
H. Rücker, R. Barth, P. Schley, W. Winkler<br />
STS Session: SiGe/SOI/Strained Si: From<br />
Growth to Device Properties, International Congress<br />
Center Munich, April 21, <strong>2004</strong>, Germany<br />
(30) Atomic Level Control of SiGe Epitaxy and<br />
Doping<br />
B. Tillack, Y. Yamamoto, J. Murota<br />
SiGe: Materials, Processing, and Devices: The<br />
1 st International Symposium, Honolulu, October<br />
03-08, <strong>2004</strong>, Hawaii, USA<br />
(31) Application of SiGe:C BiCMOS to Wireless<br />
and Radar<br />
W. Winkler, B. Heinemann, D. Knoll<br />
European Gallium Arsenide and other Compound<br />
Semiconductors Application Symposium, Amsterdam,<br />
October 11-12, <strong>2004</strong>, The Netherlands<br />
(32) High Resolution X-Ray Characterization of<br />
SiGe:C Structures for High Frequency <strong>Microelectronics</strong><br />
Applications<br />
P. Zaumseil<br />
HREDAMM, Zakopane, June 13-17, <strong>2004</strong>, Poland<br />
Vorträge<br />
Presentations<br />
(1) Nitrogen in Thin Silicon Wafers Determined<br />
by Infrared Spectroscopy<br />
V.D. Akhmetov, O. Lysytskiy, H. Richter<br />
9 th Augustusburg Conference of Advanced<br />
Science, Das Silicium-Zeitalter: Silicium für Mikroelektronik,<br />
Photvolatik und Photonik, Augustusburg,<br />
September 23-25, <strong>2004</strong>, Germany<br />
136<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
(2) Carbon and Boron in Heavily Doped SiGe:C/Si<br />
Epilayers Studied by FTIR<br />
V.D. Akhmetov, O. Lysytskiy, Y. Yamamoto,<br />
H. Richter<br />
SiGe: Materials, Processing, and Devices: The<br />
1 st International Symposium, Honolulu, October<br />
03-08, <strong>2004</strong> Hawaii, USA<br />
(3) Silicon-based Light Emission after Ion Implantation<br />
T. Arguirov, M. Kittler, W. Seifert, A. Fischer<br />
9 th Augustusburg Conference of Advanced<br />
Science, Das Silicium-Zeitalter: Silicium für<br />
Mikroelektronik, Photvolatik und Photonik, Augustusburg,<br />
September 23-25, <strong>2004</strong>, Germany<br />
(4) Bestimmung der optischen Eigenschaften<br />
des Fotoresists für die Fotolithographie-<br />
Wellenlängen durch Swingoptimierung<br />
J. Bauer, U. Haak, G. Drescher<br />
3 rd Workshop Ellipsometrie, Stuttgart, February<br />
23-25, <strong>2004</strong>, Germany<br />
(5) Effects of Various Ci/Ti and Co/TiN Layer<br />
Stacks and the Silicide Rapid Thermal Process<br />
Conditions on Cobalt Silicide Formation<br />
S. Buschbaum, O. Fursenko, D. Bolze, D. Wolansky,<br />
V. Melnik, J. Nieß, W. Lerch<br />
MAM <strong>2004</strong> – Materials for Advanced Metallization,<br />
Brussels, March <strong>2004</strong>, Belgium<br />
(6) Accurate Modeling of SiGe:C HBTs using<br />
Adaptive Neuro-Fuzzy Inference System<br />
A. Chakravorty, R.F. Scholz, B. Senapati,<br />
D. Knoll, A. Fox, R. Garg, C.K. Maiti<br />
2 nd ISTDM <strong>2004</strong>, Frankfurt (Oder), May 16-19,<br />
<strong>2004</strong>, Germany<br />
(7) Electrical Deactivation and Diffusion of<br />
Boron in Preamorphized Ultrashallow Junctions:<br />
Interstitial Transport and F co-implant<br />
Control<br />
B. Colombeau, A.J. Smith, N.E.B. Cowern,<br />
W. Lerch, S. Paul, B.J. Pawlak, F. Christiano,<br />
X. Hebras, D. Bolze, C. Ortiz, P. Pichler<br />
IEDM <strong>2004</strong>, San Francisco, December 13-15,<br />
<strong>2004</strong>, USA
(8) MEDman – Ubiquitous Medical Assistance<br />
J. deMeer<br />
EUREKA MEDEA+ Board Paris, June 03, <strong>2004</strong>,<br />
France<br />
(9) Model-driven Design of the WIN Platform<br />
J. deMeer<br />
17 èmes Journées Internationales «Génie Logiciel &<br />
Ingénierie de Systèmes et leurs Applications», Paris<br />
– November 30 - December 2, <strong>2004</strong>, France<br />
(10) How to Achieve Security by Architecturing<br />
Middleware Supporting Mobile Applications<br />
J. deMeer<br />
IST <strong>2004</strong> Conference – Workshop on Emerging<br />
Security Technology, Den Haag, November 15-<br />
17, <strong>2004</strong>, The Netherlands<br />
(11) Deployment of Sensor Networks to medical<br />
and other Business Application Domains<br />
J. deMeer<br />
IST <strong>2004</strong> Conference – Workshop on Research<br />
Collaboration between Canada and Europe, Den<br />
Haag, November 15-17, <strong>2004</strong>, The Netherlands<br />
(12) High-Level Behavioral SDL Model for the<br />
IEEE 802.15.3 MAC Protocol<br />
D. Dietterle, I. Babanskaja, K. Dombrowski,<br />
R. Kraemer<br />
WWIC <strong>2004</strong>, Frankfurt (Oder), February 05-07,<br />
<strong>2004</strong>, Germany<br />
(13) Mapping of High-Level SDL Models to Effi -<br />
cient Implementations for TinyOS<br />
D. Dietterle, J. Ryman, K. Dombrowski, R. Kraemer<br />
EUROMICRO Symposium on Digital System Design,<br />
Rennes, August 31- September 03, <strong>2004</strong>,<br />
France<br />
(14) Integrated RF LDMOS<br />
K.-E. Ehwald<br />
Workshop High-Performance SiGe:C BiCMOS for<br />
Wireless and Broadband Communication, Frankfurt<br />
(Oder), September 30, <strong>2004</strong>, Germany<br />
(15) A Two Mask Complementary LDMOS Module Integrated<br />
in a 0.25 µm SiGe:C BiCMOS Platform<br />
K.-E. Ehwald, A. Fischer, F. Fürnhammer,<br />
W. Winkler, B. Senapati, R. Barth, D. Bolze,<br />
Vorträge Presentations<br />
B. Heinemann, D. Knoll, H. Rücker, D. Schmidt,<br />
I. Shevchenko, R. Sorge, H.-E Wulf<br />
ESSDERC <strong>2004</strong>, Leuven, September 21-23,<br />
<strong>2004</strong>, Belgium<br />
(16) Bluetooth Indoor Localization System<br />
G. Fischer, B. Dietrich, F. Winkler<br />
1 st Workshop on Positioning, Navigation and<br />
Communication <strong>2004</strong>, Hannover, March 26,<br />
<strong>2004</strong>, Germany<br />
(17) SiGe:C-BiCMOS-Technologie als Basis für<br />
UWB-Transceiver<br />
G. Fischer, B. Heinemann, R. Kraemer<br />
Öffentliche Diskussionssitzung des Fachausschusses<br />
7.2 der ITG zu Ultra Wide Band – Technologien<br />
und mögliche Anwendungen, Kamp-<br />
Lintfort, November 11, <strong>2004</strong>, Germany<br />
(18) Application of Electron Holography in BiCMOS<br />
Technology<br />
P. Formanek, B. Heinemann, M. Kittler, D. Krüger,<br />
R. Kurps, A. Orchowski, A. Ourmazd,<br />
W.-D. Rau, H. Rücker, P. Schwander, B. Tillack,<br />
P. Zaumseil<br />
2 nd ISTDM <strong>2004</strong>, Frankfurt (Oder), May 16-19,<br />
<strong>2004</strong>, Germany<br />
(19) Application of Electron Holography to Extended<br />
Defects: Schottky Barriers at NiSi 2<br />
Precipitates in Silicon<br />
P. Formanek, M. Kittler<br />
10 th Internat. Conf. on Extended Defects in Semiconductors<br />
– EDS <strong>2004</strong>, Moscow, September,<br />
<strong>2004</strong>, Russia<br />
(20) Flash Integration<br />
A. Fox<br />
Workshop High-Performance SiGe:C BiCMOS for<br />
Wireless and Broadband Communication, Frankfurt<br />
(Oder), September 30, <strong>2004</strong>, Germany<br />
(21) Cost-effective Integration of an FN-programmed<br />
Embedded Flash Memory into a<br />
0.25 µm RF-BiCMOS Technology<br />
A. Fox, K.-E. Ehwald, P. Schley, R. Barth,<br />
S. Marschmeyer, V.E. Stikanov, A. Gromovyy,<br />
A Hudyryev<br />
The ICM <strong>2004</strong> International Conference on <strong>Microelectronics</strong>,<br />
Tunis, December 6-8, <strong>2004</strong>, Tunisia<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 137
Vorträge Presentations<br />
(22) Optimization of Anti-refl ective Coating<br />
PECVD SiO x N y for Lithography Application<br />
O. Fursenko, J. Bauer, B. Kuck, A. Penkov<br />
3 rd Workshop Ellipsometrie, Stuttgart, February<br />
23-25, <strong>2004</strong>, Germany<br />
(23) Spectroscopic Ellipsometry for In-Line Process<br />
Control of SiGe:C HBT Technology<br />
O. Fursenko, J. Bauer, P. Zaumseil, D. Krüger,<br />
A. Goryachko, Y. Yamamoto, K. Köpke, B. Tillack<br />
2 nd ISTDM <strong>2004</strong>, Frankfurt (Oder), May 16-19,<br />
<strong>2004</strong>, Germany<br />
(24) A DC – 10 GHz Amplifi er With Digital Offset<br />
Correction<br />
H. Gustat<br />
2 nd ISTDM <strong>2004</strong>, Frankfurt (Oder), May 16-19,<br />
<strong>2004</strong>, Germany<br />
(25) A Fully-Integrated Low-Power Low-Jitter<br />
Clock Synthesizer with 1.2 GHz Tuning Range<br />
in SiGe:C BiCMOS<br />
H. Gustat, F. Herzel, I. Shevchenko<br />
2 nd ISTDM <strong>2004</strong>, Frankfurt (Oder), May 16-19,<br />
<strong>2004</strong>, Germany<br />
(26) A Low-Parasitic Collector Construction for<br />
High-Speed SiGe:C HBTs<br />
B. Heinemann, R. Barth, D. Bolze, J. Drews,<br />
P. Formanek, T. Grabolla, U. Haak, W. Höppner,<br />
D. Knoll, B. Kuck, R. Kurps, K. Köpke,<br />
S. Marschmeyer, H.H. Richter, H. Rücker, P.<br />
Schley, D. Schmidt, W. Winkler, D. Wolansky,<br />
H.-E. Wulf, Y. Yamamoto<br />
IEDM <strong>2004</strong>, San Francisco, December 13-15,<br />
<strong>2004</strong>, USA<br />
(27) High-performance HBT Modules in BiCMOS<br />
B. Heinemann<br />
Workshop High-Performance SiGe:C BiCMOS for<br />
Wireless and Broadband Communication, Frankfurt<br />
(Oder), September 30, <strong>2004</strong>, Germany<br />
(28) Jitter and Phase-Noise in Oscillators and<br />
Phase-locked Loops<br />
F. Herzel, W. Winkler, J. Borngräber<br />
2 nd International Symposium on Fluctuations and<br />
Noise, Maspalomas, Gran Canaria, May 26-28,<br />
<strong>2004</strong>, Spain<br />
138<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
(29) Standardization of Defect Characterization<br />
Technique in Annealed CZ Si<br />
N. Inoue, K. Moriya, K. Kashima, R. Takeda,<br />
V.D. Akhmetov, O. Lysytshiy, K. Nakashima<br />
4 th International Symposium on Advanced Science<br />
and Technology of Silicon Materials, Kona,<br />
November 22-26, <strong>2004</strong>, USA<br />
(30) Oxygen, Nitrogen, Intrinsic Point Defects<br />
and their Interaction in Defect Generation<br />
for Internal Gettering<br />
G. Kissinger<br />
Physikalisches Kolloquium der BTU Cottbus,<br />
November 11, <strong>2004</strong>, Germany<br />
(31) Direct Evidence of Internal Schottky Barriers<br />
at NiSi 2 Precipitates in Si by Electron<br />
Holography<br />
M. Kittler<br />
Gordon Conference on Defects in Semiconductors,<br />
New London, July <strong>2004</strong>, USA<br />
(32) Raumladung an NiSi 2 -Präzipitaten in n-Si<br />
M. Kittler, P. Formanek<br />
Arbeitstreffen ASIS-Verbundprojekt, Grosse Ledder,<br />
April <strong>2004</strong>, Germany<br />
(33) Silicon-based Light Emission after Ion Implantation<br />
M. Kittler, T. Arguirov, A. Fischer, W. Seifert<br />
E-MRS Spring Meeting <strong>2004</strong>, Strasbourg, May<br />
24-28, <strong>2004</strong>, France<br />
(34) Silicon-based Light Emission After Ion Implantation<br />
M. Kittler, T. Arguirov, W. Seifert<br />
Photonics West <strong>2004</strong> – Optoelectronic Integration<br />
on Silicon, San Jose, January 24-29, <strong>2004</strong>, USA<br />
(35) Passivierbarkeit von Cu-kontaminierten Versetzungen<br />
in p-Si<br />
M. Kittler, W. Seifert, O. Vyvenko<br />
Arbeitstreffen ASIS-Verbundprojekt, Grosse Ledder,<br />
April <strong>2004</strong>, Germany<br />
(36) Enhanced Relaxation of SiGe Layers by He<br />
Implantation Supported by In-Situ Ultrasonics<br />
Treatments<br />
V.P. Kladko, V. Melnik, Ya. M. Olikh, V. Popov,<br />
B. Romanjuk, V.M. Yuchimchuk, D. Krüger
2 nd ISTDM <strong>2004</strong>, Frankfurt (Oder), May 16-19,<br />
<strong>2004</strong>, Germany<br />
(37) 5 GHz Transceiver in a SiGe:C BiCMOS Technology<br />
J. Klatt, N. Fiebig<br />
Workshop Analogschaltungen, Freiburg, March<br />
11-12, <strong>2004</strong>, Germany<br />
(38) Polycrystalline Si Solar Cells With DLC Antirefl<br />
ection Coatings<br />
N. Klyui, V. Litovchenko, M. Kittler, W. Seifert<br />
International Conference on Polycrystalline Semiconductors,<br />
POLYSE <strong>2004</strong>, Potsdam, September<br />
<strong>2004</strong>, Germany<br />
(39) A Modular, Low-Cost SiGe:C BiCMOS Process<br />
Featuring High-FT and High-BV CEO<br />
Transistors<br />
D. Knoll, B. Heinemann, R. Barth, K. Blum, J. Borngräber,<br />
J. Drews, K.-E. Ehwald, G. Fischer, A. Fox,<br />
T. Grabolla, U. Haak, W. Höppner, F. Korndörfer,<br />
B. Kuck, S. Marschmeyer, H.H. Richter, H. Rücker,<br />
P. Schley, D. Schmidt, R.F. Scholz, B. Senapati,<br />
B. Tillack, W. Winkler, D. Wolansky, C. Wolf, H.-E.<br />
Wulf, Y. Yamamoto, P. Zaumseil<br />
BCTM Montreal <strong>2004</strong>, September 11-17, <strong>2004</strong>,<br />
Canada<br />
(40) SGB25VD Low Cost BiCMOS Approach<br />
D. Knoll<br />
Workshop High-Performance SiGe:C BiCMOS for<br />
Wireless and Broadband Communication, Frankfurt<br />
(Oder), September 30, <strong>2004</strong>, Germany<br />
(41) Wireless Engine<br />
R. Kraemer<br />
Ringvorlesung Schwerpunkte der Informatik, Humboldt<br />
Universität Bln, January 29, <strong>2004</strong>, Germany<br />
(42) Chip-Entwicklung am <strong>IHP</strong><br />
R. Kraemer<br />
Seminar Technischer Bereich, DESY Zeuthen,<br />
February 24, <strong>2004</strong>, Germany<br />
(43) Der Bluetooth-Koffer: Intelligentes Gepäck<br />
für eine erhöhte Sicherheit<br />
R. Kraemer<br />
Ringvorlesung Das Internet und seine Anwendungen<br />
(III), BTU Cottbus, May 04, <strong>2004</strong>, Germany<br />
Vorträge Presentations<br />
(44) Integrierte drahtlose Systeme und integrierte<br />
Radarsysteme der Zukunft<br />
R. Kraemer<br />
Vortrag zum Tag der offenen Tür im <strong>IHP</strong>, Frankfurt<br />
(Oder), September 04, <strong>2004</strong>, Germany<br />
(45) Remote Operations: A Middleware and Distributed<br />
Systems Architecture for Satellite<br />
On-Board Wireless Communication<br />
R. Kraemer, K. Dombrowski, D. Dietterle, P. Langendörfer,<br />
M. Methfessel<br />
DASIA <strong>2004</strong>, Data Systems in Aerospace, Nice,<br />
June 28-July 01, <strong>2004</strong>, France<br />
(46) GALS Baseband Processor for WLAN<br />
M. Krstic, E. Grass<br />
4 th ACiD-WG Workshop, Turku, June 28-29,<br />
<strong>2004</strong>, Finland<br />
(47) GALSifi cation of IEEE 802.11a Baseband<br />
Processor<br />
M. Krstic, E. Grass<br />
14 th International Conference on PATMOS <strong>2004</strong>,<br />
Santorini, September 15-17, <strong>2004</strong>, Greece<br />
(48) A Location Aware Revocation Approach<br />
D. Kulikowski, P. Langendörfer, K. Piotrowski<br />
Mobile Computing und Medien Kommunikation<br />
im Internet, University of Ulm, September 23,<br />
<strong>2004</strong>, Germany<br />
(49) PLASMADS: Smart Mobiles Meet Intelligent<br />
Environments<br />
P. Langendörfer, H. Maass, T. Falck<br />
4 th Workshop on Applications and Services<br />
in Wireless Networks, Boston, August 09-11,<br />
<strong>2004</strong>, USA<br />
(50) A Combined Synchrotron X-Ray Diffraction<br />
and STM Study of the Structural Properties<br />
of Ultra-Thin Pr 2 O 3 Layers on Si(111)<br />
L. Libralesso, T. Schröder, T.L. Lee, I. Joumard,<br />
J. Zegenhagen, H.-J. Müssig<br />
E-MRS Spring Meeting <strong>2004</strong>, Strasbourg, May<br />
24-28, <strong>2004</strong>, France<br />
(51) Dependence of Structural and Electrical<br />
Properties of Pr and La Oxides on Growth,<br />
Annealing and Storage Conditions<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 139
Vorträge<br />
140<br />
Presentations<br />
G. Lippert, J. Dabrowski, P. Formanek, V. Melnik,<br />
R. Sorge, Ch. Wenger, P. Zaumseil, H.-J. Müssig<br />
16 th International Vacuum Congress, Venice,<br />
June 28 - July 02, <strong>2004</strong>, Italy<br />
(52) Deposition Conditions and Post Treatment<br />
of High-k Praseodymium and Lanthanum<br />
Oxide Dielectrics<br />
G. Lippert, J. Dabrowski, P. Formanek, V. Melnik,<br />
R. Sorge, Ch. Wenger, P. Zaumseil, H.-J. Müssig<br />
206 th Meeting of the Electrochemical Society,<br />
Honolulu, October 03-08, <strong>2004</strong>, Hawaii, USA<br />
(53) Properties of Pr-silicate High-k Dielectrics<br />
Formed by Solid-State Reaction Between Pr<br />
and SiO 2<br />
G. Lupina<br />
Deutscher <strong>MB</strong>E-Workshop, Braunschweig, October<br />
12, <strong>2004</strong>, Germany<br />
(54) Solid State Reaction between Pr and SiO 2<br />
Studied by Photoelectron Spectroscopy and<br />
ab initio Calculations<br />
G. Lupina, J. Dabrowski, P. Formanek, D. Schmeißer,<br />
R. Sorge, C. Wenger, P. Zaumseil, H.-J. Müssig<br />
E-MRS Spring Meeting, Strasbourg, May 24-28,<br />
<strong>2004</strong>, France<br />
(55) A CORDIC Like Processor for Computation<br />
of Arctangent and Absolute Magnitude of a<br />
Vector<br />
K. Maharatna, A. Troya, M. Krstic, E. Grass,<br />
U. Jagdhold<br />
Int. Symposium on Circuits and Systems, ISCAS<br />
<strong>2004</strong>, Vancouver, May 23 - 26, <strong>2004</strong>, Canada<br />
(56) Wann werden die Grenzen der Mikroelektronik<br />
erreicht? – Zukünftige Entwicklungstrends<br />
W. Mehr<br />
Tag der offenen Tür im <strong>IHP</strong>, Frankfurt (Oder),<br />
September 04, <strong>2004</strong>, Germany<br />
(57) TCP/IP Processor for Wireless<br />
M. Methfessel<br />
Workshop High-Performance SiGe:C BiCMOS for<br />
Wireless and Broadband Communication, Frankfurt<br />
(Oder), September 30, <strong>2004</strong>, Germany<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
(58) Thin Dielectric Films Grown by Solid Phase<br />
Reaction of Pr with Thermal SiO 2<br />
H.-J. Müssig, J. Dabrowski, C. Wenger, G. Lupina,<br />
R. Sorge, P. Formanek, P. Zaumseil, D. Schmeißer<br />
MRS Spring Meeting, San Francisco, April 12-16,<br />
<strong>2004</strong>, USA<br />
(59) Moneta: An Anonymity Providing Lightweight<br />
Payment System for Mobile Devices<br />
K. Piotrowski, P. Langendörfer, D. Kulikowski<br />
2 nd GI/IFIP Workshop on Virtual Goods, Ilmenau,<br />
May 27 - 29, <strong>2004</strong>, Germany<br />
(60) Ensuring Anonymity in e-commerce Systems<br />
Using a Hidden Identity Approach: Discussion<br />
of Problems and Solutions<br />
K. Piotrowksi, P. Langendörfer, O. Maye<br />
7 th International Conference on Electronic Commerce<br />
Research, Dallas, June 10-13, <strong>2004</strong>,<br />
USA<br />
(61) Applying Position Prediction as a Means for<br />
Performance-tuning in Location-aware Platforms<br />
A. Post, P. Langendörfer, R. Kraemer<br />
1 st Workshop on Positioning, Navigation and<br />
Communication <strong>2004</strong> (WPNC’04), Hannover,<br />
March 26, <strong>2004</strong>, Germany<br />
(62) Mechanische Eigenschaften von ultradünnen<br />
Si-, GeSi- und GeSi:C-<strong>MB</strong>E Schichten auf<br />
(100) Siliziumsubstraten<br />
R. Ries, A. Richter, B. Tillack<br />
5. Workshop Rasterkraftmikroskopie in der<br />
Werkstoffwissenschaft, Dresden, February 26-<br />
27, <strong>2004</strong>, Germany<br />
(63) Integration of High-Performance SiGe:C<br />
HBTs with Thin-Film SOI CMOS<br />
H. Rücker, B. Heinemann, R. Barth, D. Bolze,<br />
J. Drews, O. Fursenko, T. Grabolla, U. Haak,<br />
W. Höppner, D. Knoll, S. Marschmeyer, N. Mohapatra,<br />
H.H. Richter, P. Schley, D. Schmidt,<br />
B. Tillack, G. Weidner, D. Wolansky, H.-E. Wulf,<br />
Y. Yamamoto<br />
IEDM <strong>2004</strong>, San Francisco, December 13-15,<br />
<strong>2004</strong>, USA
(64) The System Behavioral Model of IEEE 802.15.3<br />
Mac Protocol – Design and Profi ling<br />
J. Ryman, D. Dietterle, K. Dombrowski, P. Bubacz<br />
2 nd International Workshop on Discrete-Event<br />
System Design, DESDes ‘04, Dychow, September<br />
15-17, <strong>2004</strong>, Poland<br />
(65) A 1 GHz AGC Amplifi er in BiCMOS With 3 µm<br />
Settling-Time for 802.11a WLAN<br />
K. Schmalz<br />
IEEE Norchip <strong>2004</strong>, Oslo, November 8-9, <strong>2004</strong>,<br />
Norway<br />
(66) High Reactivity of Pr on Oxide Covered<br />
4H-SiC<br />
D. Schmeißer, G. Lupina, H.-J. Müssig<br />
E-MRS Spring Meeting <strong>2004</strong>, Strasbourg, May<br />
24-28, <strong>2004</strong>, France<br />
(67) Pr 4 f Occupancy and VB/CB Band Offsets of<br />
Pr 2 O 3 at the Interface to Si (001) and SiC<br />
(0001) Surfaces<br />
D. Schmeißer, H.-J. Müssig<br />
E-MRS Spring Meeting <strong>2004</strong>, Strasbourg, May<br />
24-28, <strong>2004</strong>, France<br />
(68) Design Kit and MPW Service<br />
R.F. Scholz<br />
Workshop High-Performance SiGe:C BiCMOS for<br />
Wireless and Broadband Communication, Frankfurt<br />
(Oder), September 30, <strong>2004</strong>, Germany<br />
(69) Advanced Technique for Broadband on-Wafer<br />
RF Device Characterization<br />
R.F. Scholz, F. Korndörfer, B. Senapati, A. Rumiantsev<br />
63 rd ARFTG Conference, On Wafer Characterization,<br />
Ft. Worth, June 11, <strong>2004</strong>, USA<br />
(70) The Heteroepitaxial Systems Pr 2 O 3 /Si(001)<br />
and Pr 2 O 3 /Si(111): Structure and Strain in<br />
Rare Earth Oxide Epilayers on Si<br />
T. Schröder, T.L. Lee, L. Libralesso, C. Wenger,<br />
P. Zaumseil, H.-J. Müssig<br />
GDR Meeting, Grenoble, June <strong>2004</strong>, France<br />
Vorträge<br />
Presentations<br />
(71) Structure and Thickness-Dependent Lattice<br />
Parameters of Ultrathin Epitaxial Pr 2 O 3 Films<br />
on Si(001) Studied by SR-GIXRD<br />
T. Schröder, T.-L. Lee, J. Zegenhagen, C. Wenger,<br />
P. Zaumseil, H.-J. Müssig<br />
Frühjahrstagung der Deutschen Physikalischen<br />
Gesellschaft, Regensburg, March 08-12, <strong>2004</strong>,<br />
Germany<br />
(72) A Grazing Incidence X-Ray Diffraction Study<br />
of Ultra-Thin Praseodymium Oxide Layers<br />
on Si (001): From Pseudomorphism to Bulk<br />
Behavior<br />
T. Schröder, T.L. Lee, L. Libralesso, J. Zegenhagen,<br />
Ch. Wenger, P. Zaumseil, H.-J. Müssig<br />
E-MRS Spring Meeting <strong>2004</strong>, Strasbourg, May<br />
24-28, <strong>2004</strong>, France<br />
(73) Defekte und Rekombinationseigenschaften<br />
in n-leitendem HEM-Material<br />
W. Seifert, M. Kittler, G. Jia<br />
Arbeitstreffen ASIS-Verbundprojekt, Ochsenfurt,<br />
September <strong>2004</strong>, Germany<br />
(74) Modelling and RF Characterisation<br />
B. Senapati<br />
Workshop High-Performance SiGe:C BiCMOS for<br />
Wireless and Broadband Communication, Frankfurt<br />
(Oder), September 30, <strong>2004</strong>, Germany<br />
(75) Macro Model of Power RF LDMOSFET<br />
B. Senapati, K.-E. Ehwald, I. Shevchenko,<br />
R. Scholz, F. Fürnhammer<br />
International Conference on Communications,<br />
Devices and Intelligent Systems, Kolkata, January<br />
8-10, <strong>2004</strong>, India<br />
(76) VBIC Model for SiGe:C Bipolar Technology<br />
B. Senapati, R.F. Scholz, D. Knoll, B. Heinemann,<br />
A. Chakravorty<br />
11 th International MIXDES Conference, Szczecin,<br />
June 24-26, <strong>2004</strong>, Poland<br />
(77) Self-Consistent Characterization of Gate Controlled<br />
Diodes for CMOS Technology Monitoring<br />
R. Sorge, P. Schley, K.-E. Ehwald<br />
ESSDERC <strong>2004</strong>, Leuven, September 21-23,<br />
<strong>2004</strong>, Belgium<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 141
Vorträge Presentations<br />
(78) Modular Processor: A Flexible Library of<br />
ASIC Modules<br />
Z. Stamenkovic, G. Panic, U. Jagdhold, H. Frankenfeldt,<br />
K. Tittelbach-Helmrich, G. Schoof,<br />
R. Kraemer<br />
IASTED International Conference on Applied<br />
Simulation and Modelling – ASM <strong>2004</strong>, Rhodes,<br />
June 28-30, <strong>2004</strong>, Greece<br />
(79) Atomic Layer Processing for Steep and Shallow<br />
Doping Profi les<br />
B. Tillack, D. Bolze, R. Kurps, D. Wolansky,<br />
Y. Yamamoto, W. Mehr<br />
Workshop RTP & Blitzlampen-Temperverfahren,<br />
Rossendorf, October 21, <strong>2004</strong>, Germany<br />
(80) Advances in SiGe HBT Technology in Europe<br />
B. Tillack, D. Knoll, B. Heinemann, K.-E. Ehwald, H.<br />
Rücker, R. Barth, P. Schley, W. Winkler, W. Mehr<br />
Das Silicium-Zeitalter: Silicium für Mikroelektronik,<br />
Photovoltaik und Photonik, Augustusburg,<br />
September 23-25, <strong>2004</strong>, Germany<br />
(81) Recombination Activity and Electrical Levels<br />
of Clean and Copper Contaminated Dislocations<br />
in p-type Si<br />
O.F. Vyvenko, M. Kittler, W. Seifert, M.V. Trushin<br />
10 th Internat. Conf. on Extended Defects in Semiconductors<br />
EDS <strong>2004</strong>, Moscow, September<br />
<strong>2004</strong>, Russia<br />
(82) First Investigations of MIM Capacitors Using<br />
Pr 2 O 3 Dielectrics<br />
C. Wenger<br />
Frühjahrstagung der DPG, Regensburg, March<br />
11, <strong>2004</strong>, Germany<br />
(83) Electrical Properties of Praseodymium-Silicate<br />
Films for High-K Gate Applications<br />
C. Wenger, J. Dabrowski, G. Lupina, P. Zaumseil,<br />
R. Sorge, P. Formanek, G. Lippert, H.-J. Müssig<br />
Workshop of Dielectrics in <strong>Microelectronics</strong><br />
<strong>2004</strong>, Cork, June 28-30, <strong>2004</strong>, Ireland<br />
(84) First Investigation of MIM Capacitors Using<br />
Pr 2 O 3 Dielectrics<br />
C. Wenger, J. Dabrowski, P. Zaumseil, R. Sorge,<br />
P. Formanek, G. Lippert, H.-J. Müssig<br />
E-MRS Spring Meeting, Strasbourg, May 24-28,<br />
<strong>2004</strong>, France<br />
142<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
(85) High-Performance RF Circuits<br />
W. Winkler<br />
Workshop High-Performance SiGe:C BiCMOS for<br />
Wireless and Broadband Communication, Frankfurt<br />
(Oder), September 30, <strong>2004</strong>, Germany<br />
(86) DüseF: Bedeutung und Stand der Forschung<br />
im <strong>IHP</strong><br />
W. Winkler<br />
Presentation for Project Preparation „Drahtlose<br />
Übertragung von Sensordaten im Fahrzeug<br />
(DüseF)“, Stuttgart Gerlingen, January 26, <strong>2004</strong>,<br />
Germany<br />
(87) Millimeterwellen-Schaltungen: Bedeutung<br />
und Stand der Forschung im <strong>IHP</strong><br />
W. Winkler<br />
Workshop MMIC-Technologie in der KFZ-Radarsensorik,<br />
Wolfsburg, January 30, <strong>2004</strong>, Germany<br />
(88) Frontend-Anforderungen für 77 GHz UMRR<br />
Sensor<br />
W. Winkler<br />
Workshop MMIC-Technologie in der KFZ-Radarsensorik,<br />
Wolfsburg, February 20, <strong>2004</strong>, Germany<br />
(89) Vorstellung der <strong>IHP</strong> Technologie und der <strong>IHP</strong><br />
Schaltungstechnik<br />
W. Winkler<br />
Meeting „Radarsysteme für die Automobilindustrie“,<br />
Ilmenau, April 4, <strong>2004</strong>, Germany<br />
(90) Vorstellung des <strong>IHP</strong> und Grundschaltungen<br />
für 60 und 76 GHz Radarsysteme<br />
W. Winkler<br />
Treffen zur Zusammenarbeit zwischen TU-Ilmenau<br />
(TUI), DaimlerChrysler (DC), MEDAV und <strong>IHP</strong>,<br />
Ilmenau, April 30, <strong>2004</strong>, Germany<br />
(91) Kostengünstige MMICs für 77 GHz mit der<br />
<strong>IHP</strong> SiGe:C Technologie<br />
W. Winkler<br />
Workshop „MMIC-Technologie in der KFZ-Radarsensorik“,<br />
Wolfsburg, June 16, <strong>2004</strong>, Germany<br />
(92) Cost-Effective MMICs for 77 GHz Automotive<br />
Radar with <strong>IHP</strong> SiGe:C Technology<br />
W. Winkler<br />
Workshop „MMIC-Technologie in der KFZ-Radarsensorik“,<br />
Wolfsburg, Septrmber 28, <strong>2004</strong>, Germany
(93) LC-Oscillator for 94 GHz Automotive Radar<br />
System Fabricated in SiGe:C BiCMOS Technology<br />
W. Winkler, J. Borngräber<br />
European Gallium Arsenide and other Compound<br />
Semiconductors Application Symposium, Amsterdam,<br />
October 11-12, <strong>2004</strong>, The Netherlands<br />
(94) A 117 GHz LC-Oscillator in SiGe:C BiCMOS<br />
Technology<br />
W. Winkler, J. Borngräber, B. Heinemann<br />
2 nd ISTDM <strong>2004</strong>, Frankfurt (Oder), May 16-19,<br />
<strong>2004</strong>, Germany<br />
(95) LC-Oscillators Above 100 GHz in Silicon-<br />
Based Technology<br />
W. Winkler, J. Borngräber, B. Heinemann<br />
ESSCIRC <strong>2004</strong> – European Solid-State Circuits<br />
Conference, Leuven, September 20-23, <strong>2004</strong>,<br />
Belgium<br />
(96) High-Frequency Low-Noise Amplifi ers and<br />
Low-Jitter Oscillators in SiGe:C BiCMOS Technology<br />
W. Winkler, J. Borngräber, F. Herzel, B. Heinemann,<br />
R. Scholz<br />
2 nd International Symposium on Fluctuations and<br />
Noise, Maspalomas, Gran Canaria, May 26-28,<br />
<strong>2004</strong>, Spain<br />
(97) 60 GHz Transceiver Circuits in SiGe:C BiCMOS<br />
Technology<br />
W. Winkler, J. Borngräber, F. Herzel, H. Gustat,<br />
B. Heinemann, F. Korndörfer<br />
ESSCIRC <strong>2004</strong> – European Solid-State Circuits<br />
Conference, Leuven, September 20-23, <strong>2004</strong>,<br />
Belgium<br />
(98) Reliability and Process Qualifi cation<br />
P. Zaumseil<br />
Workshop High-Performance SiGe:C BiCMOS for<br />
Wireless and Broadband Communication, Frankfurt<br />
(Oder), September 30, <strong>2004</strong>, Germany<br />
(99) A Complex X-Ray Characterization of Epitaxially<br />
Grown High-K Gate Dielectrics<br />
P. Zaumseil, T. Schröder<br />
XTOP <strong>2004</strong>, Prague, September 07-10, <strong>2004</strong>,<br />
Czech Republic<br />
Berichte <strong>Report</strong>s<br />
Berichte<br />
<strong>Report</strong>s<br />
(1) SSMSC – Smart Secure Mass Storage Cards<br />
E. Charbonnier, J. deMeer<br />
Project Full Proposal to EU EUREKA/MEDEA+,<br />
23.09.<strong>2004</strong><br />
(2) Ab Initio Investigation of Pr-related High-K<br />
Dielectrics for CMOS Technology Development<br />
J. Dabrowski<br />
Project HFO06: Application for Computing Time<br />
on IBM Regatta and Cray, Progress <strong>Report</strong><br />
07.2003-04.<strong>2004</strong><br />
(3) Verbundprojekt „Wireless Internet-Zellular“<br />
Machbarkeitsstudie: Applikationen und Spezifi<br />
kation ihrer zugehörigen Demonstratoren<br />
C. Deist, O. Maye et al., <strong>2004</strong><br />
(4) On Designing Consistent Middleware Platforms,<br />
Version 0.2<br />
J. deMeer<br />
Contribution to Work Item AP2.1 (Architectural<br />
Principles) of the WINcell Project, 30.08.<strong>2004</strong><br />
(5) Begriffsdefi nitionen für AP2.1 „Tragfähige<br />
Architektur“<br />
J. deMeer<br />
Contribution to Work Item AP2.1 (Architectural<br />
Principles) of the WINcell Project, 06.08.<strong>2004</strong><br />
(6) RESIDUAL – Refl ective System Design for<br />
Human Life Assistancy<br />
J. deMeer<br />
EU STREP Proposal on FET open Call FP6-2002-<br />
IST-C, 17.12.<strong>2004</strong><br />
(7) Zwischenbericht<br />
K. Dombrowski<br />
BASUMA Projekt, <strong>2004</strong><br />
(8) Zwischenbericht Gesamtprojekt<br />
K. Dombrowski<br />
BASUMA Projekt, <strong>2004</strong><br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 143
Berichte <strong>Report</strong>s<br />
(9) Effi cient Implementations of Cryptographic<br />
Routines – A Review and Performance Analysis<br />
of Various Approaches<br />
Z. Dyka, F. Vater, O. Maye, P. Langendörfer,<br />
R. Kraemer<br />
Technical <strong>Report</strong> 01/04, BTU Cottbus, <strong>2004</strong><br />
(10) 4 th Periodic <strong>Report</strong> and Final <strong>Report</strong> HERCU-<br />
LAS Project<br />
P. Formanek, M. Kittler, <strong>2004</strong><br />
(11) Single-Chip Lösung für bandbreiteneffi -<br />
zientes drahtloses Kommunikationssystem<br />
E. Grass, K. Tittelbach-Helmrich, H. Frankenfeldt,<br />
N. Fiebig<br />
B<strong>MB</strong>F-Projekt 01 BU 054, Schlussbericht: On<br />
the Single-Chip Implementation of a Hiperlan/2<br />
and IEEE 802.11a Capable Modem, <strong>2004</strong><br />
(12) Abschlussbericht<br />
E. Grass, N. Fiebig, K. Tittelbach-Helmrich<br />
IBMS2 (B<strong>MB</strong>F) Single-Chip Lösung für bandbreiteneffizientes<br />
drahtloses Kommunikationssystem,<br />
<strong>2004</strong><br />
(13) Zwischenbericht 1<br />
E. Grass, F. Herzel, M. Piz, J.P. Ebert<br />
WIGWAM (B<strong>MB</strong>F) Schichtenübergreifender Entwurf<br />
eines Höchstgeschwindigkeits-WLAN: Konzept,<br />
SoC-Implementierung und Demonstrator,<br />
im Rahmen der Leitinnovation „Mobile Internet“,<br />
16.02.<strong>2004</strong><br />
(14) Zwischenbericht 2<br />
E. Grass, F. Herzel, M. Piz, J.P. Ebert<br />
WIGWAM (B<strong>MB</strong>F) Schichtenübergreifender Entwurf<br />
eines Höchstgeschwindigkeits-WLAN: Konzept,<br />
SoC-Implementierung und Demonstrator,<br />
im Rahmen der Leitinnovation „Mobile Internet“,<br />
12.08.<strong>2004</strong><br />
(15) Final <strong>Report</strong> to Siltronic AG (contractual period<br />
March 15 – June 30, <strong>2004</strong>)<br />
G. Kissinger, <strong>2004</strong><br />
(16) Final <strong>Report</strong> to Siltronic AG (contractual period<br />
July 01 – December 31, <strong>2004</strong>)<br />
G. Kissinger, <strong>2004</strong><br />
144<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
(17) Raumladung an NiSi 2 -Präzipitaten in n-Si<br />
M. Kittler, P. Formanek<br />
Arbeitstreffen ASIS-Verbundprojekt, Grosse Ledder,<br />
April <strong>2004</strong><br />
(18) Passivierbarkeit von Cu-kontaminierten Versetzungen<br />
in p-Si<br />
M. Kittler, W. Seifert, O. Vyvenko<br />
Arbeitstreffen ASIS-Verbundprojekt, Grosse Ledder,<br />
April <strong>2004</strong><br />
(19) Ergebnisbericht Wireless Internet – zellular<br />
B. Lehmann, P. Langendörfer et al., <strong>2004</strong><br />
(20) Design of PAL and Voice Optimisation for WLAN<br />
A. Lunn, K. Tittelbach-Helmrich, F.M. Krause,<br />
T. Becker, B. Cheetham, M. Kuhn, M. Methfessel,<br />
A. Ettafagh, M. Secall, M. Spegel<br />
WinDECT Deliverable D3.2, <strong>2004</strong><br />
(21) Shallow-Trench RIE – Verfahrensentwicklung<br />
H. H. Richter, S. Marschmeyer, S. Günther, H. Silz<br />
Abschlussbericht zum Forschungs- und Entwicklungsvertrag<br />
vom 17.06.<strong>2004</strong> zwischen<br />
ZMD Dresden GmbH & Co. KG und <strong>IHP</strong> Frankfurt<br />
(Oder) GmbH<br />
(22) Solid State Reaction Between Pr and SiO 2<br />
Studied by Photoelectron Spectroscopy<br />
D. Schmeißer, G. Lupina, H.-J. Müssig<br />
BESSY II – Status <strong>Report</strong>, <strong>2004</strong><br />
(23) Defekte und Rekombinationseigenschaften in<br />
n-leitendem HEM-Material, Zwischenbericht<br />
W. Seifert, M. Kittler, G. Jia<br />
Arbeitstreffen ASIS-Verbundprojekt, Ochsenfurt,<br />
Sept. <strong>2004</strong><br />
(24) 506746 – WINDECT STP D2.2 Technical Specifi<br />
cation of 173, Demonstration System<br />
M. Spegel, A. Lunn, F.-M. Krause, T. Wellhausen,<br />
K. Tittelbach-Helmrich, P. Reinhardt,<br />
B. Cheetham<br />
WINDECT Wireless LAN with Integration of<br />
Professional-Quality DECT Telephony <strong>Report</strong>,<br />
<strong>2004</strong>
Monographien<br />
Monographs<br />
(1) Materials Science in Semiconductor Processing<br />
, Vol. 7 (<strong>2004</strong>)<br />
Papers presented at the E-MRS <strong>2004</strong> Spring<br />
Meeting Symposium C: New Materials in Future<br />
Silicon Technology<br />
Eds. J. Dabrowski, H.-J. Müssig<br />
Elsevier, <strong>2004</strong><br />
(2) Predictive Simulation of Semiconductor Processing<br />
– Status and Challenges<br />
Eds. J. Dabrowski, E.R. Weber<br />
Springer Series in Materials Science, Berlin,<br />
Springer Verlag <strong>2004</strong><br />
(3) Energy-Effi cient Communication in Ad Hoc<br />
Wireless Local Area Networks<br />
J.P. Ebert<br />
Dissertation, TU Berlin, <strong>2004</strong><br />
(4) TEM-Holographie an Bauelementestrukturen<br />
der Mikroelektronik<br />
P. Formanek<br />
Dissertation, BTU Cottbus, <strong>2004</strong><br />
(5) SiGe: Materials, Processing, and Devices:<br />
Proceedings of the 1 st International Symposium<br />
Eds: D. Harame, J. Boquet, J. Cressler,<br />
D. Houghton, H. Iwai, T.-J. King, G. Masini,<br />
J. Murota, K. Rim, B. Tillack<br />
Proceedings Electrochemical Society Vol.<br />
<strong>2004</strong>-07 (<strong>2004</strong>)<br />
(6) Integration von Standard-AAA-Technologien<br />
in eine Plattform für ortssensitive Dienste<br />
unter besonderer Berücksichtigung mobiler<br />
Endgeräte<br />
K. Jendrusch<br />
Diplomarbeit, TFH Wildau, <strong>2004</strong><br />
(7) Das Silicium-Zeitalter: Silicium für Mikroelektronik,<br />
Photovoltaik und Photonik<br />
Ed. M. Kittler<br />
Abstracts, 9 th Augustusburg Conference of<br />
Advanced Science, Augustusburg (Sachsen),<br />
23.-25. Sept. <strong>2004</strong><br />
Monographien Monographs<br />
(8) Entwurf und Implementierung einer DSPbasierten<br />
IEEE 802.11a-Synchronisationseinheit<br />
R. Kothe<br />
Diplomarbeit, BTU Cottbus, <strong>2004</strong><br />
(9) Providing Trust in E-commerce Systems<br />
(Especially in Wired/Wireless Networks)<br />
D. Kulikowski<br />
Diplomarbeit, University Zielona Gora, <strong>2004</strong><br />
(10) Wired/Wireless Internet Communications<br />
P. Langendörfer, M. Liu, I. Matta; V. Tsaoussidis<br />
(Eds.)<br />
2 nd International Conference WWIC <strong>2004</strong>, Frankfurt<br />
(Oder), Proceedings, Springer Verl., <strong>2004</strong>.-<br />
(LNCS; 2957)<br />
(11) Towards Privacy Negotiation for Internet<br />
Services: Design and Prototyping of Basic<br />
Concepts<br />
M. Maaser<br />
Diplomarbeit, BTU Cottbus, <strong>2004</strong><br />
(12) Proceedings of the First International SiGe<br />
Technology and Devices Meeting (ISTDM<br />
2003): From Materials and Process Technology<br />
to Device and Circuit Technology, Nagoya<br />
University Symposion, Japan. Jan. 15-17, 2003<br />
ed. by J. Murota, B. Tillack, M. Caymax,<br />
J. Sturm, Y. Yasuda, S. Zaima<br />
Applied Surface Science 224 (1-4) (<strong>2004</strong>)<br />
(13) Design and Implementation of an Off-Line<br />
E-Cash Scheme<br />
K. Piotrowski<br />
Diplomarbeit, University of Zielona Góra, Faculty<br />
of Electrical Engineering, Computer Science<br />
and Telecommunications, <strong>2004</strong><br />
(14) Evaluation of Performance Impacts of Early<br />
Handoff Detection for PLASMA Event and<br />
Handoff Processing<br />
A. Post<br />
Bachelorarbeit, BTU Cottbus, <strong>2004</strong><br />
(15) Gettering and Defect Engineering in Semiconductor<br />
Technology – The 10 th GADEST<br />
Conference<br />
Eds. H. Richter, M. Kittler<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 145
Patente Patents<br />
146<br />
Proc. GADEST 2003, in Solid State Phenomena,<br />
95-96, <strong>2004</strong>, 682 pages<br />
(16) Design and Profi ling of the SystemC Behavioral<br />
Model of the MAC Protocol According to<br />
IEEE 802.15.3<br />
J. Ryman<br />
Diplomarbeit, University Zielona Gora, <strong>2004</strong><br />
(17) Design, Simulation und Evaluierung eines<br />
5 GHz-Low-IF-Receivers<br />
S. Seelig<br />
Diplomarbeit, Universität der Bundeswehr, <strong>2004</strong><br />
(18) Synchronization and Channel Estimation in<br />
OFDM: Algorithms for Effi cient Implementation<br />
of WLAN Systems<br />
A. Troya<br />
Dissertation, BTU Cottbus, <strong>2004</strong><br />
Patente<br />
Patents<br />
(1) Verfahren und Vorrichtung zur Niedertemperaturepitaxie<br />
auf einer Vielzahl von Halbleitersubstraten<br />
T. Grabolla, B. Tillack<br />
<strong>IHP</strong>.256.04, DE-Patentanmeldung am 10.05.04<br />
AZ: 10 <strong>2004</strong> 024 207.0<br />
(2) Schieberegister mit linearer Rückkopplung<br />
H. Gustat<br />
<strong>IHP</strong>.254.03, DE-Patentanmeldung am 28.01.04,<br />
AZ: 10 <strong>2004</strong> 005 243.3<br />
(3) Vertikaler Bipolartransistor<br />
B. Heinemann<br />
<strong>IHP</strong>.263.04 DE-Patentanmeldung am 11.12.04,<br />
AZ: 10 <strong>2004</strong> 061 327.3<br />
(4) Silizium-basierter Lichtemitter<br />
M. Kittler, A. Fischer, T. Arguirov, W. Seifert<br />
<strong>IHP</strong>.258.04, DE-Patentanmeldung am 14.05.04,<br />
AZ: 10 <strong>2004</strong> 025 099.5<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
(5) Kondensatorstruktur<br />
G. Lippert<br />
<strong>IHP</strong>.257.04, DE-Patentanmeldung am 04.05.04,<br />
AZ: 10 <strong>2004</strong> 023 135.4<br />
(6) Halbleiterbauelement mit Gegensignalschaltung<br />
zum Vermeiden von Übersprechen elektronischer<br />
Baugruppen<br />
G. Lippert<br />
<strong>IHP</strong>.251.03, DE-Patentanmeldung am 08.04.04,<br />
AZ: 10 <strong>2004</strong> 018 448.8<br />
(7) Verfahren zur Herstellung einer Lanthanoidsilikatschicht,<br />
insbesondere einer Praseodymsilikatschicht<br />
H.-J. Müssig<br />
<strong>IHP</strong>.259.04, DE-Patentanmeldung am 30.03.04,<br />
AZ: 10 <strong>2004</strong> 016 320.0<br />
(8) Ätzverfahren für MOS-Schichtstrukturen mit<br />
praseodymoxidhaltigem Dielektrikum<br />
H.-J. Müssig<br />
<strong>IHP</strong>.261.04, DE-Patentanmeldung am 04.10.04,<br />
AZ: 04 090 382.5<br />
(9) Method and Apparatus for the Determination<br />
of the Concentration of Impurities in<br />
a Wafer<br />
H. Richter, V.D. Akhmetov, O. Lysytskiy<br />
<strong>IHP</strong>.260.04, EP-Patentanmeldung am 14.05.04,<br />
AZ: 04 090 195.1<br />
(10) Verfahren zum schrittweisen Austausch persönlicher<br />
Informationen in non-trusted Peerto-Peer<br />
Umgebungen<br />
T. Falck, H. Maaß, K. Weidenhaupt, P. Langendörfer<br />
PHDE30356, PCT-Anmeldung mit Philips
Notizen Notices<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT 147
Notizen Notices<br />
148<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT
Wegbeschreibung zum <strong>IHP</strong><br />
Directions to <strong>IHP</strong><br />
per Flugzeug<br />
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Bahnhof Berlin-Zoologischer Garten (19 Minuten);<br />
dann mit dem RegionalExpress RE 1 bis Frankfurt<br />
(Oder) Hauptbahnhof (ca. 1 Stunde 20 Minuten).<br />
- Vom Flughafen Berlin-Schönefeld mit dem Airport-<br />
Express oder der S-Bahnlinie S 9 bis Bahnhof Berlin-Ostbahnhof<br />
(19 bzw. 32 Minuten); dann mit dem<br />
RegionalExpress RE 1 bis Frankfurt (Oder) Hauptbahnhof<br />
(ca. 1 Stunde).<br />
- Vom Flughafen Berlin-Tempelhof mit der U-Bahnlinie<br />
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(11 Minuten); umsteigen in den Regional-<br />
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per Auto<br />
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per Straßenbahn in Frankfurt (Oder)<br />
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in Richtung Markendorf Ort bis Haltestelle Technologiepark<br />
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by tram in Frankfurt (Oder)<br />
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Ort to Technologiepark (14 minutes).<br />
by plane<br />
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station Berlin-Zoologischer Garten (19 minutes);<br />
then take the RegionalExpress RE 1 to Frankfurt<br />
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- From Berlin-Tempelhof Airport take the subway line U 6<br />
in the direction Alt-Tegel to the station Friedrichstraße;<br />
there transfer to the RegionalExpress RE 1 to Frankfurt<br />
(Oder) Hauptbahnhof (appr. 1 hour 15 minutes).<br />
by train<br />
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railway stations Zoologischer Garten, Friedrichstraße,<br />
Alexanderplatz or Ostbahnhof to Frankfurt<br />
(Oder) Hauptbahnhof.<br />
by car<br />
JAHRESBERICHT <strong>2004</strong> | <strong>IHP</strong> ANNUAL REPORT<br />
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Frankfurt (Oder)/Warschau (Warsaw); take exit<br />
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follow the signs to "Technologiepark Ostbrandenburg"<br />
(appr. 1 hour).
<strong>2004</strong><br />
<strong>IHP</strong> GmbH – Innovations for High Performance <strong>Microelectronics</strong>/Institut<br />
für innovative Mikroelektronik<br />
Im Technologiepark 25<br />
15236 Frankfurt (Oder)<br />
Germany<br />
Phone +49.335.56 25 0<br />
Fax +49.335.56 25 300<br />
www.ihp-microelectronics.com<br />
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