Design Kit Tutorial for 0.13 µm SiGe BiCMOS IIS Erlangen, June 26 ...

Invitation
You are invited to attend the
Design Kit Tutorial for 0.13 µm SiGe BiCMOS
IIS Erlangen, June 26-27, 2012
Cadence AMS flow and mixed signal simulation in
IHP SG13 technologies
Start: June 26, 2012 11:00 a.m.
General Aspects:
- Opening remarks
- Tape out procedure and MPW organisation
- Design Kit installation and support
- Design Kit elements and features
Demonstration on Design Example:
- Cadence Schematic mixed signal simulation
- Cadence Layout verification (Assura)
DRC, LVS, QRC, Filler generation
- Parasitic Extraction Post layout simulation
End: June 27, 2012 ~3:00 p.m.
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Organisation
Registration
Please fill out the attached registration form. After receipt of your
registration we will send you a confirmation and an invoice for the
attendance fee (€ 500, 25% discount for Europractice members).
Contact and Requests
Dr. Wolfgang Kissinger
kissinger@ihp-microelectronics.com
Fax: +49 335 5625 222
Phone: +49 335 5625 410
Tutorial Location
The workshop will take place at the
Fraunhofer-Institut für Integrierte Schaltungen IIS
Am Wolfsmantel 33
91058 Erlangen, Germany
Hotel Information
http://www.iis.fraunhofer.de/en/kontakt/hotels/
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Registration Form
I will attend the design kit tutorial at June 26 & 27, 2012
Family Name…………………………………………
First Name…………………………………………….
Titel……………………………………………………
Organisation………………………………………….
Address………………………………………………
City…………………………………………………….
Zip Code………………………………………………
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The attendance fee is € 500 (€ 375 for Europractice members).
It includes documentations, light lunch and refreshments. It will
be invoiced with the confirmation of your registration.
Please fax or mail the registration form before June 15 to
Dr. Wolfgang Kissinger, Im Technologiepark 25
D-15236 Frankfurt (Oder), Germany
Email: kissinger@ihp-microelectronics.com
Fax: +49 335 5625 222
Phone: +49 335 5625 410
innovations for high performance microelectronics