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Advanced Configuration and Power Interface Specification

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<strong>Advanced</strong> <strong>Configuration</strong> <strong>and</strong> <strong>Power</strong> <strong>Interface</strong> <strong>Specification</strong><br />

Field<br />

Max Sections Per<br />

Record<br />

4 12 Indicates the maximum number of error sections included in an<br />

error record created as a result of an error reported by this error<br />

source. Must be >= 1.<br />

Bus 4 16 Identifies the PCI Bus <strong>and</strong> Segment of the device. The Bus is<br />

encoded in bits [7:0]. For systems that expose multiple PCI<br />

segment groups, the segment number is encoded in bits [23:8]<br />

<strong>and</strong> bits [31:24] must be zero. For systems that do not expose<br />

multiple PCI segment groups, bits 8-31 must be zero. If the<br />

GLOBAL flag is specified, this field is ignored.<br />

Device 2 20 Identifies the PCI Device Number of the device.<br />

If the GLOBAL flag is specified, this field is ignored.<br />

Function 2 22 Identifies the PCI Function Number of the device.<br />

If the GLOBAL flag is specified, this field is ignored.<br />

Device Control 2 24 Device control bits with which to initialize the device.<br />

Reserved 2 26 Must be zero.<br />

Uncorrectable Error<br />

Mask<br />

Uncorrectable Error<br />

Severity<br />

Correctable Error<br />

Mask<br />

<strong>Advanced</strong> Error<br />

Capabilities <strong>and</strong><br />

Control<br />

Byte<br />

Length<br />

Byte<br />

Offset<br />

Description<br />

4 28 Value to write to the root port’s Uncorrectable Error Mask<br />

register.<br />

4 32 Value to write to the root port’s Uncorrectable Error Severity<br />

register.<br />

4 36 Value to write to the root port’s Correctable Error Mask register.<br />

4 40 Value to write to the root port’s <strong>Advanced</strong> Error Capabilities <strong>and</strong><br />

Control Register.<br />

18.3.2.5 PCI Express/PCI-X Bridge AER Structure<br />

PCI Express/PCI-X bridges that implement AER support implement fields that control the behavior<br />

how errors are reported across the bridge.<br />

The HEST may contain one entry of this type for each PCI Express/PCI-X bridges if none of the<br />

entries has the GLOBAL flag set. If the GLOBAL flag is set, there may only be one entry of this<br />

type <strong>and</strong> the information contained in that entry will be applied to all PCI Express/ PCI-X bridges.<br />

Table 18-328 PCI Express Bridge AER Structure<br />

Field<br />

Byte<br />

Length<br />

Byte<br />

Offset<br />

Description<br />

Type 2 0 8 – AER Bridge.<br />

Source Id 2 2 Uniquely identifies the error source.<br />

Reserved 2 4 Reserved.<br />

722 April, 2015 Version 6.0

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