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Advanced Configuration and Power Interface Specification
ACPI_6.0
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<strong>Advanced</strong> <strong>Configuration</strong> <strong>and</strong> <strong>Power</strong> <strong>Interface</strong> <strong>Specification</strong><br />
660 April, 2015 Version 6.0
<strong>Advanced</strong> <strong>Configuration</strong> <strong>and</strong> <strong>Power</strong> <strong>Interface</strong> <strong>Specification</strong> 660 April, 2015 Version 6.0
ACPI System Management Bus <strong>Interface</strong> <strong>Specification</strong> 13 ACPI System Management Bus <strong>Interface</strong> <strong>Specification</strong> This section describes the System Management Bus (SMBus) generic address space <strong>and</strong> the use of this address space to access SMBus devices from AML. Unlike other address spaces, SMBus operation regions are inherently non-linear, where each offset within an SMBus address space represents a variable-sized (from 0 to 32 bytes) field. Given this uniqueness, SMBus operation regions include restrictions on their field definitions <strong>and</strong> require the use of an SMBus-specific data buffer for all transactions. The SMBus interface presented in this section is intended for use with any hardware implementation compatible with the SMBus specification. SMBus hardware is broadly classified as either non-EC– based or EC-based. EC-based SMBus implementations comply with the st<strong>and</strong>ard register set defined in Section 12, ACPI Embedded Controller <strong>Interface</strong> <strong>Specification</strong>.” Non-EC SMBus implementations can employ any hardware interface <strong>and</strong> are typically used for their cost savings when SMBus security is not required. Non–EC-based SMBus implementations require the development of hardware specific drivers for each OS implementation. See Section 13.2.1, “Declaring SMBus Host Controller Objects,” for more information. Support of the SMBus generic address space by ACPI-compatible operating systems is optional. As such, the Smart Battery System Implementer’s Forum (SBS-IF) has defined an SMBus interface based on a st<strong>and</strong>ard set of control methods. This interface is documented in the SMBus Control Method <strong>Interface</strong> <strong>Specification</strong>, available at “Links to ACPI-Related Documents” (http://uefi.org/ acpi) under the heading "Smart Battery System Components <strong>and</strong> SMBus <strong>Specification</strong>".. 13.1 SMBus Overview SMBus is a two-wire interface based upon the I²C protocol. The SMBus is a low-speed bus that provides positive addressing for devices, as well as bus arbitration. For more information, refer to the complete set of SMBus specifications published by the SBS-IF. 13.1.1 SMBus Slave Addresses Slave addresses are specified using a 7-bit non-shifted notation. For example, the slave address of the Smart Battery Selector device would be specified as 0x0A (1010b), not 0x14 (10100b) as might be found in other documents. These two different forms of addresses result from the format in which addresses are transmitted on the SMBus. During transmission over the physical SMBus, the slave address is formatted in an 8-bit block with bits 7-1 containing the address <strong>and</strong> bit 0 containing the read/write bit. ASL code, on the other h<strong>and</strong>, presents the slave address simply as a 7-bit value making it the responsibility of the OS (driver) to shift the value if needed. For example, the ASL value would have to be shifted left 1 bit before being Version 6.0 661
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Advanced Configuration and Power In
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Contents 1 2 Introduction........
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5 ACPI Software Programming Model
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7 6.3.6 _RMV (Remove) ............
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14.1.3 Generic Communications Subsp
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A.4.1 Power State Definitions......
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Tables Table 1-1 Hardware Type vs.
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Table 5-91 Power state Values .....
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Table 6-184 Device Insertion, Remov
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Table 10-275 Control Method Battery
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Table 19-367 Field Unit list entire
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Introduction 1.10 Related Documents
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Definition of Terms 2 Definition of
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ACPI Hardware Specification 4 ACPI
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Processor Configuration and Control
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Processor Configuration and Control
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ACPI Machine Language (AML) Specifi
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ACPI Machine Language (AML) Specifi
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ACPI Machine Language (AML) Specifi
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ACPI Machine Language (AML) Specifi
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ACPI Machine Language (AML) Specifi
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ACPI Machine Language (AML) Specifi
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ACPI Machine Language (AML) Specifi
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ACPI Machine Language (AML) Specifi
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ACPI Machine Language (AML) Specifi
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ACPI Data Tables and Table Definiti
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ACPI Data Tables and Table Definiti
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ACPI Data Tables and Table Definiti
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ACPI Data Tables and Table Definiti
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ACPI Data Tables and Table Definiti
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ACPI Data Tables and Table Definiti
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ACPI Data Tables and Table Definiti
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Appendix A Device Class Specificati
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• PCI Bus Power Management Capabi
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A.4.1 Power State Definitions State
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A.5.1 Power State Definitions State
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A.6.1.2 Internal Flat Panel Devices
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power transitions and power managem
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A video controller conforming to th
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State Status Definition D2 N/A This
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The most common modem type is an IS
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State Status Definition D1 Optional
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A.10.1 Power State Definitions Stat
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A.11.1 Power State Definitions A.11
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A floppy disk and IDE channel devic
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Appendix B Video Extensions B.1 ACP
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GPE // ACPI General-purpose HW even
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B.3.2 _DOD (Enumerate All Devices A
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Pipe / Head Ports Display Types Dis
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the next boot, a 1 indicates a PCI
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Value 0x84 Description Previous Dis
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B.5.5 _DDC (Return the EDID for thi
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Bits Definition 31 0 - Don’t do a
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internal data structure of the OS t
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Symbols _EJx 334 ??????????????????
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Power Resource statements 391 prima
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centenary value, RTC alarm 83 Centr
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power resource objects 398 D2 Devic
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Eject Device List (_EDL) object 332
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features 68 functional implementati
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I/O resource flag 366 I/O SAPIC def
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logic fixed power button 77 lid swi
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objects _ BMC (Battery Maintenance
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transitioning working to soft-off s
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power resources battery management
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definition 22 table fields 115 RTC_
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protocols 650, 662, 669 Read/Write
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top of memory 704 ToString (Convert
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