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Advanced Configuration and Power Interface Specification

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<strong>Advanced</strong> <strong>Configuration</strong> <strong>and</strong> <strong>Power</strong> <strong>Interface</strong> <strong>Specification</strong><br />

Table 12-292 Events for Which Embedded Controller Must Generate SCIs<br />

Event<br />

IBF=0<br />

OBF=1<br />

SCI_EVT=1<br />

Description<br />

Signals that the embedded controller has read the last comm<strong>and</strong> or data from the input<br />

buffer <strong>and</strong> the host is free to send more data.<br />

Signals that the embedded controller has written a byte of data into the output buffer <strong>and</strong><br />

the host is free to read the returned data.<br />

Signals that the embedded controller has detected an event that requires OS attention.<br />

OSPM should issue a query (QR_EC) comm<strong>and</strong> to find the cause of the event.<br />

12.6.2 Comm<strong>and</strong> Interrupt Model<br />

The embedded controller must generate SCIs for comm<strong>and</strong>s as follows:<br />

Table 12-293 Read Comm<strong>and</strong> (3 Bytes)<br />

Byte #1 (Comm<strong>and</strong> byte Header) Interrupt on IBF=0<br />

Byte #2 (Address byte to read) No Interrupt<br />

Byte #3 (Data read to host) Interrupt on OBF=1<br />

Table 12-294 Write Comm<strong>and</strong> (3 Bytes)<br />

Byte #1 (Comm<strong>and</strong> byte Header) Interrupt on IBF=0<br />

Byte #2 (Address byte to write) Interrupt on IBF=0<br />

Byte #3 (Data to read ) Interrupt on IBF=0<br />

Table 12-295 Query Comm<strong>and</strong> (2 Bytes<br />

Byte #1 (Comm<strong>and</strong> byte Header) No Interrupt<br />

Byte #2 (Query value to host) Interrupt on OBF=1<br />

Table 12-296 Burst Enable Comm<strong>and</strong> (2 Bytes)<br />

Byte #1 (Comm<strong>and</strong> byte Header) No Interrupt<br />

Byte #2 (Burst acknowledge byte) Interrupt on OBF=1<br />

Table 12-297 Burst Disable Comm<strong>and</strong> (1 Byte)<br />

Byte #1 (Comm<strong>and</strong> byte Header) Interrupt on IBF=0<br />

12.7 Embedded Controller Interfacing Algorithms<br />

To initiate communications with the embedded controller, OSPM or system management h<strong>and</strong>ler<br />

acquires ownership of the interface. This ownership is acquired through the use of the Global Lock<br />

(described in Section 5.2.10.1, “Global Lock”), or is owned by default by OSPM as a non-shared<br />

resource (<strong>and</strong> the Global Lock is not required for accessibility).<br />

644 April, 2015 Version 6.0

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