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Advanced Configuration and Power Interface Specification

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<strong>Advanced</strong> <strong>Configuration</strong> <strong>and</strong> <strong>Power</strong> <strong>Interface</strong> <strong>Specification</strong><br />

Field Format Description<br />

Flags DWORD Mode flags<br />

Bit [0]: 1 indicates using UltraDMA on drive 0<br />

Bit [1]: 1 indicates IOChannelReady is used on drive 0<br />

Bit [2]: 1 indicates using UltraDMA on drive 1<br />

Bit [3]: 1 indicates IOChannelReady is used on drive 1<br />

Bit [4]: 1 indicates chipset can set timing independently for each drive<br />

Bits [31:5]: reserved (must be 0)<br />

9.8.2.1.2 _STM (Set Timing Mode)<br />

This Control Method sets the IDE channel’s transfer timings to the setting requested. The AML code<br />

is required to convert <strong>and</strong> set the nanoseconds timing to the appropriate transfer mode settings for<br />

the IDE controller. _STM may also make adjustments so that _GTF control methods return the<br />

correct comm<strong>and</strong>s for the current channel settings.<br />

This control method takes three arguments: Channel timing information (as described in Table 9-6),<br />

<strong>and</strong> the ATA drive ID block for each drive on the channel. The channel timing information is not<br />

guaranteed to be the same values as returned by _GTM; the OS may tune these values as needed.<br />

Arguments: (3)<br />

Arg0 – A Buffer containing a channel timing information block (described in Table 9-6)<br />

Arg1 – A Buffer containing the ATA drive ID block for channel 0<br />

Arg2 – A Buffer containing the ATA drive ID block for channel 1<br />

Return Value:<br />

None<br />

The ATA drive ID block is the raw data returned by the Identify Drive ATA comm<strong>and</strong>, which has<br />

the comm<strong>and</strong> code “0ECh.” The _STM control method is responsible for correcting for drives that<br />

misreport their timing information.<br />

9.8.3 Serial ATA (SATA) Controller Device<br />

9.8.3.1 Definitions<br />

HBA<br />

Native SATA aware<br />

Host Bus Adapter<br />

Refers to system software (BIOS, option ROM, operating system,<br />

etc) that comprehends a particular SATA HBA implementation<br />

<strong>and</strong> underst<strong>and</strong>s its programming interface <strong>and</strong> power<br />

management behavior.<br />

Non-native SATA aware Refers to system software (BIOS, option ROM, operating system,<br />

etc) that does not comprehend a particular SATA HBA<br />

implementation <strong>and</strong> does not underst<strong>and</strong> its programming<br />

interface or power management behavior. Typically, non-native<br />

SATA aware software will use a SATA HBA’s emulation<br />

interface (e.g. task file registers) to control the HBA <strong>and</strong> access<br />

its devices.<br />

512 April, 2015 Version 6.0

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