27.10.2015 Views

Advanced Configuration and Power Interface Specification

ACPI_6.0

ACPI_6.0

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

<strong>Advanced</strong> <strong>Configuration</strong> <strong>and</strong> <strong>Power</strong> <strong>Interface</strong> <strong>Specification</strong><br />

optimizations / control policy <strong>and</strong> the performance impact of the platform's energy efficiency-related<br />

optimizations / control policy.<br />

Writes to this register only have meaning when Autonomous Selection is enabled.<br />

8.4.7.1.8 OSPM Control Policy<br />

8.4.7.1.8.1 In-B<strong>and</strong> Thermal Control<br />

A processor using performance controls may be listed in a thermal zone’s _PSL list. If it is <strong>and</strong> the<br />

thermal zone engages passive cooling as a result of passing the _PSV threshold, OSPM will apply<br />

the ∆P[%] to modify the value in the desired performance register. Any time that passive cooling is<br />

engaged, OSPM must also set the maximum performance register equal to the desired performance<br />

register, to enforce the platform does not exceed the desired performance opportunistically.<br />

Note: In System-on-Chip-based platforms where the SoC is comprised of multiple device components in<br />

addition to the processor, OSPM’s use of the Desired <strong>and</strong> Maximum registers for thermal control<br />

may not produce an optimal result because of SoC device interaction. The use of proprietary<br />

package level thermal controls (if they exist) may produce more optimal results.<br />

8.4.7.1.9 Using PCC Registers<br />

If the PCC register space is used, all PCC registers must be defined to be in the same subspace.<br />

OSPM will write registers by filling in the register value <strong>and</strong> issuing a PCC write comm<strong>and</strong> (see<br />

Table 8-252). It may read static registers, counters, <strong>and</strong> the performance limited register by issuing a<br />

read comm<strong>and</strong> (see Table 8-252). To amortize the cost of PCC transactions, OSPM should read or<br />

write all PCC registers via a single read or write comm<strong>and</strong> when possible.<br />

Table 8-252 PCC Comm<strong>and</strong>s Codes used by Collaborative Processor Performance Control<br />

Comm<strong>and</strong> Description<br />

0x00<br />

0x01<br />

0x02-0xFF<br />

Read registers. Executed to request the platform update all registers for all enabled<br />

processors with their current value.<br />

Write registers. Executed to notify the platform one or more read/write registers for an<br />

enabled processor has been updated.<br />

All other values are reserved.<br />

8.4.7.1.10 Relationship to other ACPI-defined Objects <strong>and</strong> Notifications<br />

If _CPC is present, its use supersedes the use of the following existing ACPI objects:<br />

• The P_BLK P_CNT register<br />

• _PTC<br />

• _TSS<br />

• _TPC<br />

• _TSD<br />

• _TDL<br />

• _PCT<br />

• _PSS<br />

490 April, 2015 Version 6.0

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!