Advanced Configuration and Power Interface Specification

Advanced Configuration and Power Interface Specification
querying the feedback counters, the counters may wrap without OSPM being able to detect that they
have done so.
If not implemented (or zero), the performance counters are assumed to never wrap during the
lifetime of the platform.
8.4.7.1.3.2 Performance Limited Register
Register Location: PCC or Functional Fixed Hardware
Attribute:
Read/Write
Size:
>=2 bit(s)
In the event that the platform must constrain the delivered performance to less than the minimum
performance or the desired performance (or, less than the guaranteed performance, if desired
performance is greater than guaranteed performance) due to an unpredictable event, the platform
must set the performance limited indicator to a non-zero value. This indicates to OSPM that an
unpredictable event has limited processor performance, and the delivered performance may be less
than desired / minimum performance.
Table 8-251 Performance Limited Register Status Bits
Bit Name Description
0 Desired_Excursion Set when Delivered Performance has been constrained to less than
Desired Performance (or, less than the guaranteed performance, if desired
performance is greater than guaranteed performance). This bit is not
utilized when Autonomous Selection is enabled.
1 Minimum_Excursion Set when Delivered Performance has been constrained to less than
Minimum Performance
2-n Reserved Reserved
Bits within the Performance Limited Register are sticky, and will remain non-zero until OSPM
clears the bit. The platform should only issue a Notify when Minimum Excursion transitions from 0
to 1 to avoid repeated events when there is sustained or recurring limiting but OSPM has not cleared
the previous indication.
Note: All accesses to the Performance Limited Register must be made using interlocked operations, by
both accessing entities.
The performance limited register should only be used to report short term, unpredictable events (e.g.,
PROCHOT being asserted). If the platform is capable of identifying longer term, predictable events
that limit processor performance, it should use the guaranteed performance register to notify OSPM
of this limitation. Changes to guaranteed performance should not be more frequent than once per
second. If the platform is not able to guarantee a given performance level for a sustained period of
time (greater than one second), it should guarantee a lower performance level and opportunistically
enter the higher performance level as requested by OSPM and allowed by current operating
conditions.
488 April, 2015 Version 6.0