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Advanced Configuration and Power Interface Specification

ACPI_6.0

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Processor <strong>Configuration</strong> <strong>and</strong> Control<br />

performance states including internal CPU core frequency, typical power dissipation, control<br />

register values needed to transition between performance states, <strong>and</strong> status register values that allow<br />

OSPM to verify performance transition status after any OS-initiated transition change request. The<br />

list is sorted in descending order by typical power dissipation. As a result, the zeroth entry describes<br />

the highest performance state <strong>and</strong> the ‘nth’ entry describes the lowest performance state.<br />

Arguments:<br />

None<br />

Return Value:<br />

A variable-length Package containing a list of Pstate sub-packages as described below<br />

Return Value Information<br />

Package {<br />

PState [0] // Package – Performance state 0<br />

}<br />

….<br />

PState [n]<br />

// Package – Performance state n<br />

Each Pstate sub-Package contains the elements described below:<br />

Package {<br />

CoreFrequency<br />

<strong>Power</strong><br />

Latency<br />

BusMasterLatency<br />

Control<br />

Status<br />

}<br />

// Integer (DWORD)<br />

// Integer (DWORD)<br />

// Integer (DWORD)<br />

// Integer (DWORD)<br />

// Integer (DWORD)<br />

// Integer (DWORD)<br />

Table 8-248 PState Package Values<br />

Element Object Type Description<br />

Core<br />

Frequency<br />

<strong>Power</strong><br />

Latency<br />

Bus Master<br />

Latency<br />

Control<br />

Status<br />

Integer<br />

(DWORD)<br />

Integer<br />

(DWORD)<br />

Integer<br />

(DWORD)<br />

Integer<br />

(DWORD)<br />

Integer<br />

(DWORD)<br />

Integer<br />

(DWORD)<br />

Indicates the core CPU operating frequency (in MHz).<br />

Indicates the performance state’s maximum power dissipation (in milliwatts).<br />

Indicates the worst-case latency in microseconds that the CPU is unavailable<br />

during a transition from any performance state to this performance state.<br />

Indicates the worst-case latency in microseconds that Bus Masters are<br />

prevented from accessing memory during a transition from any performance<br />

state to this performance state.<br />

Indicates the value to be written to the Performance Control Register<br />

(PERF_CTRL) in order to initiate a transition to the performance state.<br />

Indicates the value that OSPM will compare to a value read from the<br />

Performance Status Register (PERF_STATUS) to ensure that the transition to<br />

the performance state was successful. OSPM may always place the CPU in<br />

the lowest power state, but additional states are only available when indicated<br />

by the _PPC method.<br />

Version 6.0 471

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