Advanced Configuration and Power Interface Specification

Advanced Configuration and Power Interface Specification
Return Value Information
Package {
TStateDependency[0] // Package
….
TStateDependency[n] // Package
}
Each TStateDependency sub-Package contains the elements described below:
Package {
NumEntries
Revision
Domain
CoordType
NumProcessors
}
// Integer
// Integer (BYTE)
// Integer (DWORD)
// Integer (DWORD)
// Integer (DWORD)
Table 8-246 TStateDependency Package Values
Element Object Type Description
NumEntries Integer The number of entries in the TStateDependency package including this field.
Current value is 5.
Revision Integer
(BYTE)
The revision number of the TStateDependency package format. Current
value is 0.
Domain
CoordType
Num
Processors
Integer
(DWORD)
Integer
(DWORD)
Integer
(DWORD)
The dependency domain number to which this T state entry belongs.
The type of coordination that exists (hardware) or is required (software) as a
result of the underlying hardware dependency. Could be either 0xFC
(SW_ALL), 0xFD (SW_ANY) or 0xFE (HW_ALL) indicating whether OSPM is
responsible for coordinating the T-state transitions among processors with
dependencies (and needs to initiate the transition on all or any processor in
the domain) or whether the hardware will perform this coordination.
The number of processors belonging to the domain for this logical
processor’s T-states. OSPM will not start performing power state transitions
to a particular T-state until this number of processors belonging to the same
domain have been detected and started.
Example
This is an example usage of the _TSD structure in a Processor structure in the namespace. The
example represents a two processor configuration with three T-states per processor. For all T-states,
there exists dependence between the two processors, such that one processor transitioning to a
particular T-state, causes the other processor to transition to the same T-state. OSPM will be
required to coordinate the T-state transitions between the two processors and can initiate a transition
on either processor to cause both to transition to the common target T-state.
466 April, 2015 Version 6.0