Advanced Configuration and Power Interface Specification

Processor Configuration and Control
Table 8-243 Entry method example
Core LPI Cluster LPI System LPI Composite State Entry Method
Retention
Register: 0xDEAF
Power Down
Register 0xDEAD
Retention
Register: 0xDEAF
Power Down
Register: 0xDEAD
Run Run Core Retention
Register: 0xDEAF
Run Run Core Power Down
Register: 0xDEAD
Retention
Integer: 0x0
Retention
Integer: 0x0
Run
Run
Core Retain|Cluster Retention
Register 0xDEAF+0x0 = 0xDEAF
Core Power Down|Cluster Retention
Register 0xDEAD+0x1020000 = 0xDEAD
Power Down
Register: 0xDEAD
Power Down
Integer:
0x1020000
Run
Core Power Down|Cluster Power Down
Register 0xDEAD+0x1020000 =
0x102DEAD
System Power Down
Register 0xDECEA5ED
Power Down
Register: 0xDEAD
Power Down
Integer:
0x1020000
Power Down
Register :
0xDECEA5ED
As can be seen in the example, the cluster level retention state defines the integer value of 0 as its
entry method. By virtue of composition, this means that the entry methods for the composite states
Core Power Down and Core Power Down|Cluster Retention are the same (FFH register 0xDEAD).
Similarly the composite states for Core Retention and Core Retention|Cluster Retention are the same
(FFH register 0xDEAF). Consequently, if both CPU0 and CPU1 are in either Power Down or Power
Retention, then the platform may enter cluster CLU0 into Retention.
The example also shows how a register based entry method at a high level overrides entry method
definitions of lower levels. As pointed above this is only possible if the selected LPI implies specific
LPIs at all lower levels. In this example the System Power Down LPI, entered through FFH register
0xDECEA5ED, implies Power Down LPIs at core and cluster level since based on EPS, no other
core/cluster local states could enable System Power Down.
8.4.4.3.5 Architecture Specific Context Loss Flags
For Intel based systems the value of this flags register is 0.
For ARM based systems please refer to links to ACPI-Related Documents (http://uefi.org/acpi)
under the heading "ARM FFH Specification”.
8.4.4.3.6 Residency and Entry Counter Registers
LPI state descriptions may optionally provide Residency and Usage Count registers to allow the
OSPM to gather statistics about the platform usage of a given local state. Both registers provide
running counts of their respective statistics. To measure a statistic over some time window, OSPM
should sample at the beginning and end and calculate the delta. Whether the counters restart from 0
on various flavors of reset/S-state exit is implementation defined so OSPM should resynchronize its
baseline on any reset or Sx exit.
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