Advanced Configuration and Power Interface Specification

Processor Configuration and Control
shallower power state in the parent is also enabled. Taking the system described in Figure 8-46, the
states and EPS value for the states is described in the table below:
Table 8-242 Enabled Parent State values for example system
System Level Processor
Container LPI States
Enabled Parent State
0 Running N/A
1 Power Down 0
Cluster Level Processor Container LPI States
0 Running N/A
1 Clock Gating 0 – System must be running if cluster is clock gated
2 Retention 0 – System must be running if cluster is in retention
3 Power Down 1 – System may be in power down if cluster is in power down
Core Level Processor Container LPI States
0 Running N/A
1 Clock Gating 1 – Cluster may be clock gated or running of core is clock
gated
2 Retention 2 – Cluster may running, or clock gated, or in retention if core is
in retention
3 Power Down 3 – All states at cluster level are supported if the core is
powered down
8.4.4.3.3 Power, Minimum Residency, and Worst Case Wakeup Latency
Power is not included in _LPI since relative power of different states (along with minimum
residency to comprehend transition energy), and not absolute power, drive OSPM idle state
decisions. To correctly convey relative power, local states in _LPI must be declared in power
consumption order. That is, the local states for a particular hierarchy node must be listed from
highest power (shallowest) to lowest power (deepest).
The worst case wakeup latency (WCWL) for a particular local state is the longest time from when a
wake interrupt is asserted, to when the hierarchy node can return to execution. Generally, the
WCWL will be the idle state’s exit latency plus some portion of its entry latency. How much of the
entry flow is included depends on where (and if) the platform supports checking for pending wake
events and aborting the idle state entry. For any given power state there will be a “point of no return”
after which the entry into the power state cannot be reversed. This is illustrated in Figure 8-47
below. The WCWL must include the time period from the point of no return to the time at which a
wake up interrupt can be handled.
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