27.10.2015 Views

Advanced Configuration and Power Interface Specification

ACPI_6.0

ACPI_6.0

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

Processor <strong>Configuration</strong> <strong>and</strong> Control<br />

When the OS running on a given processor detects there is no more work to schedule on that<br />

processor, it needs to select an idle state. The state may affect more than just that processor. A<br />

processor going idle could be the last one in the system, or in a processor container, <strong>and</strong> therefore<br />

may select a power state what affects multiple processors. In order to select such a state, the OS<br />

needs to choose a local power state for each affected level in the processor hierarchy.<br />

Cluster 0's children<br />

System<br />

Level ID: 3<br />

_LPI:<br />

1: <strong>Power</strong> Down<br />

Cluster0's local states<br />

LevelID: 2<br />

_LPI:<br />

1: Clock Gate<br />

2: Retention<br />

3: <strong>Power</strong> Down<br />

Cluster<br />

0<br />

Cluster1<br />

LevelID: 2<br />

_LPI:<br />

1: Clock Gate<br />

2: Retention<br />

3: <strong>Power</strong> Down<br />

Shallower states<br />

Deeper states<br />

Core0 Core1 Core2 Core3<br />

Core0's local states<br />

LevelID: 1<br />

_LPI:<br />

1: Clock Gate<br />

2: Retention<br />

3: <strong>Power</strong> Down<br />

LevelID: 1<br />

_LPI:<br />

1: Clock Gate<br />

2: Retention<br />

3: <strong>Power</strong> Down<br />

LevelID: 1<br />

_LPI:<br />

1: Clock Gate<br />

2: Retention<br />

3: <strong>Power</strong> Down<br />

LevelID: 1<br />

_LPI:<br />

1: Clock Gate<br />

2: Retention<br />

3: <strong>Power</strong> Down<br />

Figure 8-46 <strong>Power</strong> states for processor hierarchy<br />

Consider a situation where Core 0 is the last active core depicted in the example system, Figure 8-<br />

46. It may put the system into the lowest possible idle state. To do so, the OS chooses local state 3<br />

(<strong>Power</strong> Down) for Core0, local state 3 (<strong>Power</strong> Down) for Cluster0, <strong>and</strong> local state 1 (<strong>Power</strong> Down)<br />

for the system. However, most HW architectures only support a single power state request from the<br />

OS to the platform. That is, it is not possible to make a separate local power state request per<br />

hierarchy node to the platform. Therefore, the OS must combine the per level local power states into<br />

a single Composite power state. The platform then acts on the Composite power state request.<br />

A platform can only support a limited set of Composite power states, <strong>and</strong> not every combination of<br />

Local <strong>Power</strong> states across levels is valid. The valid power states in our example system are depicted<br />

in the following table:<br />

Table 8-239 Valid Local State Combinations in Figure 2 example system<br />

System Level Processor<br />

Container<br />

Cluster level Processor<br />

Container<br />

Processor<br />

Running Running Clock Gated<br />

Running Running Retention<br />

Running Running <strong>Power</strong> Down<br />

Running Clock Gated Clock Gated<br />

Version 6.0 437

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!