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Advanced Configuration and Power Interface Specification

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Processor <strong>Configuration</strong> <strong>and</strong> Control<br />

belong to a container if they are associated in some way, such as a shared cache or a low power<br />

mode which affects them all.<br />

Parent for cluster 0 <strong>and</strong><br />

cluster 1<br />

System<br />

Root<br />

Cluster<br />

0<br />

Cluster<br />

1<br />

Higher Level<br />

Lower Level<br />

Cluster 0's children<br />

Core0 Core1 Core2 Core3<br />

Leaves<br />

Figure 8-45 Processor Hierarchy<br />

Figure 8-45 depicts an example system, which comprises a system level processor container, which<br />

in turn contains two cluster processor containers, each of which contains two processors. The overall<br />

collection is called the processor hierarchy <strong>and</strong> st<strong>and</strong>ard tree terminology is used to refer to different<br />

parts of it. For example, an individual processor or container is called a node, the nodes which reside<br />

within a processor container are called children of that parent, etc. This example is symmetric but<br />

that is not a requirement. For example, a system may contain a different number of processors in<br />

different containers or an asymmetric hierarchy where one side of the topology tree is deeper than<br />

another. Also note that while this example includes a single top level processor container<br />

encompassing all processors, this is not a requirement. It is legal for a system to be described using a<br />

collection of trees.<br />

The processor hierarchy can be used to describe a number of different characteristics of system<br />

topology. The main example is shared power states, see the Low <strong>Power</strong> Idle states in Section 8.4.4<br />

for details.<br />

8.4.3.1 Processor Container Device<br />

This optional device is a container object that acts much like a bus node in a namespace. It may<br />

contain child objects that are either processor devices or other processor containers. This allows<br />

representing hierarchical processor topologies. Each processor container or processor in the<br />

Version 6.0 435

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