27.10.2015 Views

Advanced Configuration and Power Interface Specification

ACPI_6.0

ACPI_6.0

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

Processor <strong>Configuration</strong> <strong>and</strong> Control<br />

}<br />

//<br />

// Note: The UUID passed into _OSC is CPU vendor specific. Consult CPU<br />

// vendor documentation for UUID <strong>and</strong> Capabilities Buffer bit definitions<br />

//<br />

_OSC (ToUUID("4077A616-290C-47BE-9EBD-D87058713953"), REVS, SIZE, Local2)<br />

Section 6.2.11, “_OSC (Operating System Capabilities)”, describes the _OSC object, which can be<br />

used to convey processor related OSPM capabilities to the platform. Consult CPU vendor specific<br />

documentation for the UUID <strong>and</strong> Capabilities Buffer bit definitions used by _OSC for a specific<br />

processor.<br />

8.4.2 Processor <strong>Power</strong> State Control<br />

ACPI defines multiple processor power state (C state) control interfaces. These are:<br />

1. The Processor Register Block’s (P_BLK’s) P_LVL2 <strong>and</strong> P_LVL3 registers coupled with FADT<br />

P_LVLx_LAT values <strong>and</strong><br />

2. The _CST object in the processor’s object list.<br />

3. The _LPI objects for processors <strong>and</strong> processor containers.<br />

P_BLK based C state controls are described in Section 4, “ACPI Hardware <strong>Specification</strong>” <strong>and</strong><br />

Section 8.1, “Processor <strong>Power</strong> States”. _CST based C state controls exp<strong>and</strong> the functionality of the<br />

P_BLK based controls allowing the number <strong>and</strong> type of C states to be dynamic <strong>and</strong> accommodate<br />

CPU architecture specific C state entry <strong>and</strong> exit mechanisms as indicated by registers defined using<br />

the Functional Fixed Hardware address space.<br />

_CST is an optional object that provides:<br />

• The Processor Register Block's (P_BLK's) P_LVL2 <strong>and</strong> P_LVL3 registers coupled with FADT<br />

P_LVLx_LAT values.<br />

• The _CST object in the processor's object list.<br />

ACPI 6.0 introduces _LPI, the low power idle state object. _LPI provides more detailed power state<br />

information <strong>and</strong> can describe idle states at multiple levels of hierarchy in conjunction with Processor<br />

Containers. See Section 8.4.4.3 for details.<br />

8.4.2.1 _CST (C States)<br />

_CST is an optional object that provides an alternative method to declare the supported processor<br />

power states (C States). Values provided by the _CST object override P_LVLx values in P_BLK <strong>and</strong><br />

P_LVLx_LAT values in the FADT. The _CST object allows the number of processor power states<br />

to be exp<strong>and</strong>ed beyond C1, C2, <strong>and</strong> C3 to an arbitrary number of power states. The entry semantics<br />

for these exp<strong>and</strong>ed states, (in other words), the considerations for entering these states, are conveyed<br />

to OSPM by the C-state Type field <strong>and</strong> correspond to the entry semantics for C1, C2, <strong>and</strong> C3 as<br />

described in Section 8.1.2 through Section 8.1.4. _CST defines ascending C-states characterized by<br />

lower power <strong>and</strong> higher entry/exit latency.<br />

Arguments:<br />

None<br />

Version 6.0 429

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!