Advanced Configuration and Power Interface Specification

Advanced Configuration and Power Interface Specification
Nominal performance is defined as “close as possible, but not below the indicated performance
level.” OSPM will use the duty offset and duty width to determine how to access the duty setting
field. OSPM will then program the duty setting based on the thermal condition and desired power of
the processor object. OSPM calculates the nominal performance of the processor using the equation
expressed in Equation 1. Notice that a dutysetting of zero is reserved.For example, the clock logic
could use the stop grant cycle to emulate a divided processor clock frequency on an IA processor
(through the use of the STPCLK# signal). This signal internally stops the processor’s clock when
asserted LOW. To implement logic that provides eight levels of clock control, the STPCLK# pin
could be asserted as follows (to emulate the different frequency settings):
dutysetting
0 - Reserved Value
1
2
3
4
5
6
7
STPCLK# Signal
0 1 2 3 4 5 6 7
CPU Clock Running
Duty Width (3-bits)
CPU Clock Stopped
Figure 8-43 Example Control for the STPCLK#
To start the throttling logic OSPM sets the desired duty setting and then sets the THT_EN bit HIGH.
To change the duty setting, OSPM will first reset the THT_EN bit LOW, then write another value to
the duty setting field while preserving the other unused fields of this register, and then set the
THT_EN bit HIGH again.
The example logic model is shown below:
P_LVL3
Read
P_LVL2
Read
BM_RLD
PM1x_CNT.1
ARB_DIS
PM2_CNT
BM_STS
PM1x_STS.4
Clock Logic
System
Arbiter
-- duty width
THT_EN
P_CNT.4
THTL_DTY
P_CNT.x
Figure 8-44 ACPI Clock Logic (One per Processor)
Implementation of the ACPI processor power state controls minimally requires the support a single
CPU sleeping state (C1). All of the CPU power states occur in the G0/S0 system state; they have no
meaning when the system transitions into the sleeping state(S1-S4). ACPI defines the attributes
422 April, 2015 Version 6.0