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Advanced Configuration and Power Interface Specification

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<strong>Advanced</strong> <strong>Configuration</strong> <strong>and</strong> <strong>Power</strong> <strong>Interface</strong> <strong>Specification</strong><br />

Large Item Name<br />

Extended IRQ Descriptor<br />

QWORD Address Space Descriptor<br />

Extended Address Space Descriptor<br />

GPIO Connection Descriptor<br />

Reserved<br />

GenericSerialBus Connection Descriptor<br />

Reserved<br />

Value<br />

0x09<br />

0x0A<br />

0x0B<br />

0x0C<br />

0x0D<br />

0x0E<br />

0x0F – 0x7F<br />

6.4.3.1 24-Bit Memory Range Descriptor<br />

Type 1, Large Item Name 0x1<br />

The 24-bit memory range descriptor describes a device’s memory range resources within a 24-bit<br />

address space<br />

Table 6-204 24-bit Memory Range Descriptor Definition.<br />

Offset Field Name, ASL Field Definition<br />

Name<br />

Byte 0 24-bit Memory Range Value = 0x81 (10000001B) – Type = 1, Large item name = 0x01<br />

Descriptor<br />

Byte 1 Length, bits[7:0] Value = 0x09 (9)<br />

Byte 2 Length, bits[15:8] Value = 0x00<br />

Byte 3 Information This field provides extra information about this memory.<br />

Bit [7:1] Ignored<br />

Bit [0] Write status, _RW<br />

1 writeable (read/write)<br />

0 non-writeable (read-only)<br />

Byte 4<br />

Byte 5<br />

Byte 6<br />

Byte 7<br />

Byte 8<br />

Byte 9<br />

Byte 10<br />

Range minimum base<br />

address, _MIN, bits[7:0]<br />

Range minimum base<br />

address, _MIN, bits[15:8]<br />

Range maximum base<br />

address, _MAX, bits[7:0]<br />

Range maximum base<br />

address, _MAX, bits[15:8]<br />

Base alignment, _ALN,<br />

bits[7:0]<br />

Base alignment, _ALN,<br />

bits[15:8]<br />

Range length, _LEN,<br />

bits[7:0]<br />

Address bits [15:8] of the minimum base memory address for<br />

which the card may be configured.<br />

Address bits [23:16] of the minimum base memory address for<br />

which the card may be configured<br />

Address bits [15:8] of the maximum base memory address for<br />

which the card may be configured.<br />

Address bits [23:16] of the maximum base memory address for<br />

which the card may be configured<br />

This field contains the lower eight bits of the base alignment. The<br />

base alignment provides the increment for the minimum base<br />

address. (0x0000 = 64 KB)<br />

This field contains the upper eight bits of the base alignment. The<br />

base alignment provides the increment for the minimum base<br />

address. (0x0000 = 64 KB)<br />

This field contains the lower eight bits of the memory range length.<br />

The range length provides the length of the memory range in 256<br />

byte blocks.<br />

350 April, 2015 Version 6.0

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