Advanced Configuration and Power Interface Specification

Advanced Configuration and Power Interface Specification
record to program the AER registers of a hot-added PCI Express device. However, since the Type 2
record also includes register bits that have functions other than AER, OSPM must ignore values
contained within this setting record that are not applicable.
To support PCIe RsvdP semantics for reserved bits, two values for each register are provided: an
“AND mask” and an “OR mask”. Each bit understood by firmware to be RsvdP shall be set to 1 in
the “AND mask” and 0 in the “OR mask”. Each bit that firmware intends to be configured as 0 shall
be set to 0 in both the “AND mask” and the “OR mask”. Each bit that firmware intends to be
configured a 1 shall be set to 1 in both the “AND mask” and the “OR mask”.
When configuring a given register, OSPM uses the following algorithm:
1. Read the register’s current value, which contains the register’s default value.
2. Perform a bit-wise AND operation with the “AND mask” from the table below.
3. Perform a bit-wise OR operation with the “OR mask” from the table below.
4. Override the computed settings for any bits if deemed necessary. For example, if OSPM is aware of an
architected meaning for a bit that firmware considers to be RsvdP, OSPM may choose to override the
computed setting for that bit. Note that firmware sets the “AND value” to 1 and the “OR value” to 0 for
each bit that it considers to be RsvdP.
5. Write the end result value back to the register.
Note that the size of each field in the following table matches the size of the corresponding PCI
Express register.
Table 6-175 PCI Express Setting Record Content
Field Object Type Definition
Header:
Type Integer 0x02: Type 2 (PCI Express) setting record.
Revision Integer 0x01: Revision 1, defining the set of fields below.
Uncorrectable Error Mask Register
AND Mask
Uncorrectable Error Mask Register
OR Mask
Uncorrectable Error Severity
Register AND Mask
Uncorrectable Error Severity
Register OR Mask
Correctable Error Mask Register
AND Mask
Correctable Error Mask Register OR
Mask
Advanced Error Capabilities and
Control Register AND Mask
Advanced Error Capabilities and
Control Register OR Mask
Integer
Integer
Integer
Integer
Integer
Integer
Integer
Integer
Bits [31:0] contain the “AND mask” to be used in the
OSPM algorithm described above.
Bits [31:0] contain the “OR mask” to be used in the
OSPM algorithm described above.
Bits [31:0] contain the “AND mask” to be used in the
OSPM algorithm described above.
Bits [31:0] contain the “OR mask” to be used in the
OSPM algorithm described above.
Bits [31:0] contain the “AND mask” to be used in the
OSPM algorithm described above.
Bits [31:0] contain the “OR mask” to be used in the
OSPM algorithm described above.
Bits [31:0] contain the “AND mask” to be used in the
OSPM algorithm described above.
Bits [31:0] contain the “OR mask” to be used in the
OSPM algorithm described above.
Device Control Register AND Mask Integer Bits [15 :0] contain the “AND mask” to be used in the
OSPM algorithm described above.
Device Control Register OR Mask Integer Bits [15:0] contain the “OR mask” to be used in the
OSPM algorithm described above.
310 April, 2015 Version 6.0