Advanced Configuration and Power Interface Specification

Device Configuration
Field Object Type Definition
Revision Integer 0x01: Revision 1, defining the set of fields below.
Maximum
memory read byte
count
Average
maximum
outstanding split
transactions
Total maximum
outstanding split
transactions
Integer
Integer
Integer
Maximum memory read byte count reported:
Value 0: Maximum byte count 512
Value 1: Maximum byte count 1024
Value 2: Maximum byte count 2048
Value 3: Maximum byte count 4096
The following values are defined:
Value 0: Maximum outstanding split transaction 1
Value 1: Maximum outstanding split transaction 2
Value 2: Maximum outstanding split transaction 3
Value 3: Maximum outstanding split transaction 4
Value 4: Maximum outstanding split transaction 8
Value 5: Maximum outstanding split transaction 12
Value 6: Maximum outstanding split transaction 16
Value 7: Maximum outstanding split transaction 32
See the definition for the average maximum outstanding split
transactions.
For simplicity, OSPM could use the Average Maximum Outstanding Split Transactions value as the
Maximum Outstanding Split Transactions register value in the PCI-X command register for each
PCI-X device. Another alternative is to use a more sophisticated policy and the Total Maximum
Outstanding Split Transactions Value to gain even more performance. In this case, the OS would
examined each PCI-X device that is directly attached to the host bridge, determine the number of
outstanding split transactions supported by each device, and configure each device accordingly. The
goal is to ensure that the aggregate number of concurrent outstanding split transactions does not
exceed the Total Maximum Outstanding Split Transactions Value: an integer denoting the number of
concurrent outstanding split transactions the host bridge can support (the minimum value is 1).
This object does not address providing additional information that would be used to configure
registers in bridge devices, whether architecturally-defined or specification-defined registers or
device specific registers. It is expected that a driver for a bridge would be the proper implementation
mechanism to address both of those issues. However, such a bridge driver should have access to the
data returned by the _HPX object for use in optimizing its decisions on how to configure the bridge.
Configuration of a bridge is dependent on both system specific information such as that provided by
the _HPX object, as well as bridge specific information.
6.2.9.3 PCI Express Setting Record (Type 2)
The PCI Express setting record contains the setting type 2, the current revision 1 and the type/
revision specific content (the control registers as listed in the table below) to be used when
configuring registers in the Advanced Error Reporting Extended Capability Structure or PCI Express
Capability Structure for the PCI Express devices.
The Type 2 Setting Record allows a PCI Express-aware OS that supports native hot plug to
configure the specified registers of the hot plugged PCI Express device. A PCI Express-aware OS
that has assumed ownership of native hot plug (via _OSC) but does not support or does not have
ownership of the AER register set must use the data values returned by the _HPX object‘s Type 2
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