Advanced Configuration and Power Interface Specification

Advanced Configuration and Power Interface Specification
Note: OSPM may override the settings provided by the _HPX object’s Type2 record (PCI Express
Settings) when OSPM has assumed native control of the corresponding feature. For example, if
OSPM has assumed ownership of AER (via _OSC), OSPM may override AER related settings
returned by _HPX.
Note: The _HPX object may exist under PCI compatible buses including host bridges except when the
host bridge spawns a PCI Express hierarchy. For PCI Express hierarchies, the _HPX object may
only exist under a root port or a switch downstream port.
Note: Since error status registers do not drive error signaling, OSPM is not required to clear error status
registers as part of _HPX handling.
6.2.9.1 PCI Setting Record (Type 0)
The PCI setting record contains the setting type 0, the current revision 1 and the type/revision
specific content: cache-line size, latency timer, SERR enable, and PERR enable values.
Table 6-173 PCI Setting Record Content
Field Object Type Definition
Header:
Type Integer 0x00: Type 0 (PCI) setting record.
Revision Integer 0x01: Revision 1, defining the set of fields below.
Cache-line size Integer Cache-line size reported in number of DWORDs.
Latency timer Integer Latency timer value reported in number of PCI clock cycles.
Enable SERR Integer When set to 1, indicates that action must be performed to enable SERR
in the command register.
Enable PERR Integer When set to 1, indicates that action must be performed to enable PERR
in the command register.
If the hot plug device includes bridge(s) in the hierarchy, the above settings apply to the primary side
(command register) of the hot plugged bridge(s). The settings for the secondary side of the bridge(s)
(Bridge Control Register) are assumed to be provided by the bridge driver.
The Type 0 record is applicable to hot plugged PCI, PCI-X and PCI Express devices. OSPM will
ignore settings provided in the Type0 record that are not applicable (for example, Cache-line size
and Latency Timer are not applicable to PCI Express).
6.2.9.2 PCI-X Setting Record (Type 1)
The PCI-X setting record contains the setting type 1, the current revision 1 and the type/revision
specific content: the maximum memory read byte count setting, the average maximum outstanding
split transactions setting and the total maximum outstanding split transactions to be used when
configuring PCI-X command registers for PCI-X buses and/or devices.
Table 6-174 PCI-X Setting Record Content
Field Object Type Definition
Header:
Type Integer 0x01: Type 1 (PCI-X) setting record.
308 April, 2015 Version 6.0