Advanced Configuration and Power Interface Specification

Advanced Configuration and Power Interface Specification
Table 5-44 Multiple APIC Description Table (MADT) Format ............................................. 138
Table 5-45 Multiple APIC Flags .......................................................................................... 139
Table 5-46 Interrupt Controller Structure Types ................................................................. 139
Table 5-47 Processor Local APIC Structure ...................................................................... 140
Table 5-48 Local APIC Flags .............................................................................................. 140
Table 5-49 I/O APIC Structure ........................................................................................... 141
Table 5-50 Interrupt Source Override Structure ................................................................. 142
Table 5-51 MPS INTI Flags ................................................................................................ 142
Table 5-52 Non-maskable Source Structure ...................................................................... 143
Table 5-53 Local APIC NMI Structure ................................................................................ 143
Table 5-54 Local APIC Address Override Structure .......................................................... 144
Table 5-55 I/O SAPIC Structure ......................................................................................... 144
Table 5-56 Processor Local SAPIC Structure .................................................................... 145
Table 5-57 Platform Interrupt Sources Structure ................................................................ 146
Table 5-58 Platform Interrupt Source Flags........................................................................ 147
Table 5-59 Processor Local x2APIC Structure .................................................................. 147
Table 5-60 Local x2APIC NMI Structure ............................................................................ 148
Table 5-61 GICC Structure Format..................................................................................... 149
Table 5-62 GICC CPU Interface Flags ............................................................................... 151
Table 5-63 GIC Distributor Structure .................................................................................. 152
Table 5-64 GIC MSI Structure ........................................................................................... 152
Table 5-65 GIC MSI Frame Flags....................................................................................... 153
Table 5-66 GIC Redistributor Structure ............................................................................. 153
Table 5-67 GIC Interrupt Translation Service Structure ..................................................... 154
Table 5-68 Smart Battery Description Table (SBST) Format.............................................. 155
Table 5-69 Embedded Controller Boot Resources Table Format....................................... 156
Table 5-70 Static Resource Affinity Table Format .............................................................. 158
Table 5-71 Processor Local APIC/SAPIC Affinity Structure ............................................... 159
Table 5-72 Flags – Processor Local APIC/SAPIC Affinity Structure................................... 159
Table 5-73 Memory Affinity Structure ................................................................................. 160
Table 5-74 Flags – Memory Affinity Structure..................................................................... 160
Table 5-75 Processor Local x2APIC Affinity Structure ....................................................... 161
Table 5-76 GICC Affinity Structure ................................................ 161
Table 5-77 Flags – GICC Affinity Structure......................................... 162
Table 5-78 SLIT Format...................................................................................................... 162
Table 5-79 Corrected Platform Error Polling Table Format ................................................ 163
Table 5-80 Corrected Platform Error Polling Processor Structure ...................................... 164
Table 5-81 Maximum System Characteristics Table (MSCT) Format................................. 165
Table 5-82 Maximum Proximity Domain Information Structure ......................................... 166
Table 5-83 RASF Table format ........................................................................................... 166
Table 5-84 RASF Platform Communication Channel Shared Memory Region .................. 167
Table 5-85 PCC Command Codes used by RASF Platform Communication Channel ..... 168
Table 5-86 Platform RAS capabilities bitmap ..................................................................... 168
Table 5-87 Parameter Block Structure for PATROL_SCRUB ............................................ 169
Table 5-88 MPST Table Structure ...................................................................................... 173
Table 5-89 PCC Command Codes used by MPST Platform Communication Channel ..... 174
Table 5-90 MPST Platform Communication Channel Shared Memory Region .................. 174
xxxiv April, 2015 Version 6.0