Advanced Configuration and Power Interface Specification

ACPI Software Programming Model
5.6.3 Fixed Event Handling
When OSPM receives a fixed ACPI event, it directly reads and handles the event registers itself. The
following table lists the fixed ACPI events. For a detailed specification of each event, see Section 4,
“ACPI Hardware Specification.”
Table 5-141 Fixed ACPI Events
Event
Power
management
timer carry bit
set.
Power button
signal
Sleep button
signal
RTC alarm
Wake status
System bus
master request
Global release
status
Comment
For more information, see the description of the TMR_STS and TMR_EN bits of the PM1x
fixed register block in Section 4.8.3.1, “PM1 Event Grouping,” as well as the TMR_VAL
register in the PM_TMR_BLK in Section 4.8.3.3, “Power Management Timer.”
A power button can be supplied in two ways. One way is to simply use the fixed status bit,
and the other uses the declaration of an ACPI power device and AML code to determine
the event. For more information about the alternate-device based power button, see
Section 4.8.2.2.1.2, Control Method Power Button.”
Notice that during the S0 state, both the power and sleep buttons merely notify OSPM
that they were pressed.
If the system does not have a sleep button, it is recommended that OSPM use the power
button to initiate sleep operations as requested by the user.
A sleep button can be supplied in one of two ways. One way is to simply use the fixed
status button. The other way requires the declaration of an ACPI sleep button device and
AML code to determine the event.
ACPI-defines an RTC wake alarm function with a minimum of one-month granularity. The
ACPI status bit for the device is optional. If the ACPI status bit is not present, the RTC
status can be used to determine when an alarm has occurred. For more information, see
the description of the RTC_STS and RTC_EN bits of the PM1x fixed register block in
Section 4.8.3.1, “PM1 Event Grouping.”
The wake status bit is used to determine when the sleeping state has been completed.
For more information, see the description of the WAK_STS and WAK_EN bits of the
PM1x fixed register block in Section 4.8.3.1, “PM1 Event Grouping.”
The bus-master status bit provides feedback from the hardware as to when a bus master
cycle has occurred. This is necessary for supporting the processor C3 power savings
state. For more information, see the description of the BM_STS bit of the PM1x fixed
register block in Section 4.8.3.1, “PM1 Event Grouping.”
This status is raised as a result of the Global Lock protocol, and is handled by OSPM as
part of Global Lock synchronization. For more information, see the description of the
GBL_STS bit of the PM1x fixed register block in Section 4.8.3.1, “PM1 Event Grouping.”
For more information on Global Lock, see Section 5.2.10.1, “Global Lock.”
5.6.4 General-Purpose Event Handling
When OSPM receives a general-purpose event, it either passes control to an ACPI-aware driver, or
uses an OEM-supplied control method to handle the event. An OEM can implement up to 128
general-purpose event inputs in hardware per GPE block, each as either a level or edge event. It is
also possible to implement a single 256-pin block as long as it’s the only block defined in the
system.
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