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Advanced Configuration and Power Interface Specification

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ACPI Software Programming Model<br />

accesses using the data element name. An Operation Region is a specific region of operation within<br />

an address space that is declared as a subset of the entire address space using a starting address<br />

(offset) <strong>and</strong> a length (see Section 19.6.97 “OperationRegion (Declare Operation Region)”). Control<br />

methods must have exclusive access to any address accessed via fields declared in Operation<br />

Regions. Control methods may not directly access any other hardware registers, including the ACPIdefined<br />

register blocks. Some of the ACPI registers, in the defined ACPI registers blocks, are<br />

maintained on behalf of control method execution. For example, the GPEx_BLK is not directly<br />

accessed by a control method but is used to provide an extensible interrupt h<strong>and</strong>ling model for<br />

control method invocation.<br />

Note: Accessing an OpRegion may block, even if the OpRegion is not protected by a mutex. For<br />

example, because of the slow nature of the embedded controller, an embedded controller<br />

OpRegion field access may block.<br />

There are eight predefined Operation Region types specified by ACPI as described in Table 5-137.<br />

Table 5-137 Operation Region Address Space Identifiers<br />

Name (RegionSpace Keyword)<br />

Value<br />

SystemMemory 0<br />

SystemIO 1<br />

PCI_Config 2<br />

EmbeddedControl 3<br />

SMBus 4<br />

SystemCMOS 5<br />

PCIBARTarget 6<br />

IPMI 7<br />

GeneralPurposeIO 8<br />

GenericSerialBus 9<br />

Reserved<br />

0x0A-0x7F<br />

In addition, OEMs may define Operation Regions Address Space ID types 0x80 to 0xFF.<br />

Operation region access to the SystemMemory, SystemIO, <strong>and</strong> PCI_Config address spaces is simple<br />

<strong>and</strong> straightforward. Operation region access to the EmbeddedControl address space is described in<br />

Section 12, “ACPI Embedded Controller <strong>Interface</strong> <strong>Specification</strong>”. Operation region access to the<br />

SMBus address space is described in Section 13, “ACPI System Management Bus <strong>Interface</strong><br />

<strong>Specification</strong>”. Operation region access to the CMOS, PCIBARTarget, IPMI, GenericSerialBus <strong>and</strong><br />

GeneralPurposeIO address spaces is described in the following sections.<br />

5.5.2.4.1 CMOS Protocols<br />

This section describes how CMOS battery-backed non-volatile memory can be accessed from ASL.<br />

Most computers contain an RTC/CMOS device that can be represented as a linear array of bytes of<br />

non-volatile memory. There is a st<strong>and</strong>ard mechanism for accessing the first 64 bytes of non-volatile<br />

RAM in devices that are compatible with the Motorola RTC/CMOS device used in the original IBM<br />

PC/AT. Existing RTC/CMOS devices typically contain more than 64 bytes of non-volatile RAM,<br />

<strong>and</strong> no st<strong>and</strong>ard mechanism exists for access to this additional storage area. To provide access to all<br />

Version 6.0 221

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