27.10.2015 Views

Advanced Configuration and Power Interface Specification

ACPI_6.0

ACPI_6.0

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

<strong>Advanced</strong> <strong>Configuration</strong> <strong>and</strong> <strong>Power</strong> <strong>Interface</strong> <strong>Specification</strong><br />

Field<br />

Subsystem RID 2 16 Subsystem Revision ID<br />

Byte0 is Non-Volatile Memory Subsystem Controller Revision<br />

Code defined by DDR4 SPD field 198 (per JEDEC SPD Annex<br />

L: Serial Presence Detect for DDR4 SDRAM NVDIMM<br />

Revision 0.5 or greater (Item 2220.01).<br />

Byte1 is reserved<br />

Reserved 6 18<br />

Serial Number 4 24 This field reflects the value of Module Serial Number (SPD<br />

Byte 325-328) from DDR4 SPD field as defined by JEDEC<br />

SPD Annex L: Serial Presence Detect for DDR4 SDRAM<br />

DDR4 SPD Document Release 2.<br />

Region Format<br />

<strong>Interface</strong> Code<br />

Number of Block<br />

Control Windows<br />

Size of Block<br />

Control Window<br />

Comm<strong>and</strong><br />

Register Offset in<br />

Block Control<br />

Window<br />

Size of Comm<strong>and</strong><br />

Register in Block<br />

Control Windows<br />

Status Register<br />

Offset in Block<br />

Control Window<br />

Size of Status<br />

Register in Block<br />

Control Windows<br />

NVDIMM Control<br />

Region Flag<br />

Byte<br />

Length<br />

Reserved 6 74<br />

Byte<br />

Offset<br />

Description<br />

2 28 Region Format <strong>Interface</strong> Code consists of a Class Code <strong>and</strong> an<br />

<strong>Interface</strong> Code as defined by JJEDEC SPD Annex L: Serial<br />

Presence Detect for DDR4 SDRAM NVDIMM Revision 0.5 or<br />

greater (Item 2220.01). Allows a common driver for the<br />

Memory Device region based on class code <strong>and</strong> interface code<br />

(regardless of vendor ID <strong>and</strong> device ID).<br />

2 30 Number of Block Control Windows must match the<br />

corresponding number of Block Data Windows. Fields that<br />

follow this field are valid only if the number of Block Control<br />

Windows is non-zero.<br />

8 32 In Bytes<br />

8 40 In Bytes.<br />

Logical offset. Refer to Note. The start of the subsequent Block<br />

Control Windows is calculated by adding Size of Block Control<br />

Window.<br />

8 48 In Bytes<br />

8 56 In Bytes.<br />

Logical offset. Refer to Note1. The start of the subsequent<br />

Block Control Window is calculated by adding Size of Block<br />

Control Window.<br />

8 64 In Bytes<br />

2 72 Bit [0] – set to 1 to indicate that the Block Data Windows<br />

implementation is buffered. The content of the data window is<br />

only valid when so indicated by Status Register.<br />

Note: Logical offset in structure above refers to offset from the start of NVDIMM Control Region. The<br />

logical offset is with respect to the device not with respect to system physical address space.<br />

210 April, 2015 Version 6.0

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!