Advanced Configuration and Power Interface Specification

Advanced Configuration and Power Interface Specification
SMBIOS Type 17) that contribute to the PM region. Typically, only block region requires the
interleave structure since software has to undo the effect of interleave.
5.2.25.3 Interleave Structure
Memory from DIMMs/NVDIMMs could be interleaved across memory channels, memory
controller and processor sockets. This structure describes the memory interleave for a given address
range. Since interleave is a repeating pattern, this structure only describes the lines involved in the
memory interleave before the pattern start to repeat.
Table 5-131 Interleave StructureI
Field
Byte
Length
Byte
Offset
Description
Type 2 0 2 - Interleave Structure
Length 2 2 Length in bytes for entire structure.
Interleave Structure Index 2 4 Index Number uniquely identifies the interleave
description – this allows reuse of interleave
description across multiple Memory Devices. Index
must be non-zero.
Reserved 2 6
Number of Lines Described
(m)
4 8 Only need to describe the number of lines needed
before the interleave pattern repeats
Line Size ( in bytes ) 4 12 e.g. 64, 128, 256, 4K
Line 1 Offset 4 16 Line 1 Offset refers to the offset of the line, in
multiples of Line Size, from the corresponding SPA
Range Base for the region in memory device.
Line 1 SPA = SPA Range Base + Region Offset +
(Line 1 Offset*Line Size). Line SPA is naturally
aligned to the Line size.
… 4
Line m Offset 4 16+((m-
1)*4)
Line m Offset refers to the offset of the line, in
multiples of Line Size, from the corresponding SPA
Range Base for the region in Memory Device.
Line m SPA = SPA Range Base + Region Offset +
(Line m Offset*Line Size) where m is the last line
number before the pattern repeats.
Line SPA is naturally aligned to the Line size.
5.2.25.4 SMBIOS Management Information Structure
This structure enables platform to communicate the additional SMBIOS entries beyond the entries
provided by SMBIOS Table at boot to the OS (e.g. Type 17 entries corresponding to hot added
Memory Devices).
Table 5-132 SMBIOS Management Information Structure
Field
Byte
Length
Byte
Offset
Description
208 April, 2015 Version 6.0