Advanced Configuration and Power Interface Specification

ACPI Software Programming Model
Table 5-125 Flag Definitions: SBSA Generic Watchdog Timer
Bit Field
Timer interrupt
Mode
Bit Number Description
Offset of bits
0 1 This bit indicates the mode of the timer interrupt
Timer Interrupt
polarity
1: Interrupt is Edge triggered
0: Interrupt is Level triggered
1 1 This bit indicates the polarity of the timer interrupt
1: Interrupt is Active low
0: Interrupt is Active high
Secure Timer 2 1 This bit indicates whether the timer is secure or non-secure
1: Timer is Secure
0: Timer is Non-secure
Reserved 3 29 Reserved, must be zero.
5.2.25 NVDIMM Firmware Interface Table (NFIT)
This optional table provides information that allows OSPM to enumerate NVDIMM present in the
platform and associate system physical address ranges created by the NVDIMMs. OSPM evaluates
NFIT only during system initialization. Any changes to the NVDIMM state at runtime or
information regarding dynamically added NVDIMMs are communicated using a _FIT method that
exists in ACPI namespace under NVDIMM devices. (See Section 9.20.)
The NVDIMM Firmware Interface Table (NFIT) consists of the following structures:
1. System Physical Address (SPA) Range Structure – Describes the system physical address ranges
occupied by NVDIMMs and the types of the regions
2. Memory Device to System Physical Address (SPA) Range Mapping Structure – Describes the
Memory Device's physical location, System Physical Address (SPA), NVDIMM region,
memory interleave and device state flags.
3. Interleave Structure – Describes the various interleave options active on the platform. Memory
Device to SPA Range Mapping Structure points to an Interleave Structure entry that describes
the memory interleave.
4. SMBIOS Management Information Structure – Describes SMBIOS Table entries. This allows
describing SMBIOS entries for hot added NVDIMMs.
5. NVDIMM Control Region Structure – Describes the NVDIMM and if applicable, Block Control
Window
6. NVDIMM Block Data Window Structure – Describes the Block Data Window for a Block
capable NVDIMM.
7. Flush Hint Address Structure – Describes special system physical addresses that when written
help achieve durability for writes to a NVDIMM Region. Flush Hint Address support is platform
Version 6.0 201