Advanced Configuration and Power Interface Specification

Advanced Configuration and Power Interface Specification
Reserved 2 30 Reserved, must be zero.
Table 5-123 Flag Definitions: Common Flags
Bit Field
Bit Number Description
Offset of bits
Secure Timer 0 1 This bit indicates whether the timer is secure or non-secure
Always-on
Capability
1: Timer is Secure
0: Timer is Non-secure
1 1 This bit indicates the always-on capability of the Physical and
Virtual Timers implementation.
1: This timer is guaranteed to assert its interrupt and wake a
processor, regardless of the processor’s power state. All of the
methods by which an ARM Generic Timer may generate an
interrupt must be supported, and must be capable of waking the
processor.
0: This timer may lose context or may not be guaranteed to assert
interrupts when its associated processor enters a low-power state.
Reserved 2 30 Reserved, must be zero.
5.2.24.2 SBSA Generic Watchdog Structure
The SBSA Generic Watchdog is a Platform GT with built-in support for use as the Watchdog timer
on Server Base System Architecture (SBSA)-compliant platforms.
The format of the SBSA Generic Watchdog structure is shown in Table 5-124.
The link for SBSA is http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0029/
index.html.
Table 5-124 SBSA Generic Watchdog Structure Format
Field
Byte
Length
Byte
Offset
Description
Type 1 0 0x1 Watchdog GT
Length 2 1 28
Reserved 1 3 Must be zero
RefreshFrame Physical
Address
WatchdogControlFrame
Physical Address
8 4 Physical Address at which the RefreshFrame block is
located
8 12 Physical Address at which the Watchdog Control Frame
block is located
Watchdog Timer GSIV 4 20 GSIV for the SBSA Generic Watchdog timer
Watchdog Timer Flags 4 24 Flags for the SBSA Generic Watchdog timer. See
Table 5-125
200 April, 2015 Version 6.0